DE2704560B1 - Data processing system with parallel provision and execution of machine commands - Google Patents

Description

The invention relates to a data processing system with several specialized microprograms controlled processors and with a common memory system in which the processing machine commands that are also virtually addressed are usually carried out in parallel by a preparation processor carries out command reading and address calculation for command operands, and one connected Executive processor "takes over the actual execution of commands (" Electronic Computing Systems ", 1973, p. 60-65).

For the central units of commercial data processing systems, different structures are known for the processing devices, depending on the performance class. In addition to processors with a purely sequential command processing, ie a strict sequence of functions "execution of a / menu machine command", "reading of the following (h + 1) -th machine command", "execution of the ι (η \ - l) -th machine command" etc., processors with overlapping instruction processing are also known. This makes use of the fact that a processing cycle for a machine instruction can be divided into at least a preparation phase and an execution phase. In the case of such processors, the reading process for an (n f // th machine instruction is then carried out in parallel to the execution of a / menu machine instruction, where i> I can be.

In this group of data processing systems is ι also a facility for processing machines commands of different formats in one micropio to classify grammierteii data processing systems, which is proposed in German patent application P 25 57 787. Be in this facility ι Machine commands made available in a concealed manner, d. H. already during the execution of a preceding machine command read from the main memory in a processing unit and buffered in command buffers, width of the interface to the main memory. This is next to a Current command counter, which is the complete address of the one to be executed in the processing unit Contains machine instruction, a further pre-load instruction counter connected to it is provided. This contains the memory address of the next machine command to be read out from the memory system. A comparison direction is connected to each of the two command counters, which also has an address register of the storage system is connected. This allows the content of the command buffer to be valid monitor discontinuous modifications of the current command counter. This avoids storage conflicts, in which the memory content of machine commands that have already been read out during the execution of a previous machine command is changed again.

The parallel work in processing equipment of the highest performance class is even more pronounced, they are often implemented as so-called "pipeline" processors. The structure of such processing units is z. B. in the journal "Electronic Computing Systems", 1973, pages 60 to 65 in the article "Possibilities of accelerating a central unit through structural measures" are described. The commands are then processed in the manner of an assembly line, for which the term »pipeline« has become common Has. For the individual processing phases, such as reading a machine command, decoding, address calculation and provision of the instruction operand are each one or more processing stations intended. The machine commands cycle through the chain of these processing stations and are then transferred to an executive processor

is structured analogously. The Communication with the storage system of the data processing system often takes place via an autonomous storage access control handled the various memory accesses during the entire processing / cycle coordinate a machine command or the machine commands to be processed in parallel got to.

Such a command assembly line requires a high level of circuit complexity for parallel work during the deployment and execution phases to achieve that with each one as possible Machine cycle a machine command is finally executed. In each of these two phases are how described, generally several processing stations provided d. that is, there will be a relatively large number Machine commands with different processing statuses processed at the same time. The large number of these processors, which are powerful but very complex, is particularly disadvantageous possible memory or register conflicts. In addition, experience has shown that discontinuous modifications often occur a program sequence, z. B. in the event of program interruptions or fulfilled jump conditions, so that the machine instructions read into the assembly line in consecutive order are then included in all of these lall must be declared invalid.

This high effort is not justified for data processing systems of a medium performance class, that of "pipeline" processors for controlling queues and conflict monitoring necessary is. The invention is therefore based on the object of a powerful data processing system of the type mentioned at the beginning, to which the following requirements are made:

The microprograms running in the executive processor or in the preparation processor must not be mutually exclusive hinder each other, therefore the accesses of both processors to the memory system or to the internal working registers of the executive processor can be easily coordinated. With discontinuous Program modifications must be read and preprocessed commands with certainty from excluded from execution, command processing must be as low as possible at the jump target 7. time loss to be resumed. Memory and register conflicts themselves must be as simple as possible Recognized manner and, depending on this, read or read a modified machine command again. the address calculation and the provision of operands are repeated for him.

In the case of a data processing system of the type mentioned at the beginning, this object is achieved according to the invention solved by the features described in the characterizing part of the main claim.

The executive processor and the editing processor use a common register memory, which is implemented in the executive processor. This has the advantage that a modified in the executive processor The contents of the register do not also include a modification in an otherwise required corresponding register of the Editing processor means. Furthermore, the editing and executive processors can be a single one Use the interface to the storage system together without the need for an expensive priority control would be necessary. Also the monitoring of possible memory or register conflicts with the help of two Comparison facilities is relatively simple because instead of a sophisticated monitoring method, it is relative criterion that is easy to implement is used for machine commands that are not consecutive in the memory system suppress parallel processing.

A major factor in this is that the editing processor does not have any memory operands of a machine instruction are read in advance, but only their effective memory addresses are provided. Even register operands only become direct

κι provided if this is already within a short time The deployment phase is possible or, on the other hand, it is not within the execution phase of a machine command could be read without additional expenditure of time.

Finally, the hierarchically structured microprogram control is of particular advantage for the Executive and editing processors from the loadable microprogram memory. The micro programs of the executive processor give control commands for reading a memory word at a suitable point or the register memory by the editing processor, this can cause mutual interference of the executive and editing processors on the storage system or on the register memory are excluded will. In the format of the executive processor's microinstructions, there are only two additional further bit positions are required, so that this advantage is achieved with very little effort.

Nevertheless, the microprogram memory of the executive processor is not connected to the detailed control of the Editing processor is loaded, which means a considerable broadening of the microinstruction format because a small state control memory is also provided in the preparation processor. In order to

i) the preparation processor is autonomous in relation to it the executive processor and can independently and depending on the needs of the acceptance of the Control commands transferred to the executive processor decide. Developments of the invention are in Subclaims characterized and are in the following description of an embodiment the invention explained in more detail.

For the description of this exemplary embodiment, the drawing serves as an explanation, and shows

Fig. 1 in a block diagram schematically the structure of a data processing system in which a Processor system according to the invention can be used,

F i g. 2 and F i g. 3 together show the embodiment of the preparation processor according to the invention and to it

functional units of the data processing system connected in this way,

F i g. 4 and 5 show the sequence of the processing phase of the machine commands to be provided on the basis of function diagrams.

For a better understanding of the subject matter of the invention, FIG. 1 shows a block diagram of a data processing system, of which a device for processing commands forms part. The Anaige is divided into three larger functional units, a storage system S-SYST, a processor system P-SYST and an input / output system E / O-SYST.

The memory system S-SYST contains a main memory, preferably designed as a semiconductor memory, with a plurality of memory modules SP-M, which are controlled independently of one another via a main memory controller AST. A modular PSP buffer memory is also attached to this

connected. In the typical operating case, this memory hierarchy allows more than 95% of all memory accesses to be served from the high-speed buffer memory PSP and thus to significantly reduce the effective access and cycle time of the S-SYST memory system.

As a processing system, the processor system P-SYST contains at least one executive processor EP and a processing processor UP integrated therewith, to which a microprogram load memory MPL is assigned. This contains the entire functional micro-programs and can be designed, for example, as a flexible magnetic disk.

Finally, the I / O- SYST input / output system can also be microprogram-controlled and, for this purpose, possibly also use the loadable microprogram memory WCM. In addition to an input / output control I / O-ST byte and block multiplex channels BY-MUX or BL-MUX, which are functionally to be regarded as special data transmission processors in which the input / output processes are carried out independently of the processing system Run channel programs in a controlled manner. The input / output control I / O-ST coordinates these data transfer procedures according to priority aspects. 2 ">

According to this overview described with reference to FIG. 1, the processing system and in particular the integrated processing processor IIP are of interest in the present context, since microprogrammed processing processors such as the executive processor EP can be assumed to be known per se. Only for reasons of space is the preparation processor UP in two separate figures. 2 and 3 shown. Both figures contain, as far as is necessary for understanding, in addition to i% details of the processing processor // fauch schematically indicated further functional units of the data processing system, which are clearly highlighted here from the drawing by a dash-dotted border in order to establish the connection.

The editing processor IIP integrated in the executive processor EP is to execute parallel to the processing of a machine command in the following function, which abbreviates the command execution, for the following machine commands I (n + / ^:

Reading of commands l (n + i) with / = 2 ... 8 from the storage system S-SVST in a command buffer; Provision of register operands for the instruction I (n + \);

Calculation of effective memory addresses for the ^5UE or the memory operand of the instruction

Providing the first microinstruction for the instruction I (n + \).

In general, this can reduce the time it takes for the command to provide read access to Register operands and for address calculation can be saved.

According to FIG. 2, the Aufbereifjngsprczessor IIP contains a current command counter P made up of counter flip-flops, in which the effective address of a machine command to be executed is stored. Since, as will be explained later, the command list of the data processing system includes commands with a length of two, four or six bytes, this command counter P is to be modified in the conventional manner by ± 2, ± 4 or ± 6. An analog pre-load command counter PPF is also connected to it, which is 3 byte wide and has an analog structure. This contains an effective memory address for reading commands. Its counter reading therefore usually has a lead in relation to the reading of the current command counter P , which in this exemplary embodiment can be a maximum of 20 bytes. This command counter can be modified by + 2, +4 and +8. Its lead over the status of the current command counter P is displayed in a lead counter VLZ, which is designed as an up / down counter with a width of 4 bits. Its content is decreased by 1, 2 or 3 depending on the length of the machine command to be executed. Conversely, the count of the forward counter is increased by 1, 2 or 4 when a new command word is read from the S-SYST memory system.

Two memory address comparators 5V1 and SV2 are also assigned to both command counters P and PPF. During all write operations in the S-SYST memory system, these compare the address for a machine command in the respectively connected command counter P or PPF with a memory address that is contained in a 3-byte-wide memory address register MA . Like a memory data register MD with a length of 8 bytes, this register is arranged in the executive processor EP.

In FIG. 2 it is indicated schematically that the memory address register MA can be loaded from the preload instruction counter PPF, but also internally from the executive processor EP via memory address lines SAL. Its output is connected to the S-SKST storage system. During a read operation, the memory content defined by this register is read out and transferred to the memory data register MD, but also via a memory data line SDL 1 to the integrated editing processor IIP . For memory accesses by the executive processor EP , memory data to be written are transferred to the memory data register MD via wide memory data lines SDL 2 or read memory data are transferred to third memory data lines SDL 3 in the executive processor EP . If the executive processor EP now performs a write access to the S-SYST memory system, a memory conflict is possible each time. Such a memory conflict, in which a machine command that has already been read out in advance is written again, is determined by the two memory address comparators SV1 and 5V2 and indicated by a conflict signal MC . The forward counter VLZ is set to zero by the internal control of the integrated preparation processor IIP , even if the jump conditions are fulfilled, and the machine command with the address transferred to the memory address register MA is read at the jump destination. When the forward counter VLZ is set to zero , all machine commands transmitted in advance are considered invalid.

In Fig. 3 shows, in addition to further devices of the integrated preparation processor IIP, above all a byte-containing command buffer IB with five registers, each 4 byte wide, arranged in four stages. In the first stage, two buffer registers IBD or IBE receive a double command word via the first memory data line SDL 1 directly from the memory system S-SYST . In the second stage, a further buffer register IBC takes over the content of one of the two buffer registers of the first stage and transfers it

809 521/500

a buffer register IBB of the third stage and to a further buffer register IBA in the fourth stage.

As already indicated, the machine instructions have a format of two, four or six bytes and can therefore be aligned with a word or half-word boundary. The alignment of a machine command to be processed can be recognized from the status of bit positions 29 and 30 in the current command counter P, as will be explained later. This bit combination is evaluated in order to read out a machine command from the command buffer IB. So z. B. in the case of a machine command with a format of 6 bytes aligned on a word boundary WG , the complete contents of the buffer register IBA of the fourth stage and the first two bytes 0 and 1 from the buffer register IBB of the third stage. If, on the other hand, such a command is aligned with a half-word boundary HWG , only the two bytes 2 and 3 and the buffer register IBB of the third stage are taken from the buffer register IBA of the fourth stage, all four cached bytes 0 to 3.

Three multiplexers are assigned to the command buffer IB for this read control. Command fields for address calculation are output via a first multiplexer D-MLJX for distance addresses with a width of 12 bits. A second multiplexer OM UX is used to read out the operation code of a machine command and the register length encryption with 1 byte each. Such data are to be regarded as tax data in the strict sense of the word; Lines on which such data are transported are therefore shown with broken lines for identification. The control data read out via the second multiplexer OMUX are, among other things, fed directly to the executive processor EP , which is only indicated schematically in FIG. 3, in order to initiate the microprogram required there for processing the machine command read out.

A third multiplexer R-MUX for registration addresses is 4 bits wide, is used to extract register address fields of the next machine instruction from the buffer registers IBA or IB of the fourth or third stage and is connected on the output side to the executive processor EP to control a register memory ÄSP. All internal working registers of the executive processor £ 7 * are summarized there.

In addition, a second comparison device, which is also connected to this register memory RSP , is connected to this third multiplexer R-MUX for register addresses. It consists of two register address comparators RVX and RV2, which compare the write addresses with the register addresses used to prepare a machine command for all write operations in the register memory. If a comparison is positive, this means that when an n- th machine instruction is executed, a register content is changed for a subsequent (n + 1) -th machine instruction, ie a register conflict occurs. A second conflict signal RC then emitted is used to initiate the repetition of the preparation for the (n + lj-th machine command that has taken place in the preparation processor IIP up to that point).

An address computer unit AAD with a 24-bit binary adder is also provided in the integrated preparation processor IIP. This is fed on the one hand from the multiplexer D-MUX for distance addresses and on the other hand from a register RD for register addresses. The latter is in turn connected to the register memory RSP of the executive processor EP and accepts the base and index addresses read from the register memory RSP or, in the case of pure register commands, also directly the register operands. Via the first multiplexer D-MUX , the binary adder receives the offset addresses or the result of a first address calculation from the first of two to the

ίο Binary adder AAD connected address buffer registers ABA or ABB delivered. During the address calculation itself, 12-bit wide offset addresses are padded to 24 bits with leading zeros, from the information coming from the register RD for register addresses.

I) mation, the more significant 8 bits are not included in the calculation. The result is an effective address 24 bits wide, which is stored in one of the two address buffer registers ABA or ABB , which act as a queue.

The different formats of machine commands have already been pointed out several times above, but have not yet been explained in more detail, that five groups of machine commands are distinguishable above all with regard to the type of how and where the command operands are stored. In the following table 1 these five possible command types RR to SS are expressed in relation to the respective storage medium for the operands:

Table 1

Name of command type

code

RR Register Register Instructions 00

RX register storage instructions with 01

Indexing option

RS Register Save Instructions 10

SI memory direct operand instructions 10

55 Speicner memory commands 11

The abbreviations mean
R: the register address of an operand,
X: the index register address of an operand,
/: a direct operand contained in the instruction,
5: the memory address of an operand.
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RR commands have a length of 2 bytes or - in other words - a half word. RX, RS and 5 / commands are one word, i.e. 4 bytes. Finally, 55 commands consist of 3 half-words or 6 bytes. In every machine command, this command format - referred to as code in Table 1 - is encoded in two bit positions of the operation field with 00, 01 and 11 respectively. The necessary information for all necessary route switching can be derived from this bit combination. For a machine command to be provided, it is in the current command counter Pan at the bit positions P29, P30 mentioned.

For the provision of the data of a machine command in the address buffer registers ABA or AB , the following can be determined:

In the case of ÄÄ commands, the first operand R 1 from the first address buffer register ABA and the second operand R 2 from the second address buffer register ABB are transferred to the executive processor EP . With RX, RS and 5 / commands, the address for the memory operand is read from the second address buffer register ABB and with 55 commands the address for the first memory operand is in the first address buffer.

it

Register ABA and the one for the second memory operand in the second address buffer register ABB. It is stipulated that all eight more significant bit positions are set to zero if the two address buffer registers contain addresses.

In the introduction it was explained that the integrated preparation processor UP also uses the directly assigned loadable microprogram memory WCM of the executive processor EP , above all in order to avoid access conflicts. However, in order not to unnecessarily enlarge the format of the microinstructions of the loadable microprogram memory WCM , the entire control of the integrated editing processor IIP is not taken over in detail. A status control memory ZS-ROM , which is designed as a read-only memory, is provided for detailed control of the integrated preparation processor. Only a relatively small microinstruction format of 2 bytes, for example, is required for this, so that overall a storage capacity of 1 Kbit is sufficient for the microprograms to be stored there.

The start address of a microprogram of the detailed control is formed as a function of the instruction format of the machine instruction and its relative position in a memory double word, ie its alignment in an address counter SRA assigned to this read-only memory. For this purpose, this address counter is connected to the command counter P via a 2-bit wide control line, from which it receives the two bit positions P29, 30. The address counter SRA is connected via a further 2-bit wide control line to the output of the multiplexer O-MUX for the operation code, which supplies it with two bit positions IBO, 1 as information about the operation code. The two least significant bit positions of the address counter SRA are padded with zeros. The address counter SRA is also directly connected to the loadable microprogram memory WCM of the executive processor EP via a 1-bit wide third control line. As indicated, a control command “read register memory” RRS can thus be transferred to the address counter SRA , with which the microprogram address is advanced in the state control memory ZS-ROM.

Microprogram controls are known per se, which is why the actual detailed control through the 16-bit microinstructions in the state control memory is not included in FIGS. 2 and 3 for reasons of clarity. Only one special feature is highlighted in FIG. 3: Another read-only memory is the microprogram memory WP-ROM of a maintenance processor, which is otherwise not shown in detail. There, maintenance functions are stored that are carried out by the operating system of the data processing system. During the execution of the command - i.e. in the normal program sequence - these are not required. This is utilized and will be stored in this memory, the respective first microinstructions by proceeding in the executive processor EP microprograms for the instruction execution, it is achieved that the first microinstruction of a machine instruction, such as the (n + l) -th machine instruction of already during the execution previous n-th machine command provided and can be transferred to the executive processor at the end of the execution of this machine command. The microprograms for command processing in the executive processor EP can be controlled by the integrated

Preparation processor IIP, can be seamlessly joined together.

The device described with reference to FIGS allows processing of the functions »reading a machine command«, overlapping in three stages, "Address calculation, provision of a machine command" and "Execution of a machine command". The first two functions are overlapping in the integrated for successive machine commands Processing processor // around the third function, in the steady state, overlapping again, executed in the executive processor fP.

The sequence in the first two stages is explained in more detail below with reference to FIGS. Both flow charts are related, the transitions of individual flow branches are therefore designated with identical letters A, B and C , respectively. Each block represents an elementary operation EO of a microprogram that runs either from the loadable microprogram memory WCM, the state control memory ZS-ROM or the microprogram memory WP-ROM of the maintenance processor. To make this clear, the individual elementary operations EO are, if necessary, additionally defined with these corresponding designations.

Discontinuous modifications of the current command counter P are caused, for example, by a program interruption or a fulfilled jump command. As already explained, the provision of the following machine command must then start again. As in Fig. 4, this process is controlled by the executive processor EP. If the jump condition / is met with the last elementary operation EO η when processing a machine command (s), a microprogram from the loadable microprogram memory WCM starts with the following elementary operation EO 1. It includes an address translation AT door, the content of the current command counter P and the transfer of this register content to the preload command counter PPF.

In the elementary operation EO 2 , the function »Read command double word« RDI runs from the memory system S-SYSTab, the content of the pre-load command counter PPF is increased by eight and the next effective memory address is set.

In the third elementary operation EO3 , the read command double word / D Win is transferred to the command buffer IB . In addition, the loadable microprogram memory WCM issues a control command PF “Read memory system” to the integrated processing processor IIP , which then reads the next double-word command.

At this point in time, the machine command I (n + \) already read into the command buffer IB is not yet made available in the address buffer registers ABA or ABB . Therefore, in the executive processor EP, ie on the execution level, in the subsequent elementary operation EO 4, a possibly repeated zero operation NOOP follows . At the same time, another control command RRS "Read register memory" is transferred to the integrated preparation processor IIP , so that an elementary operation then runs in parallel on the preparation level, which is controlled from the state control memory ZS-ROM. The first machine command I (n + 1) read is further processed step by step until it is made available for processing in the executive processor EP .

In detail, there can be three process branches A, B and C in the integrated preparation processor HP , which are shown in FIG. 5 are shown. These sequences for the second functional level, ie on the provision level, are dependent on the command type RR, > RX, RS, Sl or SS and on the alignment of a command in the memory double word. In the case of a machine command aligned with a double word boundary DG ^, the two bit positions 29 and 30 in the current command counter Pin have the bit combination m 00 in this example. In one orientation on a word boundary WG the bit combination means 10 and at a position on one of the two half-word boundaries HWG 1 and HWG 2 in the double word names of the bit combinations 01 and 11. The type of bit combination determines one of the ι> three outlet branches A, B or C .

In the most important case, branch A, a machine command to be processed is aligned with a double word boundary DWG or the first half word boundary HWG 1; this is always the case in the steady m state, while a different alignment is possible after discontinuous modifications. For each machine instruction type, the processes taking place during the three elementary operations £ 041, EO 51 and £ 061 of this branch A are in the individual appropriately marked blocks in FIG. 5 specified.

Let us first consider ÄÄ commands. With this type of instruction, the two operands are in registers R 1 and R 2 of the register memory RSP and are thus defined by register addresses. In the first elementary operation EO 41 of this branch of the process, the control command RRS "read register memory" issued by the loadable microprogram memory WCM is taken over by the integrated preparation processor HP , and the content of the second register Rl is transferred from the register memory RSP to the register RD for register operands. In the second elementary operation EO 5 \ , this read register content is entered in the second address buffer register ABB . In addition, triggered by a further control command RRS, the other register operand is now also read from register R 1 and transferred to the first address buffer register ABA in the next elementary operation £ 061. Both register operands are now made available, thereupon a ready signal SRR is generated in the integrated preparation processor HP. This triggers the control of the microprogram memory WP-ROM of the maintenance processor and reads out the first elementary operation EOX ' on the "0" execution level for the machine command I (n + \) provided . The further execution of the command then runs, controlled from the loadable microprogram memory WCM , in the executive processor EPab.

For the other command groups, the three elementary operations EO 41, EO 51 and EO 61 each have an analog, but type-specific preparation. In this context, however, a special feature should be noted: The other machine instructions can also contain operands that are stored in an «, o operand register Ri or Rl or in an index register XX or Xl of the register memory RSP . Except in the case of /? Commands, however, the editing processor IIP does not provide such an operand directly, but only its register address, and this operand is read by the executive processor EP during the processing phase. This has the major advantage that this one

40

4> considered process branch A only ever requires the three elementary operations £ 041, 51 and 61, especially since it is easier to carry out this access to the register memory RSP in one of the elementary operations of the execution phase in parallel with another step. In Fig. 5, therefore, only the more extensive address calculations for the other operands are shown for the sake of simplicity.

In the case of SS commands, for example, an effective memory address must be determined for both operands. For this purpose, in the three elementary operations, the contents of two base registers BX and B 2 are read out one after the other from the register memory RSPd 'and are each transferred to the register RD for register operands. In the address arithmetic unit AAD , the associated offset address Dl or D 2 of the operand is added to the respective base address. The results are entered in one of the two address buffer registers ABA or ABB . At the end of the third elementary operation, this is fulfilled for both memory operands and a ready signal SSS for this type of instruction is generated in the integrated preparation processor IIP.

The provision of commands for RX, RS and 5 / commands should therefore be immediately recognizable from the flow chart. This also applies to the other two process branches B and C, in which the machine command is aligned with a word boundary WG or the second half-word boundary HWG1. A further detailed description of the elementary operations £ 042 to £ 072 or the elementary operations EO 43 to £ 083 therefore no longer appears necessary for a complete understanding.

Returning to the illustration in FIG. 4, it should only be pointed out that the preamble with the elementary operations £ 01 to £ 03 - as already indicated - is only required after discontinuous modifications in the current command counter Per. In the normal case, with constructive intermediate storage of successive machine commands in the command buffer IB, this introductory phase is skipped or already carried out during the processing phase of preceding machine commands. _

In Fig. 4, this is indicated by a control signal / which is evaluated together with the readiness signal 5. If both signals occur, the last elementary operation £ 0 η of the processing phase of the machine command In is immediately followed by the processing phase of the subsequent machine command I (n + \) with the first elementary operation EOX ' . However, if the readiness signal S is missing after the last elementary operation EO η has elapsed, then zero operations NOOP are faded in until this signal occurs.

From the above explanations it can be seen that the microprograms stored in the loadable microprogram memory WCM also trigger the processes in the integrated editing processor IIP via certain signals, in particular the control commands RRS and PF. However, it is left to the integrated preparation processor IIP whether it accepts the signals offered or not. In this way it is possible on the one hand to coordinate accesses of the integrated editing processor IIP and the executive processor EP to common storage devices, such as to the storage system S-SYST or to the register memory RSP , and thus to simplify the controls in the interfaces.

On the other hand, the processes still run in the

15 16

Both processors IIP and EP separately gain from one another compared to conventional, with one processing and independently from each other, so they can be executed in real parallel with processing processor- equipped central units. As the small scope of the detailed control without - as in the case of the "pipeline" principle for the integrated preparation processor IIP and built-up machines - reveals its circuit structure after each processing , such a ί station in buffer facilities is queued and actual parallel work is already carried out with a small amount of queues - Need to become,
wall possible. It brings a significant performance

Add 5 sheets of Zeicliiuiimcn

Claims (9)

Patent claims: 1. Data processing system with several specialized processors controlled by microprograms and with a common memory system in which the processing of also virtually addressed machine commands usually takes place in parallel, with a processing processor performing the command reading and the address calculation for command operands, and a connected executive processor the actual Takes over command execution, characterized in that a loadable microprogram memory (WCM ) belonging to the executive processor (EP) also controls the process of making available machine commands in the preparation pio / essor (IIP) in such a way that simultaneous accesses by the preparation processor and the executive processor / and its register memory ( RSP) or / to storage system (S-SYSI) avoided that the editing processor has its own small status control memory (ZM-ROM) , which stores the microprograms for the detailed control of the editing processor e nthalt and its read operations are triggered by control signals emitted by the loadable microprogram memory of the executive processor, so that the processing processor also has an instruction memory (IB) built up from several buffer registers (ΙΒΛ to IBl. ) for the temporary storage of those read in advance from the memory system Has machine commands, an address computer (AAD, ABB, ΛBA) for providing register operands or effective addresses of memory operands is connected to them and that two comparison devices (SVl , SV2 or RVi, RV2) are arranged, which compare memory or register addresses with the corresponding addresses in anticipation of machine commands read in advance and if they match e in conflict signal (MC or RC) , whereby machine commands read in advance in the preparation processor are invalid and then read again. 2. Data processing system according to claim 1, characterized in that the preparation processor (IIP) for pre-reading machine commands from the memory system (S-SYST) also uses a memory address register (MA) arranged in the executive processor (I: P) and for this purpose in addition to a current command counter (P) with the effective address of a machine command (In) to be executed has a pre-loading command counter (PPF) connected to it, which when pre-reading machine commands (l (n + m)) has a corresponding value compared to the count of the current command counter Has lead, the absolute size of which is recorded in a lead counter (VLZ) assigned to the pre-load command counter. 3. Data processing system according to claim 2, characterized in that the comparison direction (SV \, SV2 ) provided in the preparation processor (IIP) contains two registers to avoid memory conflicts, which are sent to the current command counter (P) or to the pre-load command counter ( PPF) are connected and receive the effective addresses of machine commands stored there and which are also connected in parallel to the memory address register (MA) , so that during a write operation of the executive processor (EP) it can be determined by an address comparison in the comparison device whether the write operation Machine commands read in advance are detected and, in this case of conflict, the comparison device issues a conflict signal (MC) for Sthreiboperutionen in the memory system, with which the forward counter (VLZ) is set to zero and thus a renewed reading of the invalid in the command buffer (IB) cached machine commands are triggered d. 4. Data processing system according to one of claims 1 to 3, characterized in that the command buffer (IB) has buffer registers arranged in four stages, of which two registers (IBD or IBE) via a memory data line (SDL I) directly in the first stage are connected to the output of the memory system (S-SYSI) and receive a read memory double word that the outputs of these two buffer registers are connected in parallel to the inputs of a third Pulferregister (IBC) of the second stage, which is connected via a further buffer register f / ß £ y of the third stage is connected to the fifth buffer register (IBA) of the fourth stage. 5. Data processing system according to claim 4, characterized in that command errors which record the operational code of machine commands aligned at a half-word limit (HWCi) oiler a word limit (WCl) are assigned outputs of the fifth buffer register (MA) with the inputs of a multiplexer (O-MLIX ) are connected for the operation code, the outputs of which are connected to the executive processor (EP) for the transfer of the operation code of a provided machine command, that the command fields for offset addresses of command operands are assigned to outputs of the fourth and fifth buffer registers (IBA or IBB), a multiplexer (D-MVK) for distance addresses is connected, the outputs of which are connected to the address arithmetic unit (AAD) , and that a multiplexer (R-MUX) (Ur Register -Operand is connected, which via address lines with the in Execut The register memory (RSP) contained in the processor is connected. 6. Data processing system according to claim 5, characterized in that to avoid register conflicts to the multiplexer (R-MUX) for register operands, the second comparison device (RVt, RV2) is connected, the two registers for the addresses of the operands of the register Contains machine instruction to be processed and is also connected to the register memory (RSP) in the executive processor (EP) , so that during write operations of the executive processor in the register memory, the called address for an internal working register in the register memory with the addresses for register operands of the machine command to be provided is comparable and, in the event of a positive comparison, a conflict signal (RC) for .Schreiboperationen is issued in the register memory, which invalidates the previous preparation for the machine command concerned. 7. Data processing system according to claim 5 or 6, characterized in that the address arithmetic unit (AAD) connected to the multiplexer (DMUX) for distance addresses is designed w \ s binary addicrer, which also has the outputs of a register (RD) parallel to the outputs of this multiplexer for register operands are supplied, which on the other hand is connected to ilen register space (RSf) of the executive processor (EP) and that the outputs of the binary adder with two address buffer registers (AIiA, AIiIi) for register operands or effective addresses of operands of a provided machine instruction are connected and the outputs of these registers are connected to the executive processor, with the outputs of most of the two registers (AIiA) being fed back to the inputs of the binary adder via the multiplexer (D-MUX) for distance. H. Data processing system according to one of Claims 5 to 7, characterized in that the state control memory (ZS-ROM) provided for the detailed control of the processing processor (IIP ), which is designed as a fixed-value memory, is an address counter (.SYf.- l / is assigned to the machine command to be provided via a control line (IHO, I) with the multiplexer (O-MIIX) for the operational code for supplying a code via the I yp ties and the current command via a further control line (P29, JO) Belehlszähler (P) is connected, via which the alignment of the machine command to be provided in a memory double word at a double word, word, first or second Malbwortbegrenz'DWa WG, HWG I or HWG2) characterizing bit combination is transmitted and that the address counter above is also connected to a third control line, via the state control memory from the loadable microprogram memory (WCM) as the executive process ssors (EP) a control command »read register memory« (RRS) / can be monitored that triggers the reading of the next microinstruction. 9. Data processing system according to claim 8, characterized in that a microprogram memory of another processor of the data processing system, the maintenance processor is connected to the state control memory (ZS-ROM), from which after the last elementary operation of a microprogram with which the When a machine command is provided, the first microinstruction of the execution phase of the provided machine command is read out.