DE2155803C3 - Verfahren zum Herstellen einer integrierten Schaltung - Google Patents

Verfahren zum Herstellen einer integrierten Schaltung

Info

Publication number
DE2155803C3
DE2155803C3 DE2155803A DE2155803A DE2155803C3 DE 2155803 C3 DE2155803 C3 DE 2155803C3 DE 2155803 A DE2155803 A DE 2155803A DE 2155803 A DE2155803 A DE 2155803A DE 2155803 C3 DE2155803 C3 DE 2155803C3
Authority
DE
Germany
Prior art keywords
integrated circuit
formats
format
mask
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2155803A
Other languages
German (de)
English (en)
Other versions
DE2155803B2 (de
DE2155803A1 (de
Inventor
Jeffrey George Wappinger Falls Koens
Robert Donald Hopewell Junction Merillat
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2155803A1 publication Critical patent/DE2155803A1/de
Publication of DE2155803B2 publication Critical patent/DE2155803B2/de
Application granted granted Critical
Publication of DE2155803C3 publication Critical patent/DE2155803C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Hardware Redundancy (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Image Processing (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE2155803A 1970-11-23 1971-11-10 Verfahren zum Herstellen einer integrierten Schaltung Expired DE2155803C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US9197270A 1970-11-23 1970-11-23

Publications (3)

Publication Number Publication Date
DE2155803A1 DE2155803A1 (de) 1972-05-25
DE2155803B2 DE2155803B2 (de) 1979-09-27
DE2155803C3 true DE2155803C3 (de) 1980-07-17

Family

ID=22230560

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2155803A Expired DE2155803C3 (de) 1970-11-23 1971-11-10 Verfahren zum Herstellen einer integrierten Schaltung

Country Status (5)

Country Link
US (1) US3698072A (enExample)
JP (1) JPS5135352B1 (enExample)
DE (1) DE2155803C3 (enExample)
FR (1) FR2115167B1 (enExample)
GB (1) GB1302630A (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5465217A (en) * 1993-08-16 1995-11-07 Motorola, Inc. Method for automatic tab artwork building
US6760640B2 (en) * 2002-03-14 2004-07-06 Photronics, Inc. Automated manufacturing system and method for processing photomasks
US7640529B2 (en) * 2002-07-30 2009-12-29 Photronics, Inc. User-friendly rule-based system and method for automatically generating photomask orders
US7669167B2 (en) * 2002-07-30 2010-02-23 Photronics, Inc. Rule based system and method for automatically generating photomask orders by conditioning information from a customer's computer system
US6842881B2 (en) * 2002-07-30 2005-01-11 Photronics, Inc. Rule based system and method for automatically generating photomask orders in a specified order format
US20060122724A1 (en) * 2004-12-07 2006-06-08 Photoronics, Inc. 15 Secor Road P.O. Box 5226 Brookfield, Connecticut 06804 System and method for automatically generating a tooling specification using a logical operations utility that can be used to generate a photomask order

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3461547A (en) * 1965-07-13 1969-08-19 United Aircraft Corp Process for making and testing semiconductive devices
US3615466A (en) * 1968-11-19 1971-10-26 Ibm Process of producing an array of integrated circuits on semiconductor substrate

Also Published As

Publication number Publication date
FR2115167B1 (enExample) 1976-06-04
DE2155803B2 (de) 1979-09-27
FR2115167A1 (enExample) 1972-07-07
DE2155803A1 (de) 1972-05-25
GB1302630A (enExample) 1973-01-10
JPS5135352B1 (enExample) 1976-10-01
US3698072A (en) 1972-10-17

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Legal Events

Date Code Title Description
OD Request for examination
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee