DE2111633A1 - Verfahren zur Herstellung eines Oberflaechen-Feldeffekt-Transistors - Google Patents

Verfahren zur Herstellung eines Oberflaechen-Feldeffekt-Transistors

Info

Publication number
DE2111633A1
DE2111633A1 DE19712111633 DE2111633A DE2111633A1 DE 2111633 A1 DE2111633 A1 DE 2111633A1 DE 19712111633 DE19712111633 DE 19712111633 DE 2111633 A DE2111633 A DE 2111633A DE 2111633 A1 DE2111633 A1 DE 2111633A1
Authority
DE
Germany
Prior art keywords
source
drain
gate
layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19712111633
Other languages
German (de)
English (en)
Inventor
Schaefer Peter Charles
Howard Lawrence
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
General Electric Co
Original Assignee
General Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by General Electric Co filed Critical General Electric Co
Publication of DE2111633A1 publication Critical patent/DE2111633A1/de
Pending legal-status Critical Current

Links

Classifications

    • H10W74/47—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H10P95/00—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films

Landscapes

  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE19712111633 1970-03-19 1971-03-11 Verfahren zur Herstellung eines Oberflaechen-Feldeffekt-Transistors Pending DE2111633A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US2116170A 1970-03-19 1970-03-19

Publications (1)

Publication Number Publication Date
DE2111633A1 true DE2111633A1 (de) 1971-09-30

Family

ID=21802693

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19712111633 Pending DE2111633A1 (de) 1970-03-19 1971-03-11 Verfahren zur Herstellung eines Oberflaechen-Feldeffekt-Transistors

Country Status (3)

Country Link
US (1) US3670403A (enExample)
DE (1) DE2111633A1 (enExample)
FR (1) FR2083429B3 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115458399A (zh) * 2022-09-13 2022-12-09 中晟鲲鹏光电半导体有限公司 一种碳化硅晶圆的裂片方法

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3919008A (en) * 1970-12-02 1975-11-11 Hitachi Ltd Method of manufacturing MOS type semiconductor devices
US3793090A (en) * 1972-11-21 1974-02-19 Ibm Method for stabilizing fet devices having silicon gates and composite nitride-oxide gate dielectrics
US3853496A (en) * 1973-01-02 1974-12-10 Gen Electric Method of making a metal insulator silicon field effect transistor (mis-fet) memory device and the product
US3909320A (en) * 1973-12-26 1975-09-30 Signetics Corp Method for forming MOS structure using double diffusion
US3969165A (en) * 1975-06-02 1976-07-13 Trw Inc. Simplified method of transistor manufacture
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US5874766A (en) * 1988-12-20 1999-02-23 Matsushita Electric Industrial Co., Ltd. Semiconductor device having an oxynitride film
KR940009352B1 (ko) * 1990-07-09 1994-10-07 가부시끼가이샤 도시바 반도체 소자
US6004875A (en) 1995-11-15 1999-12-21 Micron Technology, Inc. Etch stop for use in etching of silicon oxide
US5830789A (en) * 1996-11-19 1998-11-03 Integrated Device Technology, Inc. CMOS process forming wells after gate formation
US20030021327A1 (en) * 2001-07-25 2003-01-30 Murry Stefan J. Semiconductor surface-emitting laser with integrated photodetector

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3475234A (en) * 1967-03-27 1969-10-28 Bell Telephone Labor Inc Method for making mis structures
US3566518A (en) * 1967-10-13 1971-03-02 Gen Electric Method for fabricating field-effect transistor devices and integrated circuit modules containing the same by selective diffusion of activator impurities through preselected portions of passivating-insulating films
US3541676A (en) * 1967-12-18 1970-11-24 Gen Electric Method of forming field-effect transistors utilizing doped insulators as activator source

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115458399A (zh) * 2022-09-13 2022-12-09 中晟鲲鹏光电半导体有限公司 一种碳化硅晶圆的裂片方法
CN115458399B (zh) * 2022-09-13 2025-01-03 中晟鲲鹏光电半导体有限公司 一种碳化硅晶圆的裂片方法

Also Published As

Publication number Publication date
FR2083429B3 (enExample) 1973-12-28
FR2083429A7 (enExample) 1971-12-17
US3670403A (en) 1972-06-20

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