DE19855488A1 - Testmustergenerator mit verbesserter Testsequenzverdichtung - Google Patents

Testmustergenerator mit verbesserter Testsequenzverdichtung

Info

Publication number
DE19855488A1
DE19855488A1 DE19855488A DE19855488A DE19855488A1 DE 19855488 A1 DE19855488 A1 DE 19855488A1 DE 19855488 A DE19855488 A DE 19855488A DE 19855488 A DE19855488 A DE 19855488A DE 19855488 A1 DE19855488 A1 DE 19855488A1
Authority
DE
Germany
Prior art keywords
test
errors
list
test sequence
sequences
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19855488A
Other languages
German (de)
English (en)
Inventor
John G Rohrbaugh
Jeffrey R Rearick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE19855488A1 publication Critical patent/DE19855488A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
DE19855488A 1998-02-20 1998-12-01 Testmustergenerator mit verbesserter Testsequenzverdichtung Withdrawn DE19855488A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/027,106 US6067651A (en) 1998-02-20 1998-02-20 Test pattern generator having improved test sequence compaction

Publications (1)

Publication Number Publication Date
DE19855488A1 true DE19855488A1 (de) 1999-09-09

Family

ID=21835718

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19855488A Withdrawn DE19855488A1 (de) 1998-02-20 1998-12-01 Testmustergenerator mit verbesserter Testsequenzverdichtung

Country Status (3)

Country Link
US (1) US6067651A (https=)
JP (1) JPH11281716A (https=)
DE (1) DE19855488A1 (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10034897A1 (de) * 2000-07-18 2002-01-31 Infineon Technologies Ag Adresszähler zur Adressierung von synchronen hochfrequenten Digitalschaltungen, insbesondere Speicherbauelementen
DE10034852A1 (de) * 2000-07-18 2002-02-07 Infineon Technologies Ag Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen
DE10137297A1 (de) * 2001-08-01 2003-02-20 Abb Patent Gmbh Verfahren zum Testen von Software-Robustheit
DE10210264B4 (de) * 2001-03-09 2007-05-10 Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto Ein Testvektorkomprimierungsverfahren
US8332715B2 (en) 2008-01-10 2012-12-11 Fujitsu Limited Test pattern generating method, device, and program

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US6295618B1 (en) * 1998-08-25 2001-09-25 Micron Technology, Inc. Method and apparatus for data compression in memory devices
US6732053B1 (en) * 1998-09-30 2004-05-04 Intel Corporation Method and apparatus for controlling a test cell
US6237117B1 (en) * 1998-09-30 2001-05-22 Sun Microsystems, Inc. Method for testing circuit design using exhaustive test vector sequence
US6314540B1 (en) * 1999-04-12 2001-11-06 International Business Machines Corporation Partitioned pseudo-random logic test for improved manufacturability of semiconductor chips
JP4334066B2 (ja) * 1999-06-29 2009-09-16 株式会社アドバンテスト パターン発生器及び電気部品試験装置
JP3734392B2 (ja) * 1999-10-29 2006-01-11 松下電器産業株式会社 半導体集積回路の故障検査方法及びレイアウト方法
US6578169B1 (en) * 2000-04-08 2003-06-10 Advantest Corp. Data failure memory compaction for semiconductor test system
US6865706B1 (en) * 2000-06-07 2005-03-08 Agilent Technologies, Inc. Apparatus and method for generating a set of test vectors using nonrandom filling
US7103816B2 (en) * 2001-01-23 2006-09-05 Cadence Design Systems, Inc. Method and system for reducing test data volume in the testing of logic products
US6886124B2 (en) * 2001-02-07 2005-04-26 Nec Corporation Low hardware overhead scan based 3-weight weighted random BIST architectures
US6845479B2 (en) * 2001-03-14 2005-01-18 Tality Uk Limited Method for testing for the presence of faults in digital circuits
US6865704B2 (en) * 2001-11-09 2005-03-08 Agilent Technologies, Inc. Scan multiplexing for increasing the effective scan data exchange rate
US7000141B1 (en) * 2001-11-14 2006-02-14 Hewlett-Packard Development Company, L.P. Data placement for fault tolerance
JP3803283B2 (ja) * 2001-11-21 2006-08-02 株式会社半導体理工学研究センター 集積回路のテストのための圧縮テストプランの生成、テスト系列生成およびテスト
US7437638B2 (en) 2002-11-12 2008-10-14 Agilent Technologies, Inc. Boundary-Scan methods and apparatus
US7032202B2 (en) * 2002-11-19 2006-04-18 Broadcom Corporation System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chains
US6989684B2 (en) * 2002-12-04 2006-01-24 Hewlett-Packard Development Company, L.P. System for and method of assessing chip acceptability and increasing yield
US6707313B1 (en) * 2003-02-19 2004-03-16 Agilent Technologies, Inc. Systems and methods for testing integrated circuits
US7024330B2 (en) * 2003-03-28 2006-04-04 Mitsubishi Electric And Electronics U.S.A., Inc. Method and apparatus for decreasing automatic test equipment setup time
JP3990319B2 (ja) * 2003-06-09 2007-10-10 株式会社アドバンテスト 伝送システム、受信装置、試験装置、及びテストヘッド
US7404109B2 (en) * 2003-06-12 2008-07-22 Verigy (Singapore) Pte. Ltd. Systems and methods for adaptively compressing test data
US7487420B2 (en) * 2005-02-15 2009-02-03 Cadence Design Systems Inc. System and method for performing logic failure diagnosis using multiple input signature register output streams
EP1701173B1 (en) * 2005-03-11 2008-08-20 Verigy (Singapore) Pte. Ltd. Error detection in compressed data
US8117513B2 (en) * 2005-03-30 2012-02-14 Lptex Corporation Test method and test program of semiconductor logic circuit device
US7555687B2 (en) * 2005-07-20 2009-06-30 Texas Instruments Incorporated Sequential scan technique for testing integrated circuits with reduced power, time and/or cost
US7743306B2 (en) * 2005-07-26 2010-06-22 Kyushu Institute Of Technology Test vector generating method and test vector generating program of semiconductor logic circuit device
KR100810140B1 (ko) * 2005-11-16 2008-03-06 엠텍비젼 주식회사 선택적 테스트 벡터 압축 방법 및 장치
JP5017603B2 (ja) * 2005-11-30 2012-09-05 国立大学法人九州工業大学 変換装置、変換方法、変換方法をコンピュータに実行させることが可能なプログラム、及び、このプログラムを記録した記録媒体
JP5066684B2 (ja) * 2006-03-28 2012-11-07 国立大学法人九州工業大学 生成装置、生成方法、生成方法をコンピュータに実行させることが可能なプログラム、及び、このプログラムを記録した記録媒体
US20070260926A1 (en) * 2006-04-13 2007-11-08 International Business Machines Corporation Static and dynamic learning test generation method
US8059547B2 (en) * 2008-12-08 2011-11-15 Advantest Corporation Test apparatus and test method
US8483073B2 (en) * 2008-12-08 2013-07-09 Advantest Corporation Test apparatus and test method
US8666691B2 (en) 2008-12-08 2014-03-04 Advantest Corporation Test apparatus and test method
US20120136603A1 (en) * 2008-12-08 2012-05-31 Advantest Corporation Test apparatus and debug method
US8743702B2 (en) * 2008-12-08 2014-06-03 Advantest Corporation Test apparatus and test method
US8692566B2 (en) 2008-12-08 2014-04-08 Advantest Corporation Test apparatus and test method
JP2009169976A (ja) * 2009-04-24 2009-07-30 Semiconductor Technology Academic Research Center 集積回路のテスト容易化設計方法および装置
JP7214440B2 (ja) * 2018-11-01 2023-01-30 三菱重工エンジニアリング株式会社 検証処理装置、検証処理方法及びプログラム

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US4991176A (en) * 1989-06-07 1991-02-05 At&T Bell Laboratories Optimal test generation for finite state machine models
US5485613A (en) * 1991-08-27 1996-01-16 At&T Corp. Method for automatic memory reclamation for object-oriented systems with real-time constraints
US5444717A (en) * 1992-12-18 1995-08-22 Digital Equipment Corporation Method for providing minimal size test vector sets
DE4305442C2 (de) * 1993-02-23 1999-08-05 Hewlett Packard Gmbh Verfahren und Vorrichtung zum Erzeugen eines Testvektors
US5418793A (en) * 1993-06-22 1995-05-23 At&T Corp. Method and apparatus for testing a complex entity
US5517506A (en) * 1994-03-28 1996-05-14 Motorola, Inc. Method and data processing system for testing circuits using boolean differences
US5696772A (en) * 1994-05-06 1997-12-09 Credence Systems Corporation Test vector compression/decompression system for parallel processing integrated circuit tester
US5617427A (en) * 1994-10-18 1997-04-01 Matsushita Electcric Industrial Co., Ltd. Method for generating test sequences for detecting faults in target scan logical blocks
US5726996A (en) * 1995-09-18 1998-03-10 Nec Usa, Inc. Process for dynamic composition and test cycles reduction
US5864838A (en) * 1996-12-31 1999-01-26 Cadence Design Systems, Inc. System and method for reordering lookup table entries when table address bits are reordered
US5905986A (en) * 1997-01-07 1999-05-18 Hewlett-Packard Company Highly compressible representation of test pattern data

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10034897A1 (de) * 2000-07-18 2002-01-31 Infineon Technologies Ag Adresszähler zur Adressierung von synchronen hochfrequenten Digitalschaltungen, insbesondere Speicherbauelementen
DE10034852A1 (de) * 2000-07-18 2002-02-07 Infineon Technologies Ag Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen
DE10034897B4 (de) * 2000-07-18 2004-08-05 Infineon Technologies Ag Adresszähler zur Adressierung von synchronen hochfrequenten Digitalschaltungen, insbesondere Speicherbauelementen
EP1176606A3 (de) * 2000-07-18 2006-05-10 Infineon Technologies AG Verfahren und Vorrichtung zum Einlesen und zur Überprüfung der zeitlichen Lage von aus einem zu testenden Speicherbaustein ausgelesenen Datenantwortsignalen
DE10210264B4 (de) * 2001-03-09 2007-05-10 Agilent Technologies, Inc. (n.d.Ges.d.Staates Delaware), Palo Alto Ein Testvektorkomprimierungsverfahren
DE10137297A1 (de) * 2001-08-01 2003-02-20 Abb Patent Gmbh Verfahren zum Testen von Software-Robustheit
US8332715B2 (en) 2008-01-10 2012-12-11 Fujitsu Limited Test pattern generating method, device, and program

Also Published As

Publication number Publication date
JPH11281716A (ja) 1999-10-15
US6067651A (en) 2000-05-23

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: AGILENT TECHNOLOGIES, INC. (N.D.GES.D.STAATES DELA

8127 New person/name/address of the applicant

Owner name: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE) PTE. LT

8139 Disposal/non-payment of the annual fee