DE19749115C2 - Taktsignal-Phasenkomparator - Google Patents
Taktsignal-PhasenkomparatorInfo
- Publication number
- DE19749115C2 DE19749115C2 DE19749115A DE19749115A DE19749115C2 DE 19749115 C2 DE19749115 C2 DE 19749115C2 DE 19749115 A DE19749115 A DE 19749115A DE 19749115 A DE19749115 A DE 19749115A DE 19749115 C2 DE19749115 C2 DE 19749115C2
- Authority
- DE
- Germany
- Prior art keywords
- clock signal
- output
- phase
- clkfbk
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003111 delayed effect Effects 0.000 claims description 10
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 10
- 206010044565 Tremor Diseases 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
- H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
- H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
- Dram (AREA)
Description
Claims (6)
- - eine erste Verzögerungseinheit (20) zum Verzögern eines Taktsignals (CLKin) um eine vorgegebene Zeit (t1),
- - einen ersten Phasendetektor (21) zum Vergleichen eines Aus gangssignals der ersten Verzögerungseinheit (20) mit einem Referenztaktsignal (CLKfbk) und zum Ausgeben eines ersten auf High- oder Low-Pegel liegenden Ausgangssignals (OUT1),
- - eine zweite Verzögerungseinheit (22) zum Verzögern des Re ferenztaktsignals (CLKfbk) um eine vorgegebene Zeit (t2), und
- - einen zweiten Phasendetektor (23) zum Vergleichen eines Ausgangssignals der zweiten Verzögerungseinheit (22) mit dem Taktsignal (CLKin) und zum Ausgeben eines zweiten auf High- oder Low-Pegel liegenden Ausgangssignals (OUT2),
- - der erste Phasendetektor (21) und der zweite Phasendetektor (23) ausgelegt sind, die jeweiligen Ausgangssignale (OUT1, OUT2) mit einem ersten gleichen Pegel auszugeben, wenn das Taktsignal (CLKin) zeitlich vor dem Referenztaktsignal (CLKfbk) auftritt, und
- - der erste Phasendetektor (21) und der zweite Phasendetektor (23) ausgelegt sind, die jeweiligen Ausgangssignale (OUT1, OUT2) mit einem zweiten gleichen Pegel auszugeben, wenn das Taktsignal (CLKin) zeitlich nach dem Referenztaktsignal (CLKfbk) auftritt.
- - der erste Phasendetektor (21) ausgelegt ist, das erste Aus gangssignal (OUT1) auf dem Low-Pegel auszugeben, und
- - der zweite Phasendetektor (23) ausgelegt ist, das zweite Ausgangssignal (OUT2) auf dem High-Pegel auszugeben, wenn das Taktsignal (CLKin) zeitlich synchronisiert mit dem Referenz taktsignal (CLKfbk) auftritt.
der erste Phasendetektor (21) ausgelegt ist, das erste Aus gangssignal (OUT1) auf dem High-Pegel auszugeben, und
der zweite Phasendetektor (23) ausgelegt ist, das zweite Ausgangssignal (OUT2) auf dem Low-Pegel auszugeben, wenn zwi schen dem Taktsignal (CLKin) und dem Referenztaktsignal (CLKfbk) eine Phasenwinkeldifferenz von 180° besteht.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970015777A KR100244466B1 (ko) | 1997-04-26 | 1997-04-26 | 클럭 위상 비교기 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE19749115A1 DE19749115A1 (de) | 1998-11-05 |
DE19749115C2 true DE19749115C2 (de) | 2002-06-13 |
Family
ID=19504041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19749115A Expired - Lifetime DE19749115C2 (de) | 1997-04-26 | 1997-11-06 | Taktsignal-Phasenkomparator |
Country Status (4)
Country | Link |
---|---|
US (1) | US6087857A (de) |
JP (1) | JP3492899B2 (de) |
KR (1) | KR100244466B1 (de) |
DE (1) | DE19749115C2 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100215889B1 (ko) * | 1997-05-06 | 1999-08-16 | 구본준 | 클럭 동기 회로 |
US6173432B1 (en) | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
DE19845121C1 (de) * | 1998-09-30 | 2000-03-30 | Siemens Ag | Integrierte Schaltung mit einstellbaren Verzögerungseinheiten für Taktsignale |
US6470060B1 (en) | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
US6373301B1 (en) * | 2001-04-18 | 2002-04-16 | Silicon Integrated Systems Corporation | Fast-locking dual rail digital delayed locked loop |
US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
ATE464697T1 (de) * | 2002-11-18 | 2010-04-15 | Nxp Bv | Integrierte schwebende leistungsübertragungsvorrichtung mit reduzierten elekromagnetischen emissionen |
US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
US7319340B2 (en) * | 2005-08-01 | 2008-01-15 | Micron Technology, Inc. | Integrated circuit load board and method having on-board test circuit |
US7328381B2 (en) * | 2005-08-01 | 2008-02-05 | Micron Technology, Inc. | Testing system and method for memory modules having a memory hub architecture |
US7765424B2 (en) | 2005-08-19 | 2010-07-27 | Micron Technology, Inc. | System and method for injecting phase jitter into integrated circuit test signals |
US7355387B2 (en) * | 2005-12-08 | 2008-04-08 | Micron Technology, Inc. | System and method for testing integrated circuit timing margins |
US7284169B2 (en) * | 2005-12-08 | 2007-10-16 | Micron Technology, Inc. | System and method for testing write strobe timing margins in memory devices |
WO2008012915A1 (fr) * | 2006-07-28 | 2008-01-31 | Fujitsu Limited | Appareil de détermination de phase et appareil de synchronisation de phase |
US7728636B2 (en) * | 2007-08-14 | 2010-06-01 | Qimonda Ag | Clock signal synchronizing device with inherent duty-cycle correction capability |
JP5433432B2 (ja) * | 2010-01-18 | 2014-03-05 | 株式会社日立製作所 | 位相周波数比較器およびシリアル伝送装置 |
US9178502B2 (en) * | 2013-12-27 | 2015-11-03 | Intel Corporation | Apparatus for a monotonic delay line, method for fast locking of a digital DLL with clock stop/start tolerance, apparatus and method for robust clock edge placement, and apparatus and method for clock offset tuning |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0572135A2 (de) * | 1992-05-26 | 1993-12-01 | Digital Equipment Corporation | Phasenregelkreis mit einer Zustandsmaschine |
JPH0730415A (ja) * | 1993-07-12 | 1995-01-31 | Oki Electric Ind Co Ltd | Pll回路 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1236494A (en) * | 1969-06-23 | 1971-06-23 | Marconi Co Ltd | Improvements in or relating to phase difference detectors |
SE413826B (sv) * | 1978-09-21 | 1980-06-23 | Ellemtel Utvecklings Ab | Sett att i ett telekommunikationssystem reglera fasleget hos en styrd signal i forhallande till en referenssignal samt anordning for genomforande av settet |
US5223755A (en) * | 1990-12-26 | 1993-06-29 | Xerox Corporation | Extended frequency range variable delay locked loop for clock synchronization |
DE4139117C1 (de) * | 1991-11-28 | 1993-06-09 | Texas Instruments Deutschland Gmbh, 8050 Freising, De | |
TW234796B (de) * | 1993-02-24 | 1994-11-21 | Advanced Micro Devices Inc | |
US5570054A (en) * | 1994-09-26 | 1996-10-29 | Hitachi Micro Systems, Inc. | Method and apparatus for adaptive clock deskewing |
US5455540A (en) * | 1994-10-26 | 1995-10-03 | Cypress Semiconductor Corp. | Modified bang-bang phase detector with ternary output |
JP3408030B2 (ja) * | 1995-09-21 | 2003-05-19 | 日本プレシジョン・サーキッツ株式会社 | 位相比較器 |
US5663665A (en) * | 1995-11-29 | 1997-09-02 | Cypress Semiconductor Corp. | Means for control limits for delay locked loop |
-
1997
- 1997-04-26 KR KR1019970015777A patent/KR100244466B1/ko not_active IP Right Cessation
- 1997-10-03 US US08/943,184 patent/US6087857A/en not_active Expired - Lifetime
- 1997-11-06 DE DE19749115A patent/DE19749115C2/de not_active Expired - Lifetime
- 1997-12-04 JP JP33339697A patent/JP3492899B2/ja not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0572135A2 (de) * | 1992-05-26 | 1993-12-01 | Digital Equipment Corporation | Phasenregelkreis mit einer Zustandsmaschine |
JPH0730415A (ja) * | 1993-07-12 | 1995-01-31 | Oki Electric Ind Co Ltd | Pll回路 |
Also Published As
Publication number | Publication date |
---|---|
KR19980078283A (ko) | 1998-11-16 |
KR100244466B1 (ko) | 2000-02-01 |
JPH10308656A (ja) | 1998-11-17 |
JP3492899B2 (ja) | 2004-02-03 |
US6087857A (en) | 2000-07-11 |
DE19749115A1 (de) | 1998-11-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition | ||
R082 | Change of representative |
Representative=s name: WUESTHOFF & WUESTHOFF PATENT- UND RECHTSANWAEL, DE Representative=s name: WUESTHOFF & WUESTHOFF PATENT- UND RECHTSANWAELTE, |
|
R081 | Change of applicant/patentee |
Owner name: CONVERSANT IP N.B. 868 INC., SAINT JOHN, CA Free format text: FORMER OWNER: LG SEMICON CO. LTD., CHEONGJU, CHOONGCHEONGBUK, KR Effective date: 20111130 Owner name: 658868 N.B. INC., CA Free format text: FORMER OWNER: LG SEMICON CO. LTD., CHEONGJU, KR Effective date: 20111130 |
|
R082 | Change of representative |
Representative=s name: WUESTHOFF & WUESTHOFF, PATENTANWAELTE PARTG MB, DE Effective date: 20111130 Representative=s name: WUESTHOFF & WUESTHOFF PATENT- UND RECHTSANWAEL, DE Effective date: 20111130 |
|
R082 | Change of representative |
Representative=s name: WUESTHOFF & WUESTHOFF PATENT- UND RECHTSANWAEL, DE |
|
R081 | Change of applicant/patentee |
Owner name: CONVERSANT IP N.B. 868 INC., SAINT JOHN, CA Free format text: FORMER OWNER: HYNIX SEMICONDUCTOR INC., ICHEON, KYONGGI, KR Effective date: 20130128 Owner name: 658868 N.B. INC., CA Free format text: FORMER OWNER: HYNIX SEMICONDUCTOR INC., ICHEON, KR Effective date: 20130128 |
|
R082 | Change of representative |
Representative=s name: WUESTHOFF & WUESTHOFF, PATENTANWAELTE PARTG MB, DE Effective date: 20130128 Representative=s name: WUESTHOFF & WUESTHOFF PATENT- UND RECHTSANWAEL, DE Effective date: 20130128 |
|
R082 | Change of representative |
Representative=s name: WUESTHOFF & WUESTHOFF PATENT- UND RECHTSANWAEL, DE |
|
R081 | Change of applicant/patentee |
Owner name: CONVERSANT IP N.B. 868 INC., SAINT JOHN, CA Free format text: FORMER OWNER: 658868 N.B. INC., SAINT JOHN, NEW BRUNSWICK, CA Effective date: 20140925 |
|
R082 | Change of representative |
Representative=s name: WUESTHOFF & WUESTHOFF PATENT- UND RECHTSANWAEL, DE Effective date: 20140925 Representative=s name: WUESTHOFF & WUESTHOFF, PATENTANWAELTE PARTG MB, DE Effective date: 20140925 |
|
R071 | Expiry of right |