DE19715730A1 - Halbleiterbauelement und Verfahren zu seiner Herstellung - Google Patents

Halbleiterbauelement und Verfahren zu seiner Herstellung

Info

Publication number
DE19715730A1
DE19715730A1 DE19715730A DE19715730A DE19715730A1 DE 19715730 A1 DE19715730 A1 DE 19715730A1 DE 19715730 A DE19715730 A DE 19715730A DE 19715730 A DE19715730 A DE 19715730A DE 19715730 A1 DE19715730 A1 DE 19715730A1
Authority
DE
Germany
Prior art keywords
layer
photo
hole
template
exposure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19715730A
Other languages
German (de)
English (en)
Inventor
Shuji Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE19715730A1 publication Critical patent/DE19715730A1/de
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE19715730A 1996-09-11 1997-04-15 Halbleiterbauelement und Verfahren zu seiner Herstellung Ceased DE19715730A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8240096A JPH1092714A (ja) 1996-09-11 1996-09-11 半導体装置およびその製造方法

Publications (1)

Publication Number Publication Date
DE19715730A1 true DE19715730A1 (de) 1998-03-12

Family

ID=17054440

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19715730A Ceased DE19715730A1 (de) 1996-09-11 1997-04-15 Halbleiterbauelement und Verfahren zu seiner Herstellung

Country Status (4)

Country Link
US (3) US6162736A (enExample)
JP (1) JPH1092714A (enExample)
KR (1) KR100243361B1 (enExample)
DE (1) DE19715730A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0982769A3 (en) * 1998-08-28 2000-05-24 Canon Kabushiki Kaisha Microdevice and structural components of the same
EP1041441A3 (en) * 1999-03-29 2003-10-01 Canon Kabushiki Kaisha Device manufacturing method

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3819711B2 (ja) * 1998-10-23 2006-09-13 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3367460B2 (ja) * 1999-04-09 2003-01-14 日本電気株式会社 半導体装置の製造方法およびこれに用いるフォトマスク
US6664011B2 (en) 2001-12-05 2003-12-16 Taiwan Semiconductor Manufacturing Company Hole printing by packing and unpacking using alternating phase-shifting masks
US6943124B1 (en) 2002-07-17 2005-09-13 Taiwan Semiconductor Manufacturing Company Two step exposure to strengthen structure of polyimide or negative tone photosensitive material
KR100576832B1 (ko) 2004-11-05 2006-05-10 삼성전자주식회사 비대칭 패턴들을 위한 포토 공정의 수행방법들 및 그를이용한 반도체 장치의 형성방법들
JP4698279B2 (ja) * 2005-05-02 2011-06-08 ユニ・チャーム株式会社 清掃具
JP4768469B2 (ja) * 2006-02-21 2011-09-07 株式会社東芝 半導体装置の製造方法
JP4984703B2 (ja) 2006-07-18 2012-07-25 富士通セミコンダクター株式会社 半導体装置の製造方法
US8124326B2 (en) * 2009-03-03 2012-02-28 Micron Technology, Inc. Methods of patterning positive photoresist

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4115909C1 (enExample) * 1991-05-15 1992-11-12 Siemens Ag, 8000 Muenchen, De
JPH05243114A (ja) * 1992-02-26 1993-09-21 Nec Corp 露光方法
JPH06151269A (ja) * 1992-11-05 1994-05-31 Fujitsu Ltd 半導体装置の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209124A (ja) * 1982-05-31 1983-12-06 Toshiba Corp レジストパタ−ン形成方法
JPH0290509A (ja) * 1988-09-27 1990-03-30 Sanyo Electric Co Ltd 半導体装置の製造方法
US5298365A (en) * 1990-03-20 1994-03-29 Hitachi, Ltd. Process for fabricating semiconductor integrated circuit device, and exposing system and mask inspecting method to be used in the process
EP0464492B1 (en) * 1990-06-21 1999-08-04 Matsushita Electronics Corporation A photomask used by photolithography and a process of producing the same
JPH04125938A (ja) * 1990-09-18 1992-04-27 Fujitsu Ltd 電界効果半導体装置およびその製造方法
JPH04158522A (ja) * 1990-10-23 1992-06-01 Fujitsu Ltd 微細なホールパターンを形成する方法
JP3084761B2 (ja) * 1991-02-28 2000-09-04 株式会社ニコン 露光方法及びマスク
KR950004968B1 (ko) * 1991-10-15 1995-05-16 가부시키가이샤 도시바 투영노광 장치
US5329335A (en) * 1992-03-17 1994-07-12 Nippon Steel Corporation Method and apparatus for projection exposure
KR970003593B1 (en) * 1992-09-03 1997-03-20 Samsung Electronics Co Ltd Projection exposure method and device using mask
US5523258A (en) * 1994-04-29 1996-06-04 Cypress Semiconductor Corp. Method for avoiding lithographic rounding effects for semiconductor fabrication
US5543253A (en) * 1994-08-08 1996-08-06 Electronics & Telecommunications Research Inst. Photomask for t-gate formation and process for fabricating the same
US6043164A (en) * 1996-06-10 2000-03-28 Sharp Laboratories Of America, Inc. Method for transferring a multi-level photoresist pattern
KR100201040B1 (ko) * 1996-08-26 1999-06-15 다니구찌 이찌로오; 기타오카 다카시 위상 쉬프트 마스크 및 그 제조 방법
US5776660A (en) * 1996-09-16 1998-07-07 International Business Machines Corporation Fabrication method for high-capacitance storage node structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4115909C1 (enExample) * 1991-05-15 1992-11-12 Siemens Ag, 8000 Muenchen, De
JPH05243114A (ja) * 1992-02-26 1993-09-21 Nec Corp 露光方法
JPH06151269A (ja) * 1992-11-05 1994-05-31 Fujitsu Ltd 半導体装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0982769A3 (en) * 1998-08-28 2000-05-24 Canon Kabushiki Kaisha Microdevice and structural components of the same
US6636294B2 (en) 1998-08-28 2003-10-21 Canon Kabushiki Kaisha Microdevice and structural components of the same
EP1041441A3 (en) * 1999-03-29 2003-10-01 Canon Kabushiki Kaisha Device manufacturing method

Also Published As

Publication number Publication date
KR19980023940A (ko) 1998-07-06
US20020022353A1 (en) 2002-02-21
US6162736A (en) 2000-12-19
KR100243361B1 (ko) 2000-03-02
US6329306B1 (en) 2001-12-11
JPH1092714A (ja) 1998-04-10

Similar Documents

Publication Publication Date Title
DE4440230C2 (de) Verfahren zur Bildung feiner Strukturen eines Halbleiterbauelements
DE69023558T2 (de) Verfahren zur Herstellung einer Halbleitervorrichtung.
DE2732184A1 (de) Halbleitervorrichtung und verfahren zu ihrer herstellung
DE69921254T2 (de) Mikrovorrichtung und strukturelle Komponenten derselben
DE19715730A1 (de) Halbleiterbauelement und Verfahren zu seiner Herstellung
DE19503985A1 (de) Verfahren zur Bildung eines Fotolackmusters für eine Halbleitervorrichtung
DE10310136B4 (de) Maskensatz zur Projektion von jeweils auf den Masken des Satzes angeordneten und aufeinander abgestimmten Strukturmustern auf einen Halbleiterwafer
DE68914572T2 (de) Verfahren zum Herstellen von Halbleitervorrichtungen.
DE19802369A1 (de) Phasenschiebe-Photomasken-Herstellungsverfahren
DE19648075C2 (de) Phasenschiebemaske und Herstellverfahren für diese
DE69712478T2 (de) Eine bildumkehrtechnik zu ausbildung kleiner strukturen in integrierten schaltkreisen
DE1639263B1 (de) Photolithographisches verfahren zum herstellen von halbleiter bauelementen oder integrierten schaltungen
DE102005047475B4 (de) Verfahren zum Herstellen eines Maskensatzes und Maskensatz zum Definieren eines Musters
DE4447264B4 (de) Verfahren zur Herstellung einer Halbton-Phasenverschiebungsmaske
DE3337300A1 (de) Verfahren zum herstellen integrierter halbleiterschaltkreise
DE19501564C2 (de) Phasenschiebermaske und Verfahren zur Herstellung derselben
DE10310137A1 (de) Satz von wenigstens zwei Masken zur Projektion von jeweils auf den Masken gebildeten und aufeinander abgestimmten Strukturmustern und Verfahren zur Herstellung der Masken
DE2642634A1 (de) Verfahren zum justieren von belichtungsmasken relativ zu einer substratscheibe
DE19503959A1 (de) Fotomaske zur Bildung eines Mikromusters einer Halbleitervorrichtung
DE2632548C2 (de) Anordnung und Verfahren zum Herstellen von Verbindungen zwischen Teilschaltungen
DE4339466C2 (de) Verfahren zur Bildung von Mustern unter Verwendung eines Mehrschichtresists
DE19825043B4 (de) Maske für die Herstellung integrierter Schaltungen
EP0931439B1 (de) Verfahren zur bildung von mindestens zwei verdrahtungsebenen auf elektrisch isolierenden unterlagen
DE2005495A1 (de) Photomaske und Verfahren zu ihrer Herstellung
DD250400A1 (de) Schablonenabbildungsverfahren zur verringerung des strukturrasters

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8131 Rejection