DE1937114B2 - Anordnung zur Auskopplung eines Ausgangssignals und zur Unterdrückung von Spannungsspitzen - Google Patents

Anordnung zur Auskopplung eines Ausgangssignals und zur Unterdrückung von Spannungsspitzen

Info

Publication number
DE1937114B2
DE1937114B2 DE1937114A DE1937114A DE1937114B2 DE 1937114 B2 DE1937114 B2 DE 1937114B2 DE 1937114 A DE1937114 A DE 1937114A DE 1937114 A DE1937114 A DE 1937114A DE 1937114 B2 DE1937114 B2 DE 1937114B2
Authority
DE
Germany
Prior art keywords
transistor
output signal
base
electrode
coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE1937114A
Other languages
German (de)
English (en)
Other versions
DE1937114A1 (de
Inventor
Karl-Ernst Dipl.-Ing. Boeters
Gerhard Dipl.-Phys. 7022 Leinfelden Conzelmann
Hans-Joachim Fleischer
Peter 7000 Stuttgart Mueller
Klaus Dipl.-Ing. 7400 Tuebingen Streit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE1937114A priority Critical patent/DE1937114B2/de
Priority to FR6945288A priority patent/FR2031008A5/fr
Priority to CH985870A priority patent/CH509006A/de
Priority to US55881A priority patent/US3662228A/en
Priority to GB3520270A priority patent/GB1324682A/en
Publication of DE1937114A1 publication Critical patent/DE1937114A1/de
Publication of DE1937114B2 publication Critical patent/DE1937114B2/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
    • H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
    • H03K17/0814—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/08146—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit in bipolar transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/64—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors having inductive loads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/63—Combinations of vertical and lateral BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]

Landscapes

  • Electronic Switches (AREA)
  • Bipolar Transistors (AREA)
DE1937114A 1969-07-22 1969-07-22 Anordnung zur Auskopplung eines Ausgangssignals und zur Unterdrückung von Spannungsspitzen Pending DE1937114B2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE1937114A DE1937114B2 (de) 1969-07-22 1969-07-22 Anordnung zur Auskopplung eines Ausgangssignals und zur Unterdrückung von Spannungsspitzen
FR6945288A FR2031008A5 (OSRAM) 1969-07-22 1969-12-29
CH985870A CH509006A (de) 1969-07-22 1970-06-30 Elektrische Schaltungsanordnung zur Auskopplung eines Ausgangssignals und zur Unterdrückung von Spannungsspitzen
US55881A US3662228A (en) 1969-07-22 1970-07-17 Circuit arrangement for generating a signal and for suppressing voltage peaks
GB3520270A GB1324682A (en) 1969-07-22 1970-07-21 Decoupling arrangements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1937114A DE1937114B2 (de) 1969-07-22 1969-07-22 Anordnung zur Auskopplung eines Ausgangssignals und zur Unterdrückung von Spannungsspitzen

Publications (2)

Publication Number Publication Date
DE1937114A1 DE1937114A1 (de) 1971-02-04
DE1937114B2 true DE1937114B2 (de) 1974-08-29

Family

ID=5740486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1937114A Pending DE1937114B2 (de) 1969-07-22 1969-07-22 Anordnung zur Auskopplung eines Ausgangssignals und zur Unterdrückung von Spannungsspitzen

Country Status (5)

Country Link
US (1) US3662228A (OSRAM)
CH (1) CH509006A (OSRAM)
DE (1) DE1937114B2 (OSRAM)
FR (1) FR2031008A5 (OSRAM)
GB (1) GB1324682A (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3145554A1 (de) * 1981-11-17 1983-05-26 Teldix Gmbh, 6900 Heidelberg Schutzschaltung fuer einen schalttransistor

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2638178C2 (de) * 1976-08-25 1986-01-02 Robert Bosch Gmbh, 7000 Stuttgart Schutzvorrichtung für integrierte Schaltungen gegen Überspannungen
GB2049330B (en) * 1979-05-02 1983-05-18 Rca Corp Antilatch circuit for power output devices using inductive loads
US4894567A (en) * 1988-10-17 1990-01-16 Honeywell Inc. Active snubber circuit
EP0507398B1 (en) * 1991-04-04 1998-01-21 Koninklijke Philips Electronics N.V. Circuit arrangement
JP3009953B2 (ja) * 1991-12-24 2000-02-14 シャープ株式会社 ダンピング回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3340407A (en) * 1964-07-29 1967-09-05 Gen Electric Deenergizing circuit
US3320551A (en) * 1965-04-12 1967-05-16 California Inst Res Found Temperature stabilized multivibrator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3145554A1 (de) * 1981-11-17 1983-05-26 Teldix Gmbh, 6900 Heidelberg Schutzschaltung fuer einen schalttransistor

Also Published As

Publication number Publication date
DE1937114A1 (de) 1971-02-04
CH509006A (de) 1971-06-15
FR2031008A5 (OSRAM) 1970-11-13
GB1324682A (en) 1973-07-25
US3662228A (en) 1972-05-09

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