DE1915501C3 - Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen - Google Patents

Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen

Info

Publication number
DE1915501C3
DE1915501C3 DE1915501A DE1915501A DE1915501C3 DE 1915501 C3 DE1915501 C3 DE 1915501C3 DE 1915501 A DE1915501 A DE 1915501A DE 1915501 A DE1915501 A DE 1915501A DE 1915501 C3 DE1915501 C3 DE 1915501C3
Authority
DE
Germany
Prior art keywords
integrated circuit
conductor tracks
insulating substrate
hole
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE1915501A
Other languages
German (de)
English (en)
Other versions
DE1915501B2 (de
DE1915501A1 (de
Inventor
Richard Dr. 8011 Neukeferloh Wiesner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE1915501A priority Critical patent/DE1915501C3/de
Priority to DE19691948333 priority patent/DE1948333C3/de
Priority to NL6918609A priority patent/NL6918609A/xx
Priority to US00020519A priority patent/US3745648A/en
Priority to CH446070A priority patent/CH503374A/de
Priority to FR7010487A priority patent/FR2039895A5/fr
Priority to AT271770A priority patent/AT305375B/de
Priority to GB04376/70A priority patent/GB1240977A/en
Priority to JP45024960A priority patent/JPS4916222B1/ja
Priority to SE7004299A priority patent/SE402516B/xx
Priority to FR7034139A priority patent/FR2064819A6/fr
Priority to CH1393370A priority patent/CH522289A/de
Priority to NL7014112A priority patent/NL7014112A/xx
Publication of DE1915501A1 publication Critical patent/DE1915501A1/de
Publication of DE1915501B2 publication Critical patent/DE1915501B2/de
Application granted granted Critical
Publication of DE1915501C3 publication Critical patent/DE1915501C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/435—Shapes or dispositions of insulating layers on leadframes, e.g. bridging members
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
DE1915501A 1969-03-26 1969-03-26 Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen Expired DE1915501C3 (de)

Priority Applications (13)

Application Number Priority Date Filing Date Title
DE1915501A DE1915501C3 (de) 1969-03-26 1969-03-26 Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen
DE19691948333 DE1948333C3 (de) 1969-09-24 Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen
NL6918609A NL6918609A (https=) 1969-03-26 1969-12-11
US00020519A US3745648A (en) 1969-03-26 1970-03-18 Method for mounting semiconductor components
AT271770A AT305375B (de) 1969-03-26 1970-03-24 Verfahren zur Montage von Halbleiterbauelementen
FR7010487A FR2039895A5 (https=) 1969-03-26 1970-03-24
CH446070A CH503374A (de) 1969-03-26 1970-03-24 Verfahren zum Verbinden einer integrierten Schaltung mit äusseren elektrischen Zuleitungen
GB04376/70A GB1240977A (en) 1969-03-26 1970-03-25 Improvements in or relating to semiconductor components
SE7004299A SE402516B (sv) 1969-03-26 1970-03-26 Sett att forbinda en integrerad krets med yttre, elektriska anslutningar
JP45024960A JPS4916222B1 (https=) 1969-03-26 1970-03-26
FR7034139A FR2064819A6 (https=) 1969-03-26 1970-09-21
CH1393370A CH522289A (de) 1969-03-26 1970-09-21 Verfahren zum Verbinden einer integrierten Schaltung mit äusseren elektrischen Zuleitungen
NL7014112A NL7014112A (https=) 1969-03-26 1970-09-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1915501A DE1915501C3 (de) 1969-03-26 1969-03-26 Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen

Publications (3)

Publication Number Publication Date
DE1915501A1 DE1915501A1 (de) 1970-10-01
DE1915501B2 DE1915501B2 (de) 1975-02-27
DE1915501C3 true DE1915501C3 (de) 1975-10-16

Family

ID=5729405

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1915501A Expired DE1915501C3 (de) 1969-03-26 1969-03-26 Verfahren zum Verbinden einer integrierten Schaltung mit äußeren elektrischen Zuleitungen

Country Status (9)

Country Link
US (1) US3745648A (https=)
JP (1) JPS4916222B1 (https=)
AT (1) AT305375B (https=)
CH (1) CH503374A (https=)
DE (1) DE1915501C3 (https=)
FR (1) FR2039895A5 (https=)
GB (1) GB1240977A (https=)
NL (1) NL6918609A (https=)
SE (1) SE402516B (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2057126C3 (de) * 1970-05-14 1975-11-06 Siemens Ag, 1000 Berlin Und 8000 Muenchen Anordnung und Verfahren zur Kontaktierung von Halbleiterbauelementen
US3823467A (en) * 1972-07-07 1974-07-16 Westinghouse Electric Corp Solid-state circuit module
US3964157A (en) * 1974-10-31 1976-06-22 Bell Telephone Laboratories, Incorporated Method of mounting semiconductor chips
US4300153A (en) * 1977-09-22 1981-11-10 Sharp Kabushiki Kaisha Flat shaped semiconductor encapsulation
US4218701A (en) * 1978-07-24 1980-08-19 Citizen Watch Co., Ltd. Package for an integrated circuit having a container with support bars
DE3019207A1 (de) * 1980-05-20 1981-11-26 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Traegerelement fuer einen ic-chip
DE3029667A1 (de) * 1980-08-05 1982-03-11 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Traegerelement fuer einen ic-baustein
US4630096A (en) * 1984-05-30 1986-12-16 Motorola, Inc. High density IC module assembly
DE3627372C3 (de) * 1986-08-12 1994-04-14 Loewe Opta Gmbh Anordnung, bestehend aus einer Leiterplatte, einem Kühlkörper und zu kühlenden elektronischen Bauelementen
DE3914756A1 (de) * 1989-05-05 1990-11-22 Platzer Schwedenbau Gmbh Verfahren zur herstellung einer rohrflanschverbindung
DE19520676A1 (de) * 1995-06-07 1996-12-12 Deutsche Telekom Ag Hybridschaltung und Verfahren zur Herstellung derselben
US6571468B1 (en) * 2001-02-26 2003-06-03 Saturn Electronics & Engineering, Inc. Traceless flip chip assembly and method
AT523450B1 (de) 2020-01-27 2025-04-15 Univ Linz Durchdringbares Element

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3271625A (en) * 1962-08-01 1966-09-06 Signetics Corp Electronic package assembly
GB1015909A (en) * 1963-12-30 1966-01-05 Gen Micro Electronics Inc Method of and product for packaging electronic devices
US3374537A (en) * 1965-03-22 1968-03-26 Philco Ford Corp Method of connecting leads to a semiconductive device
US3390308A (en) * 1966-03-31 1968-06-25 Itt Multiple chip integrated circuit assembly
US3559285A (en) * 1968-01-08 1971-02-02 Jade Corp Method of forming leads for attachment to semi-conductor devices

Also Published As

Publication number Publication date
GB1240977A (en) 1971-07-28
FR2039895A5 (https=) 1971-01-15
US3745648A (en) 1973-07-17
DE1915501B2 (de) 1975-02-27
NL6918609A (https=) 1970-09-29
AT305375B (de) 1973-02-26
SE402516B (sv) 1978-07-03
DE1915501A1 (de) 1970-10-01
JPS4916222B1 (https=) 1974-04-20
CH503374A (de) 1971-02-15

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
EF Willingness to grant licences