DE1764142B1 - Verfahren zur herstellung eines npn transistors mit hoher zuendspannung - Google Patents

Verfahren zur herstellung eines npn transistors mit hoher zuendspannung

Info

Publication number
DE1764142B1
DE1764142B1 DE19681764142 DE1764142A DE1764142B1 DE 1764142 B1 DE1764142 B1 DE 1764142B1 DE 19681764142 DE19681764142 DE 19681764142 DE 1764142 A DE1764142 A DE 1764142A DE 1764142 B1 DE1764142 B1 DE 1764142B1
Authority
DE
Germany
Prior art keywords
layer
zone
conductive
collector
silicon wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19681764142
Other languages
German (de)
English (en)
Inventor
Hughes Thomas Lawrence
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZF International UK Ltd
Original Assignee
Lucas Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucas Industries Ltd filed Critical Lucas Industries Ltd
Publication of DE1764142B1 publication Critical patent/DE1764142B1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/026Deposition thru hole in mask
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/043Dual dielectric
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/118Oxide films
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/151Simultaneous diffusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/914Doping
    • Y10S438/92Controlling diffusion profile by oxidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Thyristors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
DE19681764142 1967-04-11 1968-04-10 Verfahren zur herstellung eines npn transistors mit hoher zuendspannung Pending DE1764142B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB06543/67A GB1209313A (en) 1967-04-11 1967-04-11 HIGH VOLTAGE n-p-n TRANSISTORS
GB06542/67A GB1209310A (en) 1967-04-11 1967-04-11 High voltage n-p-n transistors

Publications (1)

Publication Number Publication Date
DE1764142B1 true DE1764142B1 (de) 1971-12-09

Family

ID=26252097

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681764142 Pending DE1764142B1 (de) 1967-04-11 1968-04-10 Verfahren zur herstellung eines npn transistors mit hoher zuendspannung

Country Status (5)

Country Link
US (2) US3535171A (OSRAM)
DE (1) DE1764142B1 (OSRAM)
FR (2) FR1575641A (OSRAM)
GB (2) GB1209313A (OSRAM)
NL (2) NL6804611A (OSRAM)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2160710B1 (OSRAM) * 1971-11-22 1974-09-27 Radiotechnique Compelec
US4006045A (en) * 1974-10-21 1977-02-01 International Business Machines Corporation Method for producing high power semiconductor device using anodic treatment and enhanced diffusion
US3961353A (en) * 1974-10-21 1976-06-01 International Business Machines Corporation High power semiconductor device
JPS5942989B2 (ja) * 1977-01-24 1984-10-18 株式会社日立製作所 高耐圧半導体素子およびその製造方法
US4587540A (en) * 1982-04-05 1986-05-06 International Business Machines Corporation Vertical MESFET with mesa step defining gate length

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1330420A (fr) * 1961-08-03 1963-06-21 Lucas Industries Ltd Redresseur commandé
US3215570A (en) * 1963-03-15 1965-11-02 Texas Instruments Inc Method for manufacture of semiconductor devices
FR1429174A (fr) * 1964-04-20 1966-02-18 Lucas Industries Ltd Procédé de fabrication d'un transistor à haute tension du type n-p-n, et transistor obtenu au moyen de ce procédé

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3210225A (en) * 1961-08-18 1965-10-05 Texas Instruments Inc Method of making transistor
US3249831A (en) * 1963-01-04 1966-05-03 Westinghouse Electric Corp Semiconductor controlled rectifiers with a p-n junction having a shallow impurity concentration gradient

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1330420A (fr) * 1961-08-03 1963-06-21 Lucas Industries Ltd Redresseur commandé
US3215570A (en) * 1963-03-15 1965-11-02 Texas Instruments Inc Method for manufacture of semiconductor devices
FR1429174A (fr) * 1964-04-20 1966-02-18 Lucas Industries Ltd Procédé de fabrication d'un transistor à haute tension du type n-p-n, et transistor obtenu au moyen de ce procédé

Also Published As

Publication number Publication date
GB1209310A (en) 1970-10-21
FR1575641A (OSRAM) 1969-07-25
US3535170A (en) 1970-10-20
NL6804611A (OSRAM) 1968-10-14
US3535171A (en) 1970-10-20
NL6804610A (OSRAM) 1968-10-14
DE1764143A1 (de) 1972-04-20
GB1209313A (en) 1970-10-21
FR1559523A (OSRAM) 1969-03-07
DE1764143B2 (de) 1972-11-09

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