DE1640468B2 - Elektrische verbindung zwischen auf gegenueberliegenden seiten von schaltkarten verlaufenden leiterstreifen - Google Patents

Elektrische verbindung zwischen auf gegenueberliegenden seiten von schaltkarten verlaufenden leiterstreifen

Info

Publication number
DE1640468B2
DE1640468B2 DE19661640468 DE1640468A DE1640468B2 DE 1640468 B2 DE1640468 B2 DE 1640468B2 DE 19661640468 DE19661640468 DE 19661640468 DE 1640468 A DE1640468 A DE 1640468A DE 1640468 B2 DE1640468 B2 DE 1640468B2
Authority
DE
Germany
Prior art keywords
electrical connection
circuit boards
operating sides
operating
sides
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19661640468
Other languages
English (en)
Other versions
DE1640468A1 (de
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of DE1640468A1 publication Critical patent/DE1640468A1/de
Publication of DE1640468B2 publication Critical patent/DE1640468B2/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/091—Locally and permanently deformed areas including dielectric material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0195—Tool for a process not provided for in H05K3/00, e.g. tool for handling objects using suction, for deforming objects, for applying local pressure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0221—Perforating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1189—Pressing leads, bumps or a die through an insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
    • Y10T29/49167—Manufacturing circuit on or in base by forming conductive walled aperture in base with deforming of conductive path

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
DE19661640468 1965-06-16 1966-06-15 Elektrische verbindung zwischen auf gegenueberliegenden seiten von schaltkarten verlaufenden leiterstreifen Withdrawn DE1640468B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US464467A US3346950A (en) 1965-06-16 1965-06-16 Method of making through-connections by controlled punctures

Publications (2)

Publication Number Publication Date
DE1640468A1 DE1640468A1 (de) 1970-08-20
DE1640468B2 true DE1640468B2 (de) 1971-06-03

Family

ID=23844048

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19661640468 Withdrawn DE1640468B2 (de) 1965-06-16 1966-06-15 Elektrische verbindung zwischen auf gegenueberliegenden seiten von schaltkarten verlaufenden leiterstreifen

Country Status (4)

Country Link
US (1) US3346950A (de)
DE (1) DE1640468B2 (de)
FR (1) FR1483563A (de)
GB (1) GB1077867A (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19522338A1 (de) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Durchkontaktierung sowie Chipträger und Chipträgeranordnung mit einer Durchkontaktierung
DE19531970A1 (de) * 1995-08-30 1997-03-06 Siemens Ag Verfahren zur Herstellung einer Verbindung zwischen zumindest zwei elektrischen Leitern, von denen einer auf einem Trägersubstrat angeordnet ist

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3576407A (en) * 1966-03-14 1971-04-27 Morris Lavine Time control system and method for producing television, radio and video tape programs and for other uses
US3519959A (en) * 1966-03-24 1970-07-07 Burroughs Corp Integral electrical power distribution network and component mounting plane
FR2064304A1 (de) * 1969-10-13 1971-07-23 Avery Products Corp
US3628243A (en) * 1969-11-14 1971-12-21 Bell Telephone Labor Inc Fabrication of printed circuit
DE2347217A1 (de) * 1973-09-19 1975-03-27 Siemens Ag Verfahren zum durchkontaktieren eines beidseitig metallkaschierten basismaterials fuer gedruckte schaltungen
FR2380686A1 (fr) * 1977-02-15 1978-09-08 Lomerson Robert Procede pour etablir une connexion electrique a travers une plaque de matiere isolante
FR2516311B1 (fr) * 1981-11-06 1985-10-11 Thomson Csf Socle pour le montage d'une pastille semi-conductrice sur l'embase d'un boitier d'encapsulation, et procede de realisation de ce socle
EP0109084B1 (de) * 1982-11-15 1987-06-10 Storno A/S Doppelseitig gedruckte Dickfilm-Leiterplatte und Verfahren zu ihrer Herstellung
NL8403755A (nl) * 1984-12-11 1986-07-01 Philips Nv Werkwijze voor de vervaardiging van een meerlaags gedrukte bedrading met doorverbonden sporen in verschillende lagen en meerlaags gedrukte bedrading vervaardigd volgens de werkwijze.
US4635358A (en) * 1985-01-03 1987-01-13 E. I. Du Pont De Nemours And Company Method for forming electrically conductive paths through a dielectric layer
JPH0666549B2 (ja) * 1988-08-31 1994-08-24 信越ポリマー株式会社 スルーホール付きフレキシブル基板の製造方法
JP2767645B2 (ja) * 1990-03-07 1998-06-18 富士通株式会社 多層配線基板の製造方法
US5189261A (en) * 1990-10-09 1993-02-23 Ibm Corporation Electrical and/or thermal interconnections and methods for obtaining such
US5205738A (en) * 1992-04-03 1993-04-27 International Business Machines Corporation High density connector system
ATE137079T1 (de) * 1992-06-15 1996-05-15 Heinze Dyconex Patente Verfahren zur herstellung von nachträglich konditionierbaren kontaktstellen an schaltungsträgern und schaltungsträger mit solchen kontaktstellen
US6010769A (en) * 1995-11-17 2000-01-04 Kabushiki Kaisha Toshiba Multilayer wiring board and method for forming the same
JPH10313008A (ja) * 1997-05-13 1998-11-24 Canon Inc 微細パターンの形成方法及び該微細パターンを有する電気素子
GB2336161B (en) 1998-04-06 2003-03-26 John Michael Lowe Method of providing conductive tracks on a printed circuit and apparatus for use in carrying out the method
US6939447B2 (en) 1998-04-06 2005-09-06 Tdao Limited Method of providing conductive tracks on a printed circuit and apparatus for use in carrying out the method
GB9828490D0 (en) * 1998-12-23 1999-02-17 Lucas Ind Plc Printed circuit device
EP1269807B1 (de) * 2000-03-31 2006-01-18 Dyconex AG Verfahren zur herstellung eines elektrischen verbindungselements und elektrisches verbindungselement
AU2001242204A1 (en) * 2000-03-31 2001-10-23 Dyconex Patente Ag Method and device for fabricating electrical connecting elements, and connectingelement
DE60130108T2 (de) * 2000-03-31 2008-08-07 Dyconex Ag Verfahren zur herstellung elektrischer verbindungselemente und verbindungselement
DE10205521A1 (de) * 2002-02-08 2003-08-28 Heraeus Gmbh W C Verfahren zur elektrischen Kontaktierung zweier Metallstrukturen
WO2004027866A2 (fr) * 2002-09-23 2004-04-01 Johnson Controls Technology Company Procede d'etablissement d'une liaison dans un substrat metallique integre
TWI400025B (zh) * 2009-12-29 2013-06-21 Subtron Technology Co Ltd 線路基板及其製作方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2977672A (en) * 1958-12-12 1961-04-04 Gen Electric Method of making bonded wire circuit
US3264402A (en) * 1962-09-24 1966-08-02 North American Aviation Inc Multilayer printed-wiring boards
US3155809A (en) * 1964-04-21 1964-11-03 Digital Sensors Inc Means and techniques for making electrical connections

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19522338A1 (de) * 1995-06-20 1997-01-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer Durchkontaktierung sowie Chipträger und Chipträgeranordnung mit einer Durchkontaktierung
DE19522338B4 (de) * 1995-06-20 2006-12-07 Pac Tech-Packaging Technologies Gmbh Chipträgeranordnung mit einer Durchkontaktierung
DE19531970A1 (de) * 1995-08-30 1997-03-06 Siemens Ag Verfahren zur Herstellung einer Verbindung zwischen zumindest zwei elektrischen Leitern, von denen einer auf einem Trägersubstrat angeordnet ist

Also Published As

Publication number Publication date
FR1483563A (fr) 1967-06-02
US3346950A (en) 1967-10-17
GB1077867A (en) 1967-08-02
DE1640468A1 (de) 1970-08-20

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Legal Events

Date Code Title Description
SH Request for examination between 03.10.1968 and 22.04.1971
E77 Valid patent as to the heymanns-index 1977
EHJ Ceased/non-payment of the annual fee