DE1514457A1 - Halbleiteranordnung mit wenigstens einem UEbergang zwischen einem Halbleiter und einem Metall - Google Patents

Halbleiteranordnung mit wenigstens einem UEbergang zwischen einem Halbleiter und einem Metall

Info

Publication number
DE1514457A1
DE1514457A1 DE19651514457 DE1514457A DE1514457A1 DE 1514457 A1 DE1514457 A1 DE 1514457A1 DE 19651514457 DE19651514457 DE 19651514457 DE 1514457 A DE1514457 A DE 1514457A DE 1514457 A1 DE1514457 A1 DE 1514457A1
Authority
DE
Germany
Prior art keywords
semiconductor
metal
semiconducting
arrangement according
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19651514457
Other languages
German (de)
English (en)
Inventor
Winstel Dr Guenter
Heywang Dr Rer Nat Walter
Karl-Heinz Zschauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of DE1514457A1 publication Critical patent/DE1514457A1/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
DE19651514457 1965-05-03 1965-05-03 Halbleiteranordnung mit wenigstens einem UEbergang zwischen einem Halbleiter und einem Metall Pending DE1514457A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DES0096890 1965-05-03

Publications (1)

Publication Number Publication Date
DE1514457A1 true DE1514457A1 (de) 1969-10-16

Family

ID=7520359

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19651514457 Pending DE1514457A1 (de) 1965-05-03 1965-05-03 Halbleiteranordnung mit wenigstens einem UEbergang zwischen einem Halbleiter und einem Metall

Country Status (6)

Country Link
AT (1) AT266217B (enrdf_load_stackoverflow)
CH (1) CH468717A (enrdf_load_stackoverflow)
DE (1) DE1514457A1 (enrdf_load_stackoverflow)
GB (1) GB1144147A (enrdf_load_stackoverflow)
NL (1) NL6605020A (enrdf_load_stackoverflow)
SE (1) SE323148B (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378629A (en) 1979-08-10 1983-04-05 Massachusetts Institute Of Technology Semiconductor embedded layer technology including permeable base transistor, fabrication method
US5298787A (en) * 1979-08-10 1994-03-29 Massachusetts Institute Of Technology Semiconductor embedded layer technology including permeable base transistor
US5032538A (en) * 1979-08-10 1991-07-16 Massachusetts Institute Of Technology Semiconductor embedded layer technology utilizing selective epitaxial growth methods

Also Published As

Publication number Publication date
SE323148B (enrdf_load_stackoverflow) 1970-04-27
AT266217B (de) 1968-11-11
CH468717A (de) 1969-02-15
GB1144147A (en) 1969-03-05
NL6605020A (enrdf_load_stackoverflow) 1966-11-04

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