DE1449564C3 - Recheneinrichtung zur Subtraktion mehrerer Operanden oder zu deren Addition durch Verwendung von Komplementärwerten eines der Operanden - Google Patents

Recheneinrichtung zur Subtraktion mehrerer Operanden oder zu deren Addition durch Verwendung von Komplementärwerten eines der Operanden

Info

Publication number
DE1449564C3
DE1449564C3 DE1449564A DE1449564A DE1449564C3 DE 1449564 C3 DE1449564 C3 DE 1449564C3 DE 1449564 A DE1449564 A DE 1449564A DE 1449564 A DE1449564 A DE 1449564A DE 1449564 C3 DE1449564 C3 DE 1449564C3
Authority
DE
Germany
Prior art keywords
circuit
signal
signals
wire
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE1449564A
Other languages
German (de)
English (en)
Other versions
DE1449564A1 (de
DE1449564B2 (de
Inventor
Gerald James St. Paul Minn. Erickson (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of DE1449564A1 publication Critical patent/DE1449564A1/de
Publication of DE1449564B2 publication Critical patent/DE1449564B2/de
Application granted granted Critical
Publication of DE1449564C3 publication Critical patent/DE1449564C3/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3832—Less usual number representations
    • G06F2207/3836—One's complement

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
DE1449564A 1962-03-29 1963-03-15 Recheneinrichtung zur Subtraktion mehrerer Operanden oder zu deren Addition durch Verwendung von Komplementärwerten eines der Operanden Expired DE1449564C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US183462A US3234370A (en) 1962-03-29 1962-03-29 Segmented arithmetic device

Publications (3)

Publication Number Publication Date
DE1449564A1 DE1449564A1 (de) 1969-06-26
DE1449564B2 DE1449564B2 (de) 1974-09-26
DE1449564C3 true DE1449564C3 (de) 1975-05-07

Family

ID=22672891

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1449564A Expired DE1449564C3 (de) 1962-03-29 1963-03-15 Recheneinrichtung zur Subtraktion mehrerer Operanden oder zu deren Addition durch Verwendung von Komplementärwerten eines der Operanden

Country Status (5)

Country Link
US (1) US3234370A (US07653806-20100126-C00004.png)
BE (1) BE629725A (US07653806-20100126-C00004.png)
DE (1) DE1449564C3 (US07653806-20100126-C00004.png)
GB (1) GB967045A (US07653806-20100126-C00004.png)
NL (1) NL290823A (US07653806-20100126-C00004.png)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1053146A (US07653806-20100126-C00004.png) * 1963-06-04
US3364472A (en) * 1964-03-06 1968-01-16 Westinghouse Electric Corp Computation unit
GB1426273A (en) * 1973-04-13 1976-02-25 Int Computers Ltd Data processing
US4161784A (en) * 1978-01-05 1979-07-17 Honeywell Information Systems, Inc. Microprogrammable floating point arithmetic unit capable of performing arithmetic operations on long and short operands
US4293907A (en) * 1978-12-29 1981-10-06 Bell Telephone Laboratories, Incorporated Data processing apparatus having op-code extension register
US4519077A (en) * 1982-08-30 1985-05-21 Amin Pravin T Digital processing system with self-test capability
US6643765B1 (en) 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB738269A (en) * 1952-04-16 1955-10-12 British Tabulating Mach Co Ltd Improvements in or relating to electronic calculating apparatus
US2936116A (en) * 1952-11-12 1960-05-10 Hnghes Aircraft Company Electronic digital computer
US2913593A (en) * 1954-04-15 1959-11-17 Sperry Rand Corp Half-adder for computers
GB840545A (en) * 1955-06-02 1960-07-06 Kokusai Denshin Denwa Co Ltd Electric borrowing circuit suitable for use in a binary subtractive circuit
US2954178A (en) * 1956-08-10 1960-09-27 Reiners Walter Winding machine with yarn-end finding and tying devices

Also Published As

Publication number Publication date
DE1449564A1 (de) 1969-06-26
DE1449564B2 (de) 1974-09-26
GB967045A (en) 1964-08-19
US3234370A (en) 1966-02-08
BE629725A (US07653806-20100126-C00004.png)
NL290823A (US07653806-20100126-C00004.png)

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Legal Events

Date Code Title Description
SH Request for examination between 03.10.1968 and 22.04.1971
C3 Grant after two publication steps (3rd publication)
E77 Valid patent as to the heymanns-index 1977
EHJ Ceased/non-payment of the annual fee