DE1290789B - Reinigungsverfahren fuer eine Halbleiterkoerper-Oberflaeche - Google Patents

Reinigungsverfahren fuer eine Halbleiterkoerper-Oberflaeche

Info

Publication number
DE1290789B
DE1290789B DEW36263A DEW0036263A DE1290789B DE 1290789 B DE1290789 B DE 1290789B DE W36263 A DEW36263 A DE W36263A DE W0036263 A DEW0036263 A DE W0036263A DE 1290789 B DE1290789 B DE 1290789B
Authority
DE
Germany
Prior art keywords
metallization
copper
semiconductor
solution
bath
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DEW36263A
Other languages
German (de)
English (en)
Inventor
Klein Donald Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of DE1290789B publication Critical patent/DE1290789B/de
Pending legal-status Critical Current

Links

Classifications

    • H10P36/03—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3228—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of AIIIBV compounds, e.g. to make them semi-insulating
    • H10P14/46—
    • H10P95/408—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Detergent Compositions (AREA)
  • Weting (AREA)
DEW36263A 1963-03-18 1964-02-27 Reinigungsverfahren fuer eine Halbleiterkoerper-Oberflaeche Pending DE1290789B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US265612A US3224904A (en) 1963-03-18 1963-03-18 Semiconductor surface cleaning

Publications (1)

Publication Number Publication Date
DE1290789B true DE1290789B (de) 1969-03-13

Family

ID=23011172

Family Applications (1)

Application Number Title Priority Date Filing Date
DEW36263A Pending DE1290789B (de) 1963-03-18 1964-02-27 Reinigungsverfahren fuer eine Halbleiterkoerper-Oberflaeche

Country Status (6)

Country Link
US (1) US3224904A (enExample)
BE (1) BE645051A (enExample)
DE (1) DE1290789B (enExample)
GB (1) GB1059039A (enExample)
NL (1) NL6402568A (enExample)
SE (1) SE300746B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005024914A1 (de) * 2005-05-31 2006-12-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden elektrisch leitfähiger Leitungen in einem integrierten Schaltkreis

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3377263A (en) * 1964-09-14 1968-04-09 Philco Ford Corp Electrical system for etching a tunnel diode
US3436259A (en) * 1966-05-12 1969-04-01 Ibm Method for plating and polishing a silicon planar surface
US4261791A (en) * 1979-09-25 1981-04-14 Rca Corporation Two step method of cleaning silicon wafers
US5911889A (en) * 1995-05-11 1999-06-15 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Aktiengesellschaft Method of removing damaged crystal regions from silicon wafers

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2323599A (en) * 1940-08-17 1943-07-06 Rca Corp Art of finishing cut-crystal elements
US2771382A (en) * 1951-12-12 1956-11-20 Bell Telephone Labor Inc Method of fabricating semiconductors for signal translating devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102005024914A1 (de) * 2005-05-31 2006-12-07 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Ausbilden elektrisch leitfähiger Leitungen in einem integrierten Schaltkreis

Also Published As

Publication number Publication date
BE645051A (enExample) 1964-07-01
NL6402568A (enExample) 1964-09-21
GB1059039A (en) 1967-02-15
US3224904A (en) 1965-12-21
SE300746B (enExample) 1968-05-06

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