DE10392127T5 - Verwendung eines Kontextidentifizierers in einem Zwischenspeicher - Google Patents

Verwendung eines Kontextidentifizierers in einem Zwischenspeicher Download PDF

Info

Publication number
DE10392127T5
DE10392127T5 DE10392127T DE10392127T DE10392127T5 DE 10392127 T5 DE10392127 T5 DE 10392127T5 DE 10392127 T DE10392127 T DE 10392127T DE 10392127 T DE10392127 T DE 10392127T DE 10392127 T5 DE10392127 T5 DE 10392127T5
Authority
DE
Germany
Prior art keywords
thread
identifier
address
context identifier
context
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10392127T
Other languages
German (de)
English (en)
Inventor
Per Hillsboro Hammarlund
K. S. Hillsboro Venkatraman
Aravindh Portland Baktha
Michael Portland Upton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE10392127T5 publication Critical patent/DE10392127T5/de
Ceased legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE10392127T 2002-03-22 2003-03-13 Verwendung eines Kontextidentifizierers in einem Zwischenspeicher Ceased DE10392127T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/104,815 2002-03-22
US10/104,815 US7085889B2 (en) 2002-03-22 2002-03-22 Use of a context identifier in a cache memory
PCT/US2003/007710 WO2003083663A2 (en) 2002-03-22 2003-03-13 Use of context identifiers in cache memory

Publications (1)

Publication Number Publication Date
DE10392127T5 true DE10392127T5 (de) 2004-07-29

Family

ID=28040700

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10392127T Ceased DE10392127T5 (de) 2002-03-22 2003-03-13 Verwendung eines Kontextidentifizierers in einem Zwischenspeicher

Country Status (9)

Country Link
US (1) US7085889B2 (enExample)
JP (1) JP4459628B2 (enExample)
KR (1) KR100634930B1 (enExample)
CN (1) CN1302396C (enExample)
AU (1) AU2003214148A1 (enExample)
DE (1) DE10392127T5 (enExample)
RU (1) RU2285286C2 (enExample)
TW (1) TWI300897B (enExample)
WO (1) WO2003083663A2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6560690B2 (en) * 2000-12-29 2003-05-06 Intel Corporation System and method for employing a global bit for page sharing in a linear-addressed cache
US20040049657A1 (en) * 2002-09-10 2004-03-11 Kling Ralph M. Extended register space apparatus and methods for processors
US7254617B2 (en) * 2002-12-06 2007-08-07 Scott Ruple Distributed cache between servers of a network
US7206916B2 (en) * 2004-03-08 2007-04-17 Sun Microsystems, Inc. Partial address compares stored in translation lookaside buffer
WO2005116837A1 (en) * 2004-05-26 2005-12-08 Intel Corporation Automatic caching generation in network applications
ATE536587T1 (de) 2004-08-31 2011-12-15 Freescale Semiconductor Inc Virtueller adressen-cache und verfahren zum gemeinsamen benutzen von daten unter verwendung einer eindeutigen task-kennung
US20070266199A1 (en) * 2004-09-07 2007-11-15 Freescale Semiconductor, Inc. Virtual Address Cache and Method for Sharing Data Stored in a Virtual Address Cache
KR100899097B1 (ko) * 2007-05-11 2009-05-25 한국과학기술원 복수의 인덱싱 정보를 제공하는 방법 및 이를 이용한 캐쉬메모리 장치
US8024546B2 (en) * 2008-10-23 2011-09-20 Microsoft Corporation Opportunistic page largification
CN101854311A (zh) * 2009-03-31 2010-10-06 国际商业机器公司 在web服务器上传递上下文信息的方法和装置
CN104932990B (zh) * 2015-06-03 2018-05-11 华为技术有限公司 一种高速缓冲存储器中数据块的替换方法和装置
CN107291630B (zh) * 2016-03-30 2020-08-25 华为技术有限公司 一种高速缓冲存储器处理方法及装置
US11379592B2 (en) * 2018-12-20 2022-07-05 Intel Corporation Write-back invalidate by key identifier
US11593109B2 (en) * 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache lines between multiple threads
US11593108B2 (en) 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache footprint between multiple threads

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8823077D0 (en) * 1988-09-30 1988-11-09 Int Computers Ltd Data processing apparatus
US5341487A (en) 1991-12-20 1994-08-23 International Business Machines Corp. Personal computer having memory system with write-through cache and pipelined snoop cycles
US5615343A (en) 1993-06-30 1997-03-25 Intel Corporation Method and apparatus for performing deferred transactions
TW255022B (enExample) 1993-06-30 1995-08-21 Intel Corp
US5568620A (en) 1993-06-30 1996-10-22 Intel Corporation Method and apparatus for performing bus transactions in a computer system
US5548733A (en) 1994-03-01 1996-08-20 Intel Corporation Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system
US5572703A (en) 1994-03-01 1996-11-05 Intel Corporation Method and apparatus for snoop stretching using signals that convey snoop results
BR9506997A (pt) 1994-03-01 1997-11-18 Intel Corp Arquitetura de barramento altamente canalizada
TW400483B (en) 1994-03-01 2000-08-01 Intel Corp High performance symmetric arbitration protocol with support for I/O requirements
US6029217A (en) 1994-10-03 2000-02-22 International Business Machines Corporation Queued arbitration mechanism for data processing system
US5710906A (en) 1995-07-07 1998-01-20 Opti Inc. Predictive snooping of cache memory for master-initiated accesses
KR0164395B1 (ko) 1995-09-11 1999-02-18 김광호 반도체 메모리 장치와 그 리이드 및 라이트 방법
US5812803A (en) 1995-09-29 1998-09-22 Intel Corporation Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller
JPH09101916A (ja) * 1995-10-06 1997-04-15 Fujitsu Ltd マルチプロセス処理装置
US5809522A (en) * 1995-12-18 1998-09-15 Advanced Micro Devices, Inc. Microprocessor system with process identification tag entries to reduce cache flushing after a context switch
US5838995A (en) 1995-12-18 1998-11-17 International Business Machines Corporation System and method for high frequency operation of I/O bus
EP0882266A1 (en) 1996-02-20 1998-12-09 Intergraph Corporation High-availability super server
JP3643425B2 (ja) 1996-02-29 2005-04-27 富士通株式会社 データ処理方法、データ処理装置及びインターフェイスコントローラ
US5754818A (en) * 1996-03-22 1998-05-19 Sun Microsystems, Inc. Architecture and method for sharing TLB entries through process IDS
US6427162B1 (en) * 1996-05-02 2002-07-30 Sun Microsystems, Inc. Separate code and data contexts: an architectural approach to virtual text sharing
US5733603A (en) 1996-06-05 1998-03-31 Kimberly-Clark Corporation Surface modification of hydrophobic polymer substrate
US6012118A (en) 1996-12-30 2000-01-04 Intel Corporation Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
JP3887867B2 (ja) * 1997-02-26 2007-02-28 株式会社日立製作所 構造化文書の登録方法
US6065101A (en) 1997-06-12 2000-05-16 International Business Machines Corporation Pipelined snooping of multiple L1 cache lines
US5919254A (en) 1997-06-25 1999-07-06 Intel Corporation Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
US6336159B1 (en) 1997-06-25 2002-01-01 Intel Corporation Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
US5991855A (en) 1997-07-02 1999-11-23 Micron Electronics, Inc. Low latency memory read with concurrent pipe lined snoops
US5978869A (en) 1997-07-21 1999-11-02 International Business Machines Corporation Enhanced dual speed bus computer system
US6108736A (en) 1997-09-22 2000-08-22 Intel Corporation System and method of flow control for a high speed bus
US5964856A (en) 1997-09-30 1999-10-12 Intel Corporation Mechanism for data strobe pre-driving during master changeover on a parallel bus
US6691118B1 (en) * 1997-10-31 2004-02-10 Oracle International Corporation Context management system for modular software architecture
US6092156A (en) 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
KR100255664B1 (ko) * 1997-12-29 2000-05-01 윤종용 반도체 집적회로의 클락 포워딩 회로 및 클락포워딩 방법
US6006291A (en) 1997-12-31 1999-12-21 Intel Corporation High-throughput interface between a system memory controller and a peripheral device
US6041380A (en) 1998-01-21 2000-03-21 Micron Electronics, Inc. Method for increasing the number of devices capable of being operably connected to a host bus
US6449677B1 (en) 1998-09-03 2002-09-10 Compaq Information Technologies Group, L.P. Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus
US6141747A (en) 1998-09-22 2000-10-31 Advanced Micro Devices, Inc. System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word
US8332478B2 (en) * 1998-10-01 2012-12-11 Digimarc Corporation Context sensitive connected content
RU2140132C1 (ru) * 1999-01-13 1999-10-20 Валов Сергей Геннадьевич Способ двухтактной ассоциативной маршрутизации
US6272604B1 (en) 1999-05-20 2001-08-07 International Business Machines Corporation Contingent response apparatus and method for maintaining cache coherency
US6487621B1 (en) 1999-08-17 2002-11-26 Compaq Information Technologies Group, L.P. Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle
US6615323B1 (en) 1999-09-02 2003-09-02 Thomas Albert Petersen Optimizing pipelined snoop processing
US6591321B1 (en) 1999-11-09 2003-07-08 International Business Machines Corporation Multiprocessor system bus protocol with group addresses, responses, and priorities
CN1173271C (zh) * 1999-12-24 2004-10-27 仁宝电脑工业股份有限公司 具有双重高速缓冲映射存储器的高速缓冲存储器系统
US6609171B1 (en) 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
EP1215577B1 (en) * 2000-08-21 2012-02-22 Texas Instruments Incorporated Fault management and recovery based on task-ID
EP1182571B1 (en) 2000-08-21 2011-01-26 Texas Instruments Incorporated TLB operations based on shared bit
EP1215582A1 (en) 2000-12-15 2002-06-19 Texas Instruments Incorporated Cache memory access system and method
US20020087824A1 (en) * 2000-12-29 2002-07-04 Hum Herbert H.J. System and method for employing a process identifier to minimize aliasing in a linear-addressed cache
US6560690B2 (en) * 2000-12-29 2003-05-06 Intel Corporation System and method for employing a global bit for page sharing in a linear-addressed cache

Also Published As

Publication number Publication date
TW200405155A (en) 2004-04-01
AU2003214148A8 (en) 2003-10-13
HK1069449A1 (en) 2005-05-20
TWI300897B (en) 2008-09-11
RU2285286C2 (ru) 2006-10-10
KR20040017821A (ko) 2004-02-27
AU2003214148A1 (en) 2003-10-13
JP4459628B2 (ja) 2010-04-28
WO2003083663A3 (en) 2004-05-21
CN1552025A (zh) 2004-12-01
WO2003083663A2 (en) 2003-10-09
US7085889B2 (en) 2006-08-01
US20030182512A1 (en) 2003-09-25
CN1302396C (zh) 2007-02-28
KR100634930B1 (ko) 2006-10-17
RU2003136262A (ru) 2005-05-27
JP2006505834A (ja) 2006-02-16

Similar Documents

Publication Publication Date Title
DE69322064T2 (de) Verfahren und System zur Zuteilung mehrerer Befehle in einem superskalaren Prozessorsystem in einem einzigen Zyklus
DE2459006C2 (de) Einrichtung zum Bilden einer absoluten Adresse in einer Datenverarbeitunsanlage
DE112017001027B4 (de) Seitenfehlerbehebung
DE69738101T2 (de) Verwaltung des Zugangs zu Objekten mit Hilfe von Referenzen mit drei Zuständen
DE112005003859B4 (de) Verwalten von Prozessorressourcen während Architekturereignissen
DE60003273T2 (de) Verfahren und Vorrichtung zur Erzeugung einer Eingabeadresse
DE69620702T2 (de) Prozessor mit vom Kompilierer zugewiesener Zwischenspeicherung variabler Länge
DE69802437T2 (de) Feinkörniger übereinstimmungsmechanismus für optimistische parallelsteuerung mit verriegelungsgruppen
DE60320026T2 (de) Verbessertes speichermanagement für echtzeit-anwendungen
DE69822534T2 (de) Gemeinsame Speicherbenutzung mit variablen Blockgrössen für symmetrische Multiporzessor-Gruppen
DE4410060B4 (de) Übersetzungsvorrichtung zum Umsetzen einer virtuellen Speicheradresse in eine physikalische Speicheradresse
DE112004002848B4 (de) Mikroprozessor und Verfahren zum Verifizieren einer Speicherdatei in einem derartigen Mikroprozessor
DE60028069T2 (de) Verfahren und vorrichtung zur kontexterhaltung unter ausführung von übersetzten befehlen
DE69811474T2 (de) Rechnerarchitektur zur aufschiebung von exceptions statischer spekulativer befehle
DE102020104701B4 (de) System zur Lokalisierung von Cachedaten
DE10392127T5 (de) Verwendung eines Kontextidentifizierers in einem Zwischenspeicher
DE102014014076A1 (de) Reduzierte Adressenkonvertierung mit mehreren Seitengrößen
DE202007019502U1 (de) Globaler Überlauf für virtualisierten Transaktionsspeicher
DE4335475A1 (de) Datenverarbeitungseinrichtung mit Cache-Speicher
DE112004000464T5 (de) Ungültigmachen von Speichereinträgen, Löschen von Pufferspeicher-Einträgen
DE2339741A1 (de) Anordnung zur bildung einer relativen adresse fuer einen speicher
DE112018003032B4 (de) Cachestruktur, die ein logisches verzeichnis verwendet
DE10002120A1 (de) Logikstruktur eines Adressumsetzpuffers
DE69418852T2 (de) Kohärenzindexerzeugung für Ein-/Ausgabeanschluss
DE112018002032T5 (de) Gemeinsames nutzen von virtuellen und realen übersetzungen in einem virtuellen cache

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law

Ref document number: 10392127

Country of ref document: DE

Date of ref document: 20040729

Kind code of ref document: P

8131 Rejection