AU2003214148A1 - Use of context identifiers in cache memory - Google Patents

Use of context identifiers in cache memory

Info

Publication number
AU2003214148A1
AU2003214148A1 AU2003214148A AU2003214148A AU2003214148A1 AU 2003214148 A1 AU2003214148 A1 AU 2003214148A1 AU 2003214148 A AU2003214148 A AU 2003214148A AU 2003214148 A AU2003214148 A AU 2003214148A AU 2003214148 A1 AU2003214148 A1 AU 2003214148A1
Authority
AU
Australia
Prior art keywords
cache memory
context identifiers
identifiers
context
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003214148A
Other languages
English (en)
Other versions
AU2003214148A8 (en
Inventor
Aravindh Baktha
Per Hammarlund
Michael Upton
K.S. Venkatraman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2003214148A8 publication Critical patent/AU2003214148A8/xx
Publication of AU2003214148A1 publication Critical patent/AU2003214148A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2003214148A 2002-03-22 2003-03-13 Use of context identifiers in cache memory Abandoned AU2003214148A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/104,815 2002-03-22
US10/104,815 US7085889B2 (en) 2002-03-22 2002-03-22 Use of a context identifier in a cache memory
PCT/US2003/007710 WO2003083663A2 (en) 2002-03-22 2003-03-13 Use of context identifiers in cache memory

Publications (2)

Publication Number Publication Date
AU2003214148A8 AU2003214148A8 (en) 2003-10-13
AU2003214148A1 true AU2003214148A1 (en) 2003-10-13

Family

ID=28040700

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003214148A Abandoned AU2003214148A1 (en) 2002-03-22 2003-03-13 Use of context identifiers in cache memory

Country Status (9)

Country Link
US (1) US7085889B2 (enExample)
JP (1) JP4459628B2 (enExample)
KR (1) KR100634930B1 (enExample)
CN (1) CN1302396C (enExample)
AU (1) AU2003214148A1 (enExample)
DE (1) DE10392127T5 (enExample)
RU (1) RU2285286C2 (enExample)
TW (1) TWI300897B (enExample)
WO (1) WO2003083663A2 (enExample)

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CN101854311A (zh) * 2009-03-31 2010-10-06 国际商业机器公司 在web服务器上传递上下文信息的方法和装置
CN104932990B (zh) * 2015-06-03 2018-05-11 华为技术有限公司 一种高速缓冲存储器中数据块的替换方法和装置
CN107291630B (zh) * 2016-03-30 2020-08-25 华为技术有限公司 一种高速缓冲存储器处理方法及装置
US11379592B2 (en) * 2018-12-20 2022-07-05 Intel Corporation Write-back invalidate by key identifier
US11593109B2 (en) * 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache lines between multiple threads
US11593108B2 (en) 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache footprint between multiple threads

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Also Published As

Publication number Publication date
TW200405155A (en) 2004-04-01
AU2003214148A8 (en) 2003-10-13
HK1069449A1 (en) 2005-05-20
TWI300897B (en) 2008-09-11
RU2285286C2 (ru) 2006-10-10
KR20040017821A (ko) 2004-02-27
JP4459628B2 (ja) 2010-04-28
WO2003083663A3 (en) 2004-05-21
CN1552025A (zh) 2004-12-01
WO2003083663A2 (en) 2003-10-09
US7085889B2 (en) 2006-08-01
US20030182512A1 (en) 2003-09-25
CN1302396C (zh) 2007-02-28
DE10392127T5 (de) 2004-07-29
KR100634930B1 (ko) 2006-10-17
RU2003136262A (ru) 2005-05-27
JP2006505834A (ja) 2006-02-16

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase