KR100634930B1 - 캐시 메모리에서 문맥 식별자를 사용하는 방법 및 장치 - Google Patents

캐시 메모리에서 문맥 식별자를 사용하는 방법 및 장치 Download PDF

Info

Publication number
KR100634930B1
KR100634930B1 KR1020037017291A KR20037017291A KR100634930B1 KR 100634930 B1 KR100634930 B1 KR 100634930B1 KR 1020037017291 A KR1020037017291 A KR 1020037017291A KR 20037017291 A KR20037017291 A KR 20037017291A KR 100634930 B1 KR100634930 B1 KR 100634930B1
Authority
KR
South Korea
Prior art keywords
thread
address
base
page directory
context identifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020037017291A
Other languages
English (en)
Korean (ko)
Other versions
KR20040017821A (ko
Inventor
퍼 하마룬드
케이.에스. 벤카트라만
아라빈드 백다
마이클 업톤
Original Assignee
인텔 코오퍼레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인텔 코오퍼레이션 filed Critical 인텔 코오퍼레이션
Publication of KR20040017821A publication Critical patent/KR20040017821A/ko
Application granted granted Critical
Publication of KR100634930B1 publication Critical patent/KR100634930B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1020037017291A 2002-03-22 2003-03-13 캐시 메모리에서 문맥 식별자를 사용하는 방법 및 장치 Expired - Fee Related KR100634930B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/104,815 2002-03-22
US10/104,815 US7085889B2 (en) 2002-03-22 2002-03-22 Use of a context identifier in a cache memory
PCT/US2003/007710 WO2003083663A2 (en) 2002-03-22 2003-03-13 Use of context identifiers in cache memory

Publications (2)

Publication Number Publication Date
KR20040017821A KR20040017821A (ko) 2004-02-27
KR100634930B1 true KR100634930B1 (ko) 2006-10-17

Family

ID=28040700

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020037017291A Expired - Fee Related KR100634930B1 (ko) 2002-03-22 2003-03-13 캐시 메모리에서 문맥 식별자를 사용하는 방법 및 장치

Country Status (9)

Country Link
US (1) US7085889B2 (enExample)
JP (1) JP4459628B2 (enExample)
KR (1) KR100634930B1 (enExample)
CN (1) CN1302396C (enExample)
AU (1) AU2003214148A1 (enExample)
DE (1) DE10392127T5 (enExample)
RU (1) RU2285286C2 (enExample)
TW (1) TWI300897B (enExample)
WO (1) WO2003083663A2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6560690B2 (en) * 2000-12-29 2003-05-06 Intel Corporation System and method for employing a global bit for page sharing in a linear-addressed cache
US20040049657A1 (en) * 2002-09-10 2004-03-11 Kling Ralph M. Extended register space apparatus and methods for processors
US7254617B2 (en) * 2002-12-06 2007-08-07 Scott Ruple Distributed cache between servers of a network
US7206916B2 (en) * 2004-03-08 2007-04-17 Sun Microsystems, Inc. Partial address compares stored in translation lookaside buffer
WO2005116837A1 (en) * 2004-05-26 2005-12-08 Intel Corporation Automatic caching generation in network applications
ATE536587T1 (de) 2004-08-31 2011-12-15 Freescale Semiconductor Inc Virtueller adressen-cache und verfahren zum gemeinsamen benutzen von daten unter verwendung einer eindeutigen task-kennung
US20070266199A1 (en) * 2004-09-07 2007-11-15 Freescale Semiconductor, Inc. Virtual Address Cache and Method for Sharing Data Stored in a Virtual Address Cache
KR100899097B1 (ko) * 2007-05-11 2009-05-25 한국과학기술원 복수의 인덱싱 정보를 제공하는 방법 및 이를 이용한 캐쉬메모리 장치
US8024546B2 (en) * 2008-10-23 2011-09-20 Microsoft Corporation Opportunistic page largification
CN101854311A (zh) * 2009-03-31 2010-10-06 国际商业机器公司 在web服务器上传递上下文信息的方法和装置
CN104932990B (zh) * 2015-06-03 2018-05-11 华为技术有限公司 一种高速缓冲存储器中数据块的替换方法和装置
CN107291630B (zh) * 2016-03-30 2020-08-25 华为技术有限公司 一种高速缓冲存储器处理方法及装置
US11379592B2 (en) * 2018-12-20 2022-07-05 Intel Corporation Write-back invalidate by key identifier
US11593109B2 (en) * 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache lines between multiple threads
US11593108B2 (en) 2021-06-07 2023-02-28 International Business Machines Corporation Sharing instruction cache footprint between multiple threads

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8823077D0 (en) * 1988-09-30 1988-11-09 Int Computers Ltd Data processing apparatus
US5341487A (en) 1991-12-20 1994-08-23 International Business Machines Corp. Personal computer having memory system with write-through cache and pipelined snoop cycles
US5615343A (en) 1993-06-30 1997-03-25 Intel Corporation Method and apparatus for performing deferred transactions
TW255022B (enExample) 1993-06-30 1995-08-21 Intel Corp
US5568620A (en) 1993-06-30 1996-10-22 Intel Corporation Method and apparatus for performing bus transactions in a computer system
US5548733A (en) 1994-03-01 1996-08-20 Intel Corporation Method and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus system
US5572703A (en) 1994-03-01 1996-11-05 Intel Corporation Method and apparatus for snoop stretching using signals that convey snoop results
BR9506997A (pt) 1994-03-01 1997-11-18 Intel Corp Arquitetura de barramento altamente canalizada
TW400483B (en) 1994-03-01 2000-08-01 Intel Corp High performance symmetric arbitration protocol with support for I/O requirements
US6029217A (en) 1994-10-03 2000-02-22 International Business Machines Corporation Queued arbitration mechanism for data processing system
US5710906A (en) 1995-07-07 1998-01-20 Opti Inc. Predictive snooping of cache memory for master-initiated accesses
KR0164395B1 (ko) 1995-09-11 1999-02-18 김광호 반도체 메모리 장치와 그 리이드 및 라이트 방법
US5812803A (en) 1995-09-29 1998-09-22 Intel Corporation Method and apparatus for controlling data transfers between a bus and a memory device using a multi-chip memory controller
JPH09101916A (ja) * 1995-10-06 1997-04-15 Fujitsu Ltd マルチプロセス処理装置
US5809522A (en) * 1995-12-18 1998-09-15 Advanced Micro Devices, Inc. Microprocessor system with process identification tag entries to reduce cache flushing after a context switch
US5838995A (en) 1995-12-18 1998-11-17 International Business Machines Corporation System and method for high frequency operation of I/O bus
EP0882266A1 (en) 1996-02-20 1998-12-09 Intergraph Corporation High-availability super server
JP3643425B2 (ja) 1996-02-29 2005-04-27 富士通株式会社 データ処理方法、データ処理装置及びインターフェイスコントローラ
US5754818A (en) * 1996-03-22 1998-05-19 Sun Microsystems, Inc. Architecture and method for sharing TLB entries through process IDS
US6427162B1 (en) * 1996-05-02 2002-07-30 Sun Microsystems, Inc. Separate code and data contexts: an architectural approach to virtual text sharing
US5733603A (en) 1996-06-05 1998-03-31 Kimberly-Clark Corporation Surface modification of hydrophobic polymer substrate
US6012118A (en) 1996-12-30 2000-01-04 Intel Corporation Method and apparatus for performing bus operations in a computer system using deferred replies returned without using the address bus
JP3887867B2 (ja) * 1997-02-26 2007-02-28 株式会社日立製作所 構造化文書の登録方法
US6065101A (en) 1997-06-12 2000-05-16 International Business Machines Corporation Pipelined snooping of multiple L1 cache lines
US5919254A (en) 1997-06-25 1999-07-06 Intel Corporation Method and apparatus for switching between source-synchronous and common clock data transfer modes in a multiple processing system
US6336159B1 (en) 1997-06-25 2002-01-01 Intel Corporation Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system
US5991855A (en) 1997-07-02 1999-11-23 Micron Electronics, Inc. Low latency memory read with concurrent pipe lined snoops
US5978869A (en) 1997-07-21 1999-11-02 International Business Machines Corporation Enhanced dual speed bus computer system
US6108736A (en) 1997-09-22 2000-08-22 Intel Corporation System and method of flow control for a high speed bus
US5964856A (en) 1997-09-30 1999-10-12 Intel Corporation Mechanism for data strobe pre-driving during master changeover on a parallel bus
US6691118B1 (en) * 1997-10-31 2004-02-10 Oracle International Corporation Context management system for modular software architecture
US6092156A (en) 1997-11-05 2000-07-18 Unisys Corporation System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations
KR100255664B1 (ko) * 1997-12-29 2000-05-01 윤종용 반도체 집적회로의 클락 포워딩 회로 및 클락포워딩 방법
US6006291A (en) 1997-12-31 1999-12-21 Intel Corporation High-throughput interface between a system memory controller and a peripheral device
US6041380A (en) 1998-01-21 2000-03-21 Micron Electronics, Inc. Method for increasing the number of devices capable of being operably connected to a host bus
US6449677B1 (en) 1998-09-03 2002-09-10 Compaq Information Technologies Group, L.P. Method and apparatus for multiplexing and demultiplexing addresses of registered peripheral interconnect apparatus
US6141747A (en) 1998-09-22 2000-10-31 Advanced Micro Devices, Inc. System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word
US8332478B2 (en) * 1998-10-01 2012-12-11 Digimarc Corporation Context sensitive connected content
RU2140132C1 (ru) * 1999-01-13 1999-10-20 Валов Сергей Геннадьевич Способ двухтактной ассоциативной маршрутизации
US6272604B1 (en) 1999-05-20 2001-08-07 International Business Machines Corporation Contingent response apparatus and method for maintaining cache coherency
US6487621B1 (en) 1999-08-17 2002-11-26 Compaq Information Technologies Group, L.P. Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle
US6615323B1 (en) 1999-09-02 2003-09-02 Thomas Albert Petersen Optimizing pipelined snoop processing
US6591321B1 (en) 1999-11-09 2003-07-08 International Business Machines Corporation Multiprocessor system bus protocol with group addresses, responses, and priorities
CN1173271C (zh) * 1999-12-24 2004-10-27 仁宝电脑工业股份有限公司 具有双重高速缓冲映射存储器的高速缓冲存储器系统
US6609171B1 (en) 1999-12-29 2003-08-19 Intel Corporation Quad pumped bus architecture and protocol
EP1215577B1 (en) * 2000-08-21 2012-02-22 Texas Instruments Incorporated Fault management and recovery based on task-ID
EP1182571B1 (en) 2000-08-21 2011-01-26 Texas Instruments Incorporated TLB operations based on shared bit
EP1215582A1 (en) 2000-12-15 2002-06-19 Texas Instruments Incorporated Cache memory access system and method
US20020087824A1 (en) * 2000-12-29 2002-07-04 Hum Herbert H.J. System and method for employing a process identifier to minimize aliasing in a linear-addressed cache
US6560690B2 (en) * 2000-12-29 2003-05-06 Intel Corporation System and method for employing a global bit for page sharing in a linear-addressed cache

Also Published As

Publication number Publication date
TW200405155A (en) 2004-04-01
AU2003214148A8 (en) 2003-10-13
HK1069449A1 (en) 2005-05-20
TWI300897B (en) 2008-09-11
RU2285286C2 (ru) 2006-10-10
KR20040017821A (ko) 2004-02-27
AU2003214148A1 (en) 2003-10-13
JP4459628B2 (ja) 2010-04-28
WO2003083663A3 (en) 2004-05-21
CN1552025A (zh) 2004-12-01
WO2003083663A2 (en) 2003-10-09
US7085889B2 (en) 2006-08-01
US20030182512A1 (en) 2003-09-25
CN1302396C (zh) 2007-02-28
DE10392127T5 (de) 2004-07-29
RU2003136262A (ru) 2005-05-27
JP2006505834A (ja) 2006-02-16

Similar Documents

Publication Publication Date Title
US5475827A (en) Dynamic look-aside table for multiple size pages
US7165164B2 (en) Method and apparatus including heuristic for sharing TLB entries
KR100634930B1 (ko) 캐시 메모리에서 문맥 식별자를 사용하는 방법 및 장치
US4797814A (en) Variable address mode cache
US5860138A (en) Processor with compiler-allocated, variable length intermediate storage
US7194597B2 (en) Method and apparatus for sharing TLB entries
US7461209B2 (en) Transient cache storage with discard function for disposable data
US9058284B1 (en) Method and apparatus for performing table lookup
JPH10232834A (ja) キャッシュメモリを作動する方法およびコンピュータシステム
US7039768B2 (en) Cache predictor for simultaneous multi-threaded processor system supporting multiple transactions
WO1996041250A2 (en) System and method for processing multiple requests and out of order returns
EP3830719A1 (en) Binary search procedure for control table stored in memory system
JPH1124992A (ja) バックマップを有しないマルチセット仮想キャッシュでの制限された仮想アドレスエイリアシングおよび高速コンテキスト切換え
US10545877B2 (en) Apparatus and method for accessing an address translation cache
US20050027960A1 (en) Translation look-aside buffer sharing among logical partitions
US6567907B1 (en) Avoiding mapping conflicts in a translation look-aside buffer
EP0611462B1 (en) Memory unit including a multiple write cache
US11455253B2 (en) Set indexing for first-level and second-level set-associative cache
US9665494B2 (en) Parallel lookup in first and second value stores
CN117785738B (zh) 页表预取方法、装置、芯片及存储介质
HK1069449B (en) Use of a context identifier in cache memory
EP1262876B1 (en) Multiprocessing system with shared translation lookaside buffer
GB2455406A (en) Translation Lookaside Buffer for a co-processor

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20090925

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20101011

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20101011

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000