DE10344850A1 - Verfahren zur Bestimmung der relativen Lagegenauigkeit zweier Strukturelemente auf einem Wafer - Google Patents

Verfahren zur Bestimmung der relativen Lagegenauigkeit zweier Strukturelemente auf einem Wafer Download PDF

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Publication number
DE10344850A1
DE10344850A1 DE10344850A DE10344850A DE10344850A1 DE 10344850 A1 DE10344850 A1 DE 10344850A1 DE 10344850 A DE10344850 A DE 10344850A DE 10344850 A DE10344850 A DE 10344850A DE 10344850 A1 DE10344850 A1 DE 10344850A1
Authority
DE
Germany
Prior art keywords
wafer
resist
mask
structural component
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10344850A
Other languages
English (en)
Inventor
Jens Staecker
Thorsten Schedel
Heiko Hommen
Jens Uwe Bruch
Piedad Fernandez-Martinez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10344850A priority Critical patent/DE10344850A1/de
Priority to US10/950,165 priority patent/US7186484B2/en
Publication of DE10344850A1 publication Critical patent/DE10344850A1/de
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Eine Meßmarke (3) zur Bestimmung der relativen Lagegenauigkeit einer mit zwei Masken (3, 4) vorgenommenen, sukzessiven Projektion auf einen Wafer (5) umfaßt zwei auf jeweils einer der Masken (1, 2) gebildete Strukturelemente (10, 20). Die Strukturelemente (10, 2ß) überlappen sich in bezug auf ihre Position auf den Masken, so daß bei der Projektion des zweiten Strukturelementes (20) eine aufgrund des ersten Strukturelementes gebildete elektrisch leitende Struktur (30) auf dem Wafer (5) durch Entfernung eines Anteils (31) überformt wird. In einer elektrischen Linienbreitenmessung wird die verringerte Breite (CD, CD¶30a¶) der Struktur (30) gemessen und entweder mit der ursprünglichen Breite (62) oder mit derjenigen Breite (CD¶30b¶) eines weiteren durch die Überformung entstandenen Teilelementes (30b) verglichen.
DE10344850A 2003-09-26 2003-09-26 Verfahren zur Bestimmung der relativen Lagegenauigkeit zweier Strukturelemente auf einem Wafer Ceased DE10344850A1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10344850A DE10344850A1 (de) 2003-09-26 2003-09-26 Verfahren zur Bestimmung der relativen Lagegenauigkeit zweier Strukturelemente auf einem Wafer
US10/950,165 US7186484B2 (en) 2003-09-26 2004-09-24 Method for determining the relative positional accuracy of two structure elements on a wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10344850A DE10344850A1 (de) 2003-09-26 2003-09-26 Verfahren zur Bestimmung der relativen Lagegenauigkeit zweier Strukturelemente auf einem Wafer

Publications (1)

Publication Number Publication Date
DE10344850A1 true DE10344850A1 (de) 2005-04-28

Family

ID=34398985

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10344850A Ceased DE10344850A1 (de) 2003-09-26 2003-09-26 Verfahren zur Bestimmung der relativen Lagegenauigkeit zweier Strukturelemente auf einem Wafer

Country Status (2)

Country Link
US (1) US7186484B2 (de)
DE (1) DE10344850A1 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016221243A1 (de) * 2016-10-27 2017-11-09 Carl Zeiss Smt Gmbh Verfahren und Vorrichtung zur Charakterisierung eines durch wenigstens einen Lithographieschritt strukturierten Wafers

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7701231B2 (en) * 2007-03-20 2010-04-20 Cummins Filtration Ip, Inc Apparatus, system, and method for detecting cracking within an aftertreatment device
FR2925689B1 (fr) * 2007-12-21 2010-08-13 Saint Gobain Ct Recherches Dispositif de detection de fissures radiales dans un filtre a particules
JP6338929B2 (ja) * 2014-05-23 2018-06-06 東芝メモリ株式会社 レチクルマーク配置方法およびレチクルマーク配置プログラム
WO2017130366A1 (ja) * 2016-01-29 2017-08-03 株式会社 日立ハイテクノロジーズ パターン計測装置及びコンピュータープログラム

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437760A (en) * 1981-12-07 1984-03-20 The Perkin-Elmer Corp. Reusable electrical overlay measurement circuit and process
US4538105A (en) * 1981-12-07 1985-08-27 The Perkin-Elmer Corporation Overlay test wafer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5916715A (en) * 1997-09-08 1999-06-29 Advanced Micro Devices, Inc. Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements
JP3363082B2 (ja) 1997-12-05 2003-01-07 株式会社東芝 パターンの合わせずれの電気的測定方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437760A (en) * 1981-12-07 1984-03-20 The Perkin-Elmer Corp. Reusable electrical overlay measurement circuit and process
US4538105A (en) * 1981-12-07 1985-08-27 The Perkin-Elmer Corporation Overlay test wafer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016221243A1 (de) * 2016-10-27 2017-11-09 Carl Zeiss Smt Gmbh Verfahren und Vorrichtung zur Charakterisierung eines durch wenigstens einen Lithographieschritt strukturierten Wafers

Also Published As

Publication number Publication date
US7186484B2 (en) 2007-03-06
US20050260510A1 (en) 2005-11-24

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8131 Rejection