DE10343565B3 - Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop - Google Patents

Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop Download PDF

Info

Publication number
DE10343565B3
DE10343565B3 DE10343565A DE10343565A DE10343565B3 DE 10343565 B3 DE10343565 B3 DE 10343565B3 DE 10343565 A DE10343565 A DE 10343565A DE 10343565 A DE10343565 A DE 10343565A DE 10343565 B3 DE10343565 B3 DE 10343565B3
Authority
DE
Germany
Prior art keywords
phase
signal
operating voltage
latch circuit
evalaution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10343565A
Other languages
English (en)
Inventor
Stephan Henzler
Georg Georgakos
Joerg Berthold
Doris Schmitt-Landsiedel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10343565A priority Critical patent/DE10343565B3/de
Priority to EP04764805A priority patent/EP1665529A2/de
Priority to JP2005518691A priority patent/JP4575300B2/ja
Priority to PCT/EP2004/009853 priority patent/WO2005039050A2/de
Priority to US10/563,040 priority patent/US20060273838A1/en
Priority to CNB2004800187879A priority patent/CN100433552C/zh
Application granted granted Critical
Publication of DE10343565B3 publication Critical patent/DE10343565B3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356121—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit with synchronous operation

Landscapes

  • Logic Circuits (AREA)

Abstract

Master-Latchschaltung (10) mit Signalpegelverschiebung für ein Flip-Flop (1), das durch ein Taktsignal (Clk) getaktet wird, DOLLAR A wobei die Master-Latchschaltung (10) aufweist: DOLLAR A eine Signalverzögerungsschaltung (13), die das anliegende Taktsignal (Clk) mit einer bestimmten Zeitverzögerung (DELTAT) verzögert und invertiert; und DOLLAR A einen Schaltungsknoten (14), der in einer Aufladephase, in der das anliegende Taktsignal (Clk) logisch niedrig ist, auf eine Betriebsspannung (V¶B¶) aufgeladen wird und der in einer Auswertephase, wenn das anliegende Taktsignal (Clk) und das verzögerte invertierte Taktsignal DOLLAR I1 logisch hoch sind, abhängig von einem anliegenden Datensignal (D) entladbar ist, wobei das Datensignal nur Transistoren eines einzigen Typs (entweder nur N- oder nur P-Kanal) ansteuert. Die Master-Latchschaltung (10) weist nur eine einzige Versorgungsspannung auf.
DE10343565A 2003-09-19 2003-09-19 Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop Expired - Fee Related DE10343565B3 (de)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DE10343565A DE10343565B3 (de) 2003-09-19 2003-09-19 Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop
EP04764805A EP1665529A2 (de) 2003-09-19 2004-09-03 Master-latchschaltung mit signalpegelverschiebung für ein dynamisches flip-flop
JP2005518691A JP4575300B2 (ja) 2003-09-19 2004-09-03 ダイナミック・フリップ・フロップの信号レベル置換を備えたマスタ・ラッチ回路
PCT/EP2004/009853 WO2005039050A2 (de) 2003-09-19 2004-09-03 Master-latchschaltung mit signalpegelverschiebung für ein dynamisches flip-flop
US10/563,040 US20060273838A1 (en) 2003-09-19 2004-09-03 Master latch circuit with signal level displacement for a dynamic flip flop
CNB2004800187879A CN100433552C (zh) 2003-09-19 2004-09-03 用于动态触发器的具有信号电平移位功能的主锁存电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10343565A DE10343565B3 (de) 2003-09-19 2003-09-19 Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop

Publications (1)

Publication Number Publication Date
DE10343565B3 true DE10343565B3 (de) 2005-03-10

Family

ID=34177853

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10343565A Expired - Fee Related DE10343565B3 (de) 2003-09-19 2003-09-19 Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop

Country Status (6)

Country Link
US (1) US20060273838A1 (de)
EP (1) EP1665529A2 (de)
JP (1) JP4575300B2 (de)
CN (1) CN100433552C (de)
DE (1) DE10343565B3 (de)
WO (1) WO2005039050A2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2338791A1 (de) 2009-12-16 2011-06-29 MBDA France Halte- und Abwurfsystem für Lasten für Transportflugzeug

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8020018B2 (en) * 2006-09-28 2011-09-13 Infineon Technologies Ag Circuit arrangement and method of operating a circuit arrangement
CN101859595B (zh) * 2009-04-07 2012-04-04 丰田自动车株式会社 锁存装置及锁存方法
KR101573343B1 (ko) 2009-06-16 2015-12-02 삼성전자주식회사 플립플롭 회로 및 이를 구비하는 컴퓨터 시스템
US9001950B2 (en) * 2012-03-09 2015-04-07 Canon Kabushiki Kaisha Information processing apparatus, serial communication system, method of initialization of communication therefor, and serial communication apparatus
US8994429B1 (en) * 2014-03-13 2015-03-31 Oracle International Corporation Energy efficient flip-flop with reduced setup time
US9473113B1 (en) * 2015-09-24 2016-10-18 Qualcomm Incorporated Power management with flip-flops
US9564901B1 (en) 2015-12-17 2017-02-07 Apple Inc. Self-timed dynamic level shifter with falling edge generator
WO2018137751A1 (en) * 2017-01-24 2018-08-02 Telefonaktiebolaget Lm Ericsson (Publ) Variable delay circuits
JP6389937B1 (ja) * 2017-08-29 2018-09-12 力晶科技股▲ふん▼有限公司 電源制御回路及び電源制御回路を備えた論理回路装置
CN108107343B (zh) * 2017-11-22 2019-12-06 宁波大学 一种基于真实sh时间的老化传感器
US10389335B1 (en) 2018-05-04 2019-08-20 Apple Inc. Clock pulse generation circuit
CN110995206B (zh) * 2019-12-13 2023-07-28 海光信息技术股份有限公司 触发器电路
CN114531138B (zh) * 2022-01-12 2025-12-16 中国科学院微电子研究所 一种单粒子加固触发器电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0808022A2 (de) * 1996-05-16 1997-11-19 Mitsubishi Denki Kabushiki Kaisha Synchron mit Taktsignalen arbeitende Verriegelungsschaltung
EP0851581A2 (de) * 1996-12-30 1998-07-01 Sony Corporation Kippschaltung
US6507228B2 (en) * 2001-05-03 2003-01-14 International Business Machines Corporation Method and apparatus for latching a clocked data signal

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2272536B1 (de) * 1974-05-20 1978-02-03 Tokyo Shibaura Electric Co
JPS6393223A (ja) * 1986-10-07 1988-04-23 Oki Electric Ind Co Ltd 多段ダイナミツク論理回路
JPH07249982A (ja) * 1994-03-10 1995-09-26 Fujitsu Ltd ダイナミック論理回路装置
US5764089A (en) * 1995-09-11 1998-06-09 Altera Corporation Dynamic latching device
US5917355A (en) * 1997-01-16 1999-06-29 Sun Microsystems, Inc. Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism
US6043698A (en) * 1997-11-03 2000-03-28 Arm Limited Voltage level shifter
JP3652950B2 (ja) * 2000-02-02 2005-05-25 富士通株式会社 電圧変換回路及び電圧変換回路の制御回路
US6433601B1 (en) * 2000-12-15 2002-08-13 Koninklijke Philips Electronics N.V. Pulsed D-Flip-Flop using differential cascode switch
DE10204487B4 (de) * 2002-01-30 2004-03-04 Infineon Technologies Ag Temperatursensor
US20060267653A1 (en) * 2005-05-25 2006-11-30 Honeywell International Inc. Single-event-effect hardened circuitry

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0808022A2 (de) * 1996-05-16 1997-11-19 Mitsubishi Denki Kabushiki Kaisha Synchron mit Taktsignalen arbeitende Verriegelungsschaltung
EP0851581A2 (de) * 1996-12-30 1998-07-01 Sony Corporation Kippschaltung
US6507228B2 (en) * 2001-05-03 2003-01-14 International Business Machines Corporation Method and apparatus for latching a clocked data signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2338791A1 (de) 2009-12-16 2011-06-29 MBDA France Halte- und Abwurfsystem für Lasten für Transportflugzeug
WO2011080410A1 (fr) 2009-12-16 2011-07-07 Mbda France Systeme d'emport et de largage de charge pour avion de transport

Also Published As

Publication number Publication date
JP2006515494A (ja) 2006-05-25
US20060273838A1 (en) 2006-12-07
EP1665529A2 (de) 2006-06-07
JP4575300B2 (ja) 2010-11-04
WO2005039050A3 (de) 2005-06-09
WO2005039050A2 (de) 2005-04-28
CN1816967A (zh) 2006-08-09
CN100433552C (zh) 2008-11-12

Similar Documents

Publication Publication Date Title
DE10343565B3 (de) Master-Latchschaltung mit Signalpegelverschiebung für ein dynamisches Flip-Flop
US6958639B2 (en) Digital duty cycle correction circuit and method for multi-phase clock
USRE48735E1 (en) Use of a recirculating delay line with a time-to-digital converter
EP0889411A3 (de) Integrierte Schaltung mit Phasenregelschleife und eingebautem Selbsttest von Phase und Phasenzittern
JPH118532A5 (de)
CA2400830A1 (en) A phase detector
EP0940758A3 (de) Serielle Busbeschleunigungsschaltung
KR20150123929A (ko) 낮은-레이턴시 전압 부스트 회로를 갖는 전압 레벨 시프터
EP0898284A3 (de) Halbleiterspeicher mit einer Prüfschaltung
EP0963042A3 (de) Getaktete Komparatorschaltung
EP1199804A3 (de) Phasen- und Frequenzkomparator
US20100156495A1 (en) Latch circuit and clock signal dividing circuit
US6518848B2 (en) Oscillation stop detection circuit
EP0946017A3 (de) Vorrichtung zur Datenübertragung
US6348821B1 (en) Frequency doubler with 50% duty cycle output
KR100342736B1 (ko) 정전 용량 변화를 이용한 감지 회로
US20100141307A1 (en) Frequency multiplier and method for frequency multiplying
KR100742142B1 (ko) 듀얼에지 ｍ／ｎ：ｄ 카운터
US20020172196A1 (en) Signal detector
US5303279A (en) Timer circuit
WO1998020609A1 (en) Low power wake-up system and method
DK0834992T3 (da) Monolitisk MOS-switched-capacitor-kredsløb med on-chip oscillator
JP2006135888A (ja) データ通信装置、データ通信システム及びデータ通信方法
JP3154302B2 (ja) 位相差検出回路
WO2006004705A3 (en) Dynamic-to-static logic converter

Legal Events

Date Code Title Description
8100 Publication of patent without earlier publication of application
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee