DE102019111632A1 - Periodische kalibrationen während der selbstauffrischung einer speichereinrichtung - Google Patents

Periodische kalibrationen während der selbstauffrischung einer speichereinrichtung Download PDF

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Publication number
DE102019111632A1
DE102019111632A1 DE102019111632.5A DE102019111632A DE102019111632A1 DE 102019111632 A1 DE102019111632 A1 DE 102019111632A1 DE 102019111632 A DE102019111632 A DE 102019111632A DE 102019111632 A1 DE102019111632 A1 DE 102019111632A1
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Prior art keywords
self
memory
memory device
storage device
calibrations
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Pending
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DE102019111632.5A
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German (de)
English (en)
Inventor
Christopher E. Cox
Bill Nale
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Intel Corp
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Intel Corp
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Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE102019111632A1 publication Critical patent/DE102019111632A1/de
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
DE102019111632.5A 2018-06-06 2019-05-06 Periodische kalibrationen während der selbstauffrischung einer speichereinrichtung Pending DE102019111632A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/001,869 2018-06-06
US16/001,869 US10692560B2 (en) 2018-06-06 2018-06-06 Periodic calibrations during memory device self refresh

Publications (1)

Publication Number Publication Date
DE102019111632A1 true DE102019111632A1 (de) 2019-12-12

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE102019111632.5A Pending DE102019111632A1 (de) 2018-06-06 2019-05-06 Periodische kalibrationen während der selbstauffrischung einer speichereinrichtung

Country Status (4)

Country Link
US (3) US10692560B2 (https=)
JP (1) JP7556185B2 (https=)
CN (1) CN110570886A (https=)
DE (1) DE102019111632A1 (https=)

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US11977770B2 (en) * 2018-06-04 2024-05-07 Lodestar Licensing Group Llc Methods for generating notifications for updated information from mode registers of a memory device to a host and memory devices and systems employing the same
US11217284B2 (en) * 2020-04-03 2022-01-04 Micron Technology, Inc. Memory with per pin input/output termination and driver impedance calibration
JP6890701B1 (ja) * 2020-05-19 2021-06-18 華邦電子股▲ふん▼有限公司Ｗｉｎｂｏｎｄ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏｒｐ． コードシフト算出回路およびコードシフト値の算出方法
US11664062B2 (en) * 2020-07-24 2023-05-30 Advanced Micro Devices, Inc. Memory calibration system and method
US11971832B2 (en) * 2020-10-07 2024-04-30 Infineon Technologies LLC Methods, devices and systems for high speed transactions with nonvolatile memory on a double data rate memory bus
US11914905B1 (en) * 2021-07-15 2024-02-27 Xilinx, Inc. Memory self-refresh re-entry state

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Publication number Priority date Publication date Assignee Title
US7020818B2 (en) * 2004-03-08 2006-03-28 Intel Corporation Method and apparatus for PVT controller for programmable on die termination
US7454586B2 (en) 2005-03-30 2008-11-18 Intel Corporation Memory device commands
US9171585B2 (en) * 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US7432731B2 (en) * 2005-06-30 2008-10-07 Intel Corporation Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations
US7562234B2 (en) 2005-08-25 2009-07-14 Apple Inc. Methods and apparatuses for dynamic power control
JP4916699B2 (ja) * 2005-10-25 2012-04-18 エルピーダメモリ株式会社 Ｚｑキャリブレーション回路及びこれを備えた半導体装置
US7372293B2 (en) 2005-12-07 2008-05-13 Intel Corporation Polarity driven dynamic on-die termination
US7342411B2 (en) 2005-12-07 2008-03-11 Intel Corporation Dynamic on-die termination launch latency reduction
US7414426B2 (en) 2005-12-07 2008-08-19 Intel Corporation Time multiplexed dynamic on-die termination
JP4282713B2 (ja) * 2006-11-28 2009-06-24 エルピーダメモリ株式会社 キャリブレーション回路を有する半導体装置及びキャリブレーション方法
US20080197877A1 (en) 2007-02-16 2008-08-21 Intel Corporation Per byte lane dynamic on-die termination
US8949520B2 (en) * 2009-01-22 2015-02-03 Rambus Inc. Maintenance operations in a DRAM
US8307270B2 (en) * 2009-09-03 2012-11-06 International Business Machines Corporation Advanced memory device having improved performance, reduced power and increased reliability
JP2011187115A (ja) * 2010-03-08 2011-09-22 Elpida Memory Inc 半導体装置
KR101692128B1 (ko) 2012-03-27 2017-01-02 인텔 코포레이션 리프레시 모드들 동안의 메모리 디바이스들에서의 전력 소비의 감소
US9780782B2 (en) 2014-07-23 2017-10-03 Intel Corporation On-die termination control without a dedicated pin in a multi-rank system
US9811420B2 (en) 2015-03-27 2017-11-07 Intel Corporation Extracting selective information from on-die dynamic random access memory (DRAM) error correction code (ECC)
US10025685B2 (en) * 2015-03-27 2018-07-17 Intel Corporation Impedance compensation based on detecting sensor data
US20170255412A1 (en) 2016-03-04 2017-09-07 Intel Corporation Techniques for Command Based On Die Termination

Also Published As

Publication number Publication date
US10692560B2 (en) 2020-06-23
US20190043557A1 (en) 2019-02-07
JP7556185B2 (ja) 2024-09-26
US20210005245A1 (en) 2021-01-07
US20220157374A1 (en) 2022-05-19
US11790976B2 (en) 2023-10-17
JP2019212294A (ja) 2019-12-12
US11276453B2 (en) 2022-03-15
CN110570886A (zh) 2019-12-13

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