DE102012103430B4 - Verfahren zum Heften von Chips auf ein Substrat - Google Patents

Verfahren zum Heften von Chips auf ein Substrat Download PDF

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Publication number
DE102012103430B4
DE102012103430B4 DE102012103430.3A DE102012103430A DE102012103430B4 DE 102012103430 B4 DE102012103430 B4 DE 102012103430B4 DE 102012103430 A DE102012103430 A DE 102012103430A DE 102012103430 B4 DE102012103430 B4 DE 102012103430B4
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Germany
Prior art keywords
functional layer
substrate
contacts
chips
chip
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DE102012103430.3A
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German (de)
English (en)
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DE102012103430A1 (de
Inventor
Jürgen Burggraf
Markus Wimplinger
Harald Wiesbauer
Alfred Sigl
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EV Group E Thallner GmbH
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EV Group E Thallner GmbH
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Priority to DE102012103430.3A priority Critical patent/DE102012103430B4/de
Application filed by EV Group E Thallner GmbH filed Critical EV Group E Thallner GmbH
Priority to SG2014011613A priority patent/SG2014011613A/en
Priority to KR1020147028521A priority patent/KR102121080B1/ko
Priority to PCT/EP2013/055556 priority patent/WO2013156234A1/de
Priority to JP2015506146A priority patent/JP6223421B2/ja
Priority to ATA9123/2013A priority patent/AT517747B1/de
Priority to CN201380020754.7A priority patent/CN104520979B/zh
Priority to US14/395,084 priority patent/US9245869B2/en
Publication of DE102012103430A1 publication Critical patent/DE102012103430A1/de
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Publication of DE102012103430B4 publication Critical patent/DE102012103430B4/de
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    • H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
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    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating
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    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
    • H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9205—Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
    • H—ELECTRICITY
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/381—Pitch distance

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
DE102012103430.3A 2012-04-19 2012-04-19 Verfahren zum Heften von Chips auf ein Substrat Active DE102012103430B4 (de)

Priority Applications (8)

Application Number Priority Date Filing Date Title
DE102012103430.3A DE102012103430B4 (de) 2012-04-19 2012-04-19 Verfahren zum Heften von Chips auf ein Substrat
KR1020147028521A KR102121080B1 (ko) 2012-04-19 2013-03-18 칩 접촉 요소를 위한 오프닝을 가진 기능성 층이 구비된 기판에 접촉 요소로 칩을 접합하기 위한 방법
PCT/EP2013/055556 WO2013156234A1 (de) 2012-04-19 2013-03-18 Verfahren zum heften von chips mit kontaktelement auf ein mit einer funktionsschicht mit öffnungen für die chipkontaktelementen versehenes substrat
JP2015506146A JP6223421B2 (ja) 2012-04-19 2013-03-18 コンタクトエレメントを備えたチップを、チップコンタクトエレメントに対する開口を有する機能層を備えた基板に仮接合する方法
SG2014011613A SG2014011613A (en) 2012-04-19 2013-03-18 Method for fastening chips with a contact element onto a substrate provided with a functional layer having openings for the chip contact elements
ATA9123/2013A AT517747B1 (de) 2012-04-19 2013-03-18 Verfahren zum Heften von Chips mit Kontaktelement auf ein mit einer Funktionsschicht mit Öffnungen für die Chipkontaktelementen versehenes Substrat
CN201380020754.7A CN104520979B (zh) 2012-04-19 2013-03-18 将具有接触元件的芯片固定到设置有带有芯片接触元件的开口的功能层的衬底上的方法
US14/395,084 US9245869B2 (en) 2012-04-19 2013-03-18 Method for fastening chips with a contact element onto a substrate provided with a functional layer having openings for the chip contact elements

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CN (1) CN104520979B (zh)
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DE (1) DE102012103430B4 (zh)
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CN105189409B (zh) * 2013-03-29 2018-11-09 三菱综合材料株式会社 金属-陶瓷板层压体的制造装置及制造方法、功率模块用基板的制造装置及制造方法

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US6168972B1 (en) * 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
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TWI230989B (en) * 2004-05-05 2005-04-11 Megic Corp Chip bonding method
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DE102006045094A1 (de) * 2006-09-21 2008-03-27 Qimonda Ag Verfahren zum Herstellen von Chip-zu-Chip-Verbindungen
JP2010171118A (ja) 2009-01-21 2010-08-05 Panasonic Electric Works Co Ltd 実装部品の表面実装方法、その方法を用いて得られる実装部品構造体、及びその方法に用いられるアンダーフィル用液状エポキシ樹脂組成物
KR20120091691A (ko) * 2011-02-09 2012-08-20 삼성전자주식회사 휨 방지용 접합패턴을 갖는 반도체 소자 및 그 제조방법

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US5384952A (en) * 1990-12-26 1995-01-31 Nec Corporation Method of connecting an integrated circuit chip to a substrate
DE19651566A1 (de) * 1996-12-11 1998-06-18 David Finn Chip-Modul sowie Verfahren zu dessen Herstellung
US6168972B1 (en) * 1998-12-22 2001-01-02 Fujitsu Limited Flip chip pre-assembly underfill process
US20040169275A1 (en) * 2003-02-27 2004-09-02 Motorola, Inc. Area-array device assembly with pre-applied underfill layers on printed wiring board
US20060068521A1 (en) * 2004-09-29 2006-03-30 Song-Hua Shi Method of fabricating microelectronic package using no-flow underfill technology and microelectronic package formed according to the method

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AT517747B1 (de) 2019-03-15
US9245869B2 (en) 2016-01-26
JP6223421B2 (ja) 2017-11-01
KR20150013448A (ko) 2015-02-05
AT517747A5 (de) 2017-04-15
CN104520979A (zh) 2015-04-15
CN104520979B (zh) 2018-09-11
JP2015515135A (ja) 2015-05-21
SG2014011613A (en) 2014-06-27
KR102121080B1 (ko) 2020-06-10
US20150104902A1 (en) 2015-04-16
WO2013156234A1 (de) 2013-10-24

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