DE102009016681B4 - A method of manufacturing a silicon carbide semiconductor device - Google Patents

Abstract

A method of manufacturing a silicon carbide semiconductor device having an accumulation mode MOSFET, in which an accumulation mode channel formed by controlling an application voltage to a gate electrode (9) is controlled so that an electric current is passed between a source electrode ( 11) and a drain electrode (13) flowing through a source region (4) and a drift layer (2), comprising: making a substrate (1) from silicon carbide having a first or second conductivity type; forming the drift layer (2) on the substrate (1) ), wherein the drift layer (2) is made of silicon carbide and has a first conductivity type, the concentration of impurities of the drift layer (2) being lower than the concentration of impurities of the substrate (1); forming a current scattering layer (30) on the drift layer (2), wherein the current scattering layer (30) is made of silicon carbide and has the first conductivity type, the concentration of impurities tomen of the current scattering layer (30) is higher than the concentration of foreign atoms of the drift layer (2); formation of a base region (3) on the current scattering layer (30), the base region (3) being made of silicon carbide and having the second conductivity type; formation of the Source region (4) on the base region (3), the source region (4) being made of silicon carbide and having the first conductivity type, the concentration of impurities of the source region (4) being higher than the concentration of impurities of the drift layer (2); Formation of a trench (6) which extends deeper than the source region (4) and the base region (3) in order to reach the current scattering layer (30) or the drift layer (2), the source region (4) and the base region (3 ) are arranged on each side of the trench (6); formation of the channel layer (7) on a side wall of the trench (6), the channel layer (7) being made of silicon carbide and having the first conductivity type; g a gate insulation layer (8) on a surface of the channel layer (7), the gate insulation layer (8) being arranged at a predetermined distance from the base region (3); formation of the gate electrode (9) on the gate insulation layer (8) within the trench ( 6); Formation of the source electrode (11), which is electrically connected to the source region (4) and the base region (3); Formation of the drain electrode (13) on the rear side of the substrate (1); andforming a deep layer (10) which is arranged below the base region (3) and reaches the drift layer (2) by penetrating the current scattering layer (30), the deep layer (10) extending and extending deeper than the trench (6) extends in a direction perpendicular to the side wall of the trench (6), wherein the deep layer (10) has the second conductivity type, the formation of the deep layer (10) the formation of a lower layer (10a) of the deep layer (10) and an upper layer ( 10b) of the deep layer (10), the lower layer (10a) extending in one direction, the upper layer (10b) being arranged in a position corresponding to the lower layer (10a) and being connected to the lower layer (10a) , forming the lower layer (10a) comprises applying a first mask (20) on a surface of the drift layer (2) and performing ion implantation using the first mask (20), and forming the upper layer (10b) comprises attaching a second mask (21) to a surface of the current scattering layer (30) and performing ion implantation using the second mask (21) (corresponding to the semiconductor device shown in FIG. 1).

Description

The present invention relates to a method of manufacturing a silicon carbide (SiC) semiconductor device having a trench gate.

In recent years, SiC has received attention as a material for a device for generating electricity with high breakdown electric field strength. A SiC semiconductor device can control a large electric current because of its high breakdown electric field strength. Therefore, it is expected that a SiC semiconductor device will be used for controlling a motor of a hybrid vehicle.

Growing channel density is an effective way to allow a larger electric current to flow into a SiC semiconductor device. Therefore, in a silicon transistor, a MOSFET having a trench gate structure has been introduced and put into practical use. A trench gate structure can be applied to a SiC semiconductor. However, a big problem arises when the trench gate structure is applied to SiC. Namely, since the breakdown electric field strength of SiC is ten times greater than that of silicon, the voltage applied to a SiC semiconductor device during use is about ten times higher than the voltage applied to a silicon device during use. Therefore, the voltage applied to a gate insulating film formed in a trench in SiC is about ten times greater than the voltage applied to a gate insulating film formed in a silicon device. As a result, breakdown of the gate insulating film is likely to occur at a corner of the trench. A result of a simulation for this indicates that when a voltage of 650 V is applied to a drain, an electric field of 4.9 MV / cm acts on a gate insulation film in a trench. For practical use, the electric field must be equal to or less than 3 MV / cm. Taking long-term reliability into consideration, it is preferable that the electric field be equal to or less than 2 MV / cm.

U.S. 6,133,587 A ( JP H09-199724 A ) describes a SiC semiconductor device designed to solve the above problem. In this SiC semiconductor device, the thickness of a bottom wall of a trench is made larger than the thickness of a side wall of the trench in order to reduce the electric field concentration at the bottom wall of the trench. Specifically, a trench gate structure with an a-plane (1120) is formed using a substrate with a c-plane (000-1) made of 4H-SiC. That is, a trench having an a-plane side wall and a c-plane bottom wall is formed using the c-plane substrate. When a gate insulation layer is formed in the trench by thermal oxidation, the oxidation rate of the c-plane is five times greater than that of the a-plane. Accordingly, the thickness of the gate insulation layer in the trench becomes five times greater on the trench bottom wall than on the trench side wall. Therefore, the electric field concentration at the trench bottom wall can be reduced.

In a simulation, the thickness of the gate insulation layer on the trench sidewall is set to 40 nm, the thickness of the gate insulation layer on the trench bottom wall is set to 200 nm, and a voltage of 650 V is applied to a drain. The result of the simulation shows that the electric field concentration at the gate insulation layer in the trench is reduced to 3.9 MV / cm. However, the reduction in the electric field concentration is insufficient and further reduction is necessary.

The inventors of the present invention have the patent application (Japanese Patent Application Publication No. JP 2009 - 117 593 A submitted for a structure to achieve further reduction of the electric field concentration. The structure has a p-type deep layer which is arranged on the opposite side of a trench gate over an n ⁺ -type source region and a p-type base region. That is, the p-type deep layer is disposed under a p ⁺ -type contact region which is electrically connected to the p-type base region and a source electrode. The p-type deep layer extends deeper than the bottom wall of the trench gate.

When the SiC semiconductor device having this structure is manufactured, the trench gate and the p-type deep layer are manufactured by different methods. Since matching between the trench gate and the p-type deep layer is difficult, there may be some amount of variation in the distance from a sidewall of the trench gate to the p-type deep layer. As a result, the products can have different properties and the production rates can be small.

The inventors of the present invention have another patent application (Japanese Patent Application Publication No. JP 2009 - 194 065 A filed for a structure in which a p-type deep layer extends in a direction perpendicular to the part of a trench sidewall where a channel region is formed. Since in the structure of a barrier layer to a high degree to the drift layer side of the n ^- type at a PN junction between the deep layer of p-type and the drift layer of n ^- extends type, it is less likely that a high voltage is applied to a gate oxide film due to a drain voltage. Therefore, the electric field concentration in the gate oxide layer can be reduced, in particular on the bottom wall of the trench, so that the gate oxide layer can be prevented from breaking down. Further, since the longitudinal direction of the trench is not perpendicular to the longitudinal direction of the p-type deep layer, device properties are not affected by poor alignment between the masks used to form the trench and the p-type deep layer.

Further, it has been proposed that an n-type current scattering layer is formed between the n ^- -type layer and the p-type base layer in order to further reduce the ON resistance. The n-type current scattering layer allows an electric current that passes through the channel region to be widely scattered, so that the electric current can flow through the n ^- -type drift layer. In this way, the ON resistance is further reduced. In such a structure that the p-type base region and the p-type deep layer are separated by the n-type current scattering layer, the effect of reducing the electric field concentration due to the fact that the p-type deep layer cannot is fixed to a source potential, are weakened. It has therefore been proposed that the p-type layer is formed by performing ion implantation of p-type impurity atoms (foreign ions) into the surface of an n-type current scattering layer after the n-type current scattering layer is formed.

However, in the case that the p-type layer is formed by ion implantation of p-type foreign atoms (foreign ions) into the surface of the n-type current scattering layer after the n-type current scattering layer is formed, the depth of the p-type deep layer becomes -Type low. Accordingly, the difference in depth between the bottom wall of the p-type deep layer and the bottom wall of the trench becomes small, so that the effect of reducing the electric field concentration can be reduced. Further, since it is difficult to control the depth of the trench, there is a possibility that the depth of the trench becomes greater than the depth of the p-type deep layer. Since the depth of the p-type deep layer depends on the energy of ion implantation, the depth of the p-type deep layer can be increased by performing the ion implantation at high energy. However, an enormous amount of energy is required to form the p-type deep layer of the desired depth in a solid material such as SiC. Therefore, there is a need to manufacture an ion implantation apparatus which can perform ion implantation by using an enormous amount of energy. However, since such an ion implantation apparatus is expensive, a different approach is necessary.

In the DE 698 28 588 T2 describes a SiC semiconductor device in which an additional p-conductive layer is formed on the trench bottom. A high performance trench MOSFET transistor is also included DE 195 30 109 A1 revealed and will be in the EP 14 60 681 B1 SiC semiconductor devices and methods for their manufacture are described.

Given this situation, it is an object of the present invention to provide a method for manufacturing a SiC semiconductor device which has a structure for reducing the electric field concentration in a gate oxide layer formed in a trench. In this structure, a base layer is connected to a deep layer. The process ensures that the deep layer is deeper than the trench.

According to one aspect of the present invention, a method for manufacturing a silicon carbide semiconductor device having an accumulation mode MOSFET (MOSFET of the collection type), in which an accumulation mode channel (channel of the collection type) in a channel layer by controlling the application voltage on a gate electrode is controlled so that an electric current flows between a source electrode and a drain electrode through a source region and a drift layer, the formation of a substrate, and the formation of a drift layer on the substrate. The drift layer is made of silicon carbide and has the first conductivity type. The concentration of foreign atoms (foreign ions) of the drift layer is lower than the concentration of foreign atoms (foreign ions) of the substrate. The method further includes attaching a mask to a surface of the drift layer and then performing ion implantation using the mask to form a lower layer of a deep layer that extends in one direction. The deep layer has the first conductivity type. The method further includes forming a current scattering layer on the drift layer. The current scattering layer has the first conductivity type, and the concentration of foreign atoms (foreign ions) of the current scattering layer is higher than the concentration of foreign atoms (foreign ions) of the drift layer. The method further includes attaching another mask to a surface of the current scattering layer and then performing ion implantation using the other mask to form an upper layer of the deep layer in a position corresponding to the lower layer in such a way that the upper layer and the lower layer are interconnected. The method further includes forming a base area on the surfaces of the Current scattering layer and the deep layer. The base area is made of silicon carbide and has the second conductivity type.

According to another aspect of the present invention, a method of manufacturing a silicon carbide semiconductor device having a MOSFET of the inversion type, in which a channel of the inversion type, which is in a surface part of a base area arranged on a sidewall of a trench, by controlling an application voltage a gate electrode is formed, is controlled so that an electric current flows between a source electrode and a drain electrode through a source region and a drift layer, the formation of a substrate, and the formation of the drift layer on the substrate. The drift layer is made of silicon carbide and has the first conductivity type. The concentration of foreign atoms (foreign ions) of the drift layer is lower than the concentration of foreign atoms (foreign ions) of the substrate. The method further includes attaching a mask to a surface of the drift layer and then performing ion implantation using the mask to form a lower layer of a deep layer that extends in one direction. The deep layer has the first conductivity type. The method further includes forming a current scattering layer on the drift layer. The current scattering layer has the first conductivity type, and the concentration of foreign atoms (foreign ions) of the current scattering layer is higher than the concentration of foreign atoms (foreign ions) of the drift layer. The method further includes attaching another mask to a surface of the current scattering layer and then performing ion implantation using the other mask to form an upper layer of the deep layer in a position corresponding to the lower layer in such a way that the upper layer and the lower layer are interconnected. The method further includes forming a basal area on the surfaces of the current scattering layer and the deep layer. The base area is made of silicon carbide and has the second conductivity type.

• 1 ein Diagramm, das eine Querschnittsansicht eines Grabengate-MOSFET der Sammlungsart gemäß der ersten Ausführungsform der vorliegenden Erfindung darstellt;
• 2A ein Diagramm, das eine Querschnittsansicht entlang der Linie IIA-IIA in 1 darstellt, 2B ein Diagramm, das eine Querschnittsansicht entlang der Linie IIB-IIB in 1 darstellt, 2C ein Diagramm, das eine Querschnittsansicht entlang der Linie IIC-IIC in 1 darstellt, und 2D ein Diagramm, das eine Querschnittsansicht entlang der Linie IID-IID in 1 darstellt;
• 3A und 3B Diagramme, die ein Verfahren zur Herstellung des MOSFET der 1 verdeutlichen;
• 4A und 4B Diagramme, die ein Verfahren verdeutlichen, das auf das Verfahren der 3A und 3B folgt;
• 5A und 5B Diagramme, die ein Verfahren verdeutlichen, das auf das Verfahren gemäß 4A und 4B folgt;
• 6A und 6B Diagramme, die ein Verfahren verdeutlichen, das auf das Verfahren gemäß 5A und 5B folgt;
• 7A und 7B Diagramme, die ein Verfahren verdeutlichen, das auf das Verfahren gemäß 6A und 6B folgt;
• 8A und 8B Diagramme, die ein Verfahren verdeutlichen, das auf das Verfahren gemäß 7A und 7B folgt;
• 9A und 9B Diagramme, die ein Verfahren verdeutlichen, das auf das Verfahren gemäß 8A und 8B folgt;
• 10A und 10B Diagramme, die ein Verfahren verdeutlichen, das auf das Verfahren gemäß 9A und 9B folgt;
• 11 ein Diagramm, das eine Querschnittsansicht eines Grabengate-MOSFET der Sammlungsart gemäß einer zweiten Ausführungsform der vorliegenden Erfindung darstellt;
• 12 ein Diagramm, das eine Querschnittsansicht eines Grabengate-MOSFET der Sammlungsart gemäß einer dritten Ausführungsform der vorliegenden Erfindung darstellt; und
• 13 ein Diagramm, das eine Querschnittsansicht eines Grabengate-MOSFET der Inversionsart gemäß einer vierten Ausführungsform der vorliegenden Erfindung darstellt.

The above and other features, properties, and advantages of the present invention will become more apparent from the following detailed description, which is made upon review by the accompanying figures. In the figures:

• 1 Fig. 13 is a diagram showing a cross-sectional view of a collection type trench gate MOSFET according to the first embodiment of the present invention;
• 2A FIG. 13 is a diagram showing a cross-sectional view taken along line IIA-IIA in FIG 1 represents 2 B FIG. 13 is a diagram showing a cross-sectional view taken along line IIB-IIB in FIG 1 represents 2C FIG. 13 is a diagram showing a cross-sectional view taken along line IIC-IIC in FIG 1 represents, and 2D FIG. 13 is a diagram showing a cross-sectional view taken along line IID-IID in FIG 1 represents;
• 3A and 3B Diagrams showing a method of making the MOSFET's 1 clarify;
• 4A and 4B Diagrams showing a procedure that is based on the procedure of the 3A and 3B follows;
• 5A and 5B Diagrams illustrating a method that is based on the method according to 4A and 4B follows;
• 6A and 6B Diagrams illustrating a method that is based on the method according to 5A and 5B follows;
• 7A and 7B Diagrams illustrating a method that is based on the method according to 6A and 6B follows;
• 8A and 8B Diagrams illustrating a method that is based on the method according to 7A and 7B follows;
• 9A and 9B Diagrams illustrating a method that is based on the method according to 8A and 8B follows;
• 10A and 10B Diagrams illustrating a method that is based on the method according to 9A and 9B follows;
• 11 Figure 13 is a diagram illustrating a cross-sectional view of a trench gate MOSFET of the collection type according to a second embodiment of the present invention;
• 12 Fig. 13 is a diagram illustrating a cross-sectional view of a collection type trench gate MOSFET according to a third embodiment of the present invention; and
• 13th FIG. 12 is a diagram illustrating a cross-sectional view of an inversion type trench gate MOSFET according to a fourth embodiment of the present invention.

Embodiments of the present invention are described below with reference to the figures.

(First embodiment)

A first embodiment of the present invention will be described. Here, a trench gate MOSFET of the collection type is described as an element provided with a SiC semiconductor device.

1 Figure 13 is a cross-sectional perspective view of a trench gate MOSFET in accordance with the present invention. This figure corresponds to a cell of the MOSFET. Although this figure shows one cell of the MOSFET, multiple MOSFETs are each having the same structure as that in FIG 1 MOSFET shown arranged adjacent to one another. 2A-2D are diagrams showing cross-sectional views of the MOSFET of FIG 1 represent. 2A FIG. 11 is the cross-sectional view along the line IIA-IIA parallel to the xz plane of FIG 1 . 2 B FIG. 11 is the cross-sectional view along the line IIB-IIB parallel to the xz plane of FIG 1 . 2C FIG. 13 is the cross-sectional view along the line IIC-IIC parallel to the yz plane of FIG 1 . 2D FIG. 11 is the cross-sectional view along the line IID-IID parallel to the yz plane of FIG 1 .

The in 1 and the 2A-2D MOSFET shown uses a substrate 1 of the n ⁺ type made of SiC as a semiconductor substrate. For example, the substrate has 1 from the n ⁺ -type the thickness of about 300 microns and is with an impurity (foreign ion) of the n-type, such as. B. phosphorus, doped in a concentration of about 1.0 × 10 ¹⁹ / cm ³ . A drift layer 2 n ^- type of SiC is on a surface of the substrate 1 formed of the n ⁺ type. For example, the drift layer has 2 of the n ^- -type a thickness of about 10 microns to about 15 microns and is with an impurity (foreign ion) of the n-type, such as. B. phosphorus, doped in a concentration of about 3.0 × 10 ¹⁵ / cm ³ to about 7.0 × 10 ¹⁵ / cm ³ . The concentration of foreign atoms (foreign ions) in the drift layer 2 of the n ^- type can be kept unchanged in the direction of its thickness. The concentration of foreign atoms (foreign ions) is preferably in the drift layer 2 of n ^- -type distributed in the direction of their thickness so that the concentration of foreign atoms (foreign ions) on the side close to the substrate 1 of the n ⁺ type is higher than on the side facing the substrate 1 is removed from the n ⁺ type. For example, the concentration of foreign atoms (foreign ions) of 3 µm to 5 µm part of the drift layer 2 of the n ^- type from the surface of the substrate 1 of the n ⁺ type may be about 2.0 × 10 ¹⁵ / cm ³ higher than that of any other part of the drift layer 2 of the n ^- type. In such an approach, the internal resistance is the drift layer 2 n ^- -type is decreased so that the ON resistance can be decreased.

In a surface area of the drift layer 2 of the n ^- type becomes a base area 3 p-type by a current scattering layer 30th of n-type, which will be described later. A source area 4th of the n ⁺ type and a body layer 5 of the p ⁺ -type are on the ground area 3 formed of the p-type.

For example, the basic area has 3 p-type has a thickness of about 2.0 µm and is coated with a p-type impurity (foreign ion) such as. B. boron or aluminum, doped in a concentration of about 5.0 × 10 ¹⁶ / cm ³ to about 2.0 × 10 ¹⁹ / cm ³ . For example, the source area has 4th from the n ⁺ -type a thickness of about 0.3 microns and is with an impurity (foreign ion) of the n-type, such as. B. phosphorus, doped in a concentration (surface concentration) of about 1.0 × 10 ²¹ / cm ³ in its surface area. For example, the body layer has 5 from the p ⁺ -type a thickness of about 0.3 microns and is with a foreign atom (foreign ion) of the p-type, such as. B. boron or aluminum, doped in a concentration (surface concentration) of about 1.0 × 10 ²¹ / cm ³ in their surface area. The source area 4th n ⁺ type is formed on each side of a trench gate structure which will be described later. The body layer 5 p ⁺ type is on the opposite side of the trench gate structure above the source region 4th formed of the n ⁺ type.

A ditch 6th is formed so that it has the drift layer 2 of the n ^- type achieved by the basic range 3 p-type, the source region 4th of the n ⁺ type and the current scattering layer 30th n-type, which will be described later, is pierced. For example, the ditch 6th a width of 1.4 µm to 2.0 µm and a depth of more than 2.0 µm (e.g. 2.4 µm). The basic area 3 p-type and the source region 4th n ⁺ type are arranged to be in contact with a side wall of the trench 6th are. There is also a channel layer 7th n-type on an inner surface of the trench 6th educated. For example is the channel layer 7th n-type with an n-type foreign atom (foreign ion) such as B. phosphorus, doped in a concentration of 1.0 × 10 ¹⁶ / cm ³ . The layer 7th n-type is suitable for forming a channel region and has the thickness corresponding to a type that is normally off. For example, the channel layer has 7th of the n-type, a thickness of 0.3 µm to 1.0 µm at the bottom wall of the trench 6th and a thickness of 0.1 µm to 0.3 µm on the side wall of the trench 6th .

Further is a surface of the channel layer 7th n-type with a gate oxide layer 8th covered. The ditch 6th is with a gate electrode 9 filled made of doped polysilicon deposited on a surface of the gate oxide layer 8th is formed. The gate oxide layer 8th is formed by touching the surface of the channel layer 7th n-type thermally oxidized, and has a thickness of about 10 nm on both the bottom wall and the side wall of the trench 6th .

The trench gate structure is formed in this way. This trench gate structure extends in the y direction of 1 . That is, the longitudinal direction of the trench gate structure is the y-direction of 1 . Several trench gate structures are parallel to one another in the x direction 1 arranged. Furthermore, both the source area extend 4th of the n ⁺ type as well as the body layer 5 of the p ⁺ type in the longitudinal direction of the trench gate structure.

The current scattering layer 30th n-type is between the drift layer 2 of the n ^- type and the base layer 3 p-type arranged and in contact with the channel layer 7th of the n-type. For example is the current scattering layer 30th n-type with an n-type foreign atom (foreign ion) such as B. phosphorus, doped in a concentration of 2.0 × 10 ¹⁵ / cm ³ to 1.0 × 10 ¹⁷ / cm ³ . The concentration of foreign atoms (foreign ions) in the current scattering layer 30th n-type is higher than that of the drift layer 2 of the n ^- type and preferably higher than that of the channel layer 7th of the n-type. The depth of the current scattering layer 30th n-type is not limited to any particular value. In this embodiment, the current scattering layer has 30th n-type a depth that allows the trench 6th the current scattering layer 30th of the n-type penetrates. For example, the depth of the current scattering layer 30th n-type can be set to about 0.3 µm.

There is also a deep layer 10 p-type below the base area 3 formed of the p-type. The deep layer 10 p-type reaches a predetermined depth by removing the current scattering layer 30th of the n-type penetrates. The deep layer 10 p-type extends in one direction (x-direction in 1 ) perpendicular to part of the side wall of the trench 6th . A channel area is in the part of the side wall of the trench 6th educated. That is, the deep layer 10 p-type extends in a direction perpendicular to the longitudinal direction of the trench 6th .

The deep layer 10 p-type includes a lower layer 10a that are in the drift layer 2 of the n ^- type, and an upper layer 10b that are in the current scattering layer 30th is formed of the n-type. The deep layer 10 p-type extends deeper than the bottom wall of the trench 6th . That is, the deep layer 10 p-type extends deeper than the bottom of the channel layer 7th of the n-type. For example is the depth of the deep layer 10 p-type from the surface of the drift layer 2 of the n ^- type in the range from about 2.6 µm to about 3.0 µm, and the depth of the deep layer 10 p-type from the bottom of the ground area 3 p-type is in the range from about 0.9 µm to about 1.3 µm. The width (i.e., dimension in the y direction of 1 ) the deep layer 10 p-type is in the range of 0.6 µm to 1.0 µm. For example is the deep layer 10 p-type with an impurity (foreign ion) of p-type such as B. boron or aluminum, doped in a concentration of 1.0 × 10 ¹⁷ / cm ³ to 1.0 × 10 ¹⁹ / cm ³ . Several deep layers 10 p-type are arranged parallel to each other in the longitudinal direction of the trench gate structure. For example is the separation distance between adjacent deep layers 10 p-type in the range of 2 µm to 3 µm.

A source electrode 11 and a gate wire (not shown) are placed on the surfaces of the source region 4th of the n ⁺ type, the body layer 5 of the p ⁺ type and the gate electrode 9 educated. The source electrode 11 and the gate wire are formed from a plurality of metal materials (e.g., Ni / Al). The source electrode 11 and the gate wire may be in conductive contact with an n-type SiC (especially the source region 4th of the n ⁺ type and the gate electrode 9 , which is n-doped). The source electrode 11 and the gate wire may be in conductive contact with a p-type SiC (specifically the body layer 5 of the p ⁺ type and the gate electrode 9 , which is p-doped). The source electrode 11 and the gate wire are placed on an interlayer insulating film 12 formed for electrical insulation. The source electrode 11 is in electrical contact with the source region 4th of the n ⁺ type and the body layer 5 p ⁺ type through a contact hole formed in the interlayer insulating film 12 is formed. The gate wire is through the contact hole with the gate electrode 9 in electrical contact.

A drain electrode 13th is on the back of the substrate 1 of the n ⁺ type and in electrical contact with the substrate 1 formed of the n ⁺ type. In this way, an n-channel collection type trench gate MOSFET is formed.

• In dem Fall, dass SiC eine hohe Konzentration an Fremdatomen (Fremdionen) von zum Beispiel 1,0 × 10¹⁹/cm³ besitzt, hat SiC eine innere Spannung von etwa 3 V, bevor eine Gatespannung an die Gatelektrode 9 angelegt wird. Selbst wenn die Spannung der Sourceelektrode 110V beträgt, wirkt deshalb der Grundbereich 3 vom p-Typ als ein Potenzial von -3 V. Im Ergebnis erstreckt sich eine Sperrschicht von dem Grundbereich 3 vom p-Typ und ein Teil in der Nähe des Grundbereichs 3 vom p-Typ wirkt als Isolator. Selbst wenn eine positive Spannung an die Drainelektrode 13 angelegt wird, wirkt deshalb die Kanalschicht 7 vom n-Typ als Isolator. Im Ergebnis fließt kein elektrischer Strom zwischen der Sourceelektrode 11 und der Drainelektrode 13, da die Elektronen die Kanalschicht 7 vom n-Typ nicht erreichen können.

The collection-type trench gate MOSFET works in the following way:

• In the case that SiC has a high concentration of foreign atoms (foreign ions) of, for example, 1.0 × 10 ¹⁹ / cm ³ , SiC has an internal voltage of about 3 V before a gate voltage is applied to the gate electrode 9 is created. Therefore, even if the voltage of the source electrode is 110V, the basic area works 3 p-type as a potential of -3 V. As a result, a barrier layer extends from the ground area 3 p-type and a part near the ground area 3 p-type acts as an insulator. Even if a positive voltage is applied to the drain electrode 13th is applied, the channel layer therefore acts 7th n-type as an insulator. As a result, no electric current flows between the source electrode 11 and the drain electrode 13th because the electrons enter the channel layer 7th of the n-type cannot achieve.

In the OFF state (gate voltage = 0 V, drain voltage = 650 V, source voltage = 0 V) extends even when a voltage is applied to the drain electrode 13th is applied, a barrier layer of between the ground area 3 p-type and the drift layer 2 of the n ^- type (including the channel layer 7th n-type) due to reverse bias. Because in this case the concentration of the basic area 3 p-type is much larger than that of the drift layer 2 of the n ^- type, most of the barrier layer extends to the drift layer side 2 of the n ^- type. If, for example, the concentration of the basic area 3 p-type is ten times larger than that of the drift layer 2 of the n ^- type in the In the present embodiment, the barrier layer extends to the base area side 3 p-type by about 0.7 µm and to the side of the drift layer 2 of the n ^- type by about 7.0 µm. However, since the thickness of the base area 3 p-type is 2.0 µm, which is more than the size of the expansion of the barrier layer, a piercing effect can be avoided. Furthermore, the junction is more extensive than when the drain voltage is 0V. Accordingly, since the part that acts as an insulator extends further, no electric current flows between the source electrode 11 and the drain electrode 13th .

Furthermore, since the gate voltage is 0 V, an electric field is generated between the drain and the gate. Therefore, it is possible that an electric field concentration at the bottom of the gate oxide layer 8th can occur. However, there the deep layer 10 p-type extends deeper than the trench 6th , the barrier layer extends largely to the side of the drift layer 2 of the n ^- type at the PN zone transition between the deep layer 10 p-type and the drift layer 2 of the n ^- type. Therefore, it is less likely to have a high voltage due to the drain voltage across the gate oxide layer 8th is created. In particular, the extent to which the barrier layer extends to the side of the drift layer 2 of the n ^- type can be increased by reducing the concentration of foreign atoms (foreign ions) in the deep layer 10 of the p-type higher than that of the fundamental domain 3 p-type. This can reduce the electric field concentration in the gate oxide layer 8th especially on the bottom wall of the trench 6th so that punching through of the gate oxide layer 8th can be prevented.

The result of a simulation indicates that the electric field strength in the gate oxide layer 8th on the bottom wall of the trench 6th 2.0 MV / cm is when a voltage of 650 V is applied to the drain electrode 13th is created. The gate oxide layer 8th can withstand this electric field strength of 2.0 MV / cm. Even if, therefore, a voltage of 650 V is applied to the drain electrode 13th is applied, the gate oxide layer 8th not destroyed, so that a breakdown voltage of 650 V can be achieved.

In the present embodiment, the deep layer 10 of the p-type, which causes a reduction in the electric field, in the current scattering layer 30th formed of the n-type. Furthermore is the deep layer 10 of the p-type with the base region 3 connected by the p-type so that the deep layer 10 p-type can be fixed to a source potential. This can prevent the effect of reducing the electric field from being lowered. When the deep layer 10 p-type and the basic range 3 p-type through the deep layer 10 being shared by the p-type, it becomes impossible to direct a surge current from the deep layer 10 p-type to the ground area 3 from the p-type. Therefore, there is a possibility that an electric current can flow through a PNP junction formed with these parts, and a large electric current can flow due to the PNP junction acting as a transistor. As a result, element strike-through can occur. However, there the deep layer 10 of the p-type with the base region 3 p-type, it is possible to prevent such element breakdown.

On the other hand, in the ON state (gate voltage = 20 V, drain voltage = 1 V, source voltage = 0 V), a voltage of 20 V is applied to the gate electrode 9 applied so that the channel layer 7th the n-type can serve as the collection type channel. Therefore, electrons reach from the source electrode 11 are fed in, the drift layer 2 of the n ^- type, being the source area 4th of the n ⁺ type and the channel layer 7th traverse of n-type. Therefore, an electric current flows between the source electrode 11 and the drain electrode 13th .

In this case, the ON resistance is 4.9 mΩ · cm ² , which is 15% higher than the ON resistance of 4.3 mΩ · cm ² in the case that the deep layer 10 p-type of the present embodiment is not formed. This is because no channel is formed on the sidewall of the trench gate structure where the deep layer 10 is formed of the p-type. However, the increase in ON resistance is not great, and it can also be adjusted by adjusting the width of the deep layer 10 of p-type and the separation distance between the adjacent deep layer 10 p-type. Therefore, increasing the ON resistance is not a big problem.

Next, a method of manufacturing the in 1 trench gate MOSFET shown. 3A-10B are cross-sectional views illustrating methods of making the in 1 illustrate the trench gate MOSFET shown. Each 3A , 4A , 5A , 6A , 7A , 8A , 9A and 10A FIG. 11 is a cross-sectional view taken along line IIA-IIA parallel to the xz plane of FIG 1 and corresponds 2A . Each 3B , 4B , 5B , 6B , 7B , 8B , 9B and 10B FIG. 11 is a cross-sectional view taken along line IID-IID parallel to the yz plane of FIG 1 and corresponds 2D . The method is described below with reference to these figures.

(Procedure shown in FIGS. 3A and 3B)

First thing is the substrate 1 of the n ⁺ -type with a thickness of, for example, about 300 microns and doped with an impurity (foreign ion) of the n-type, such as. B. phosphorus, in a concentration of, for example, 1.0 × 10 ¹⁹ / cm ³ . After the drain electrode 13th on the back of the substrate 1 of the n ⁺ type is formed, the drift layer 2 n ^- type of SiC epitaxially on the surface of the substrate 1 grown up of the n ⁺ -type. For example, the drift layer has 2 n ^- -type has a thickness of about 15 microns and is with an impurity (foreign ion) of n-type, such as. B. phosphorus, doped in a concentration of about 3.0 × 10 ¹⁵ / cm ³ to about 7.0 × 10 ¹⁵ / cm ³ .

(Procedure shown in FIGS. 4A and 4B)

After a mask made of LTO or the like 20th on the surface of the drift layer 2 is of the n ^- type, an opening is formed in the mask by a photolithographic process 20th in a position where the deep layer 10 of the p-type is to be formed. Then, ion implantation and activation of a p-type foreign atom (foreign ion) (e.g. boron or aluminum) are performed through the mask 20th performed to the bottom layer 10a the deep layer 10 of the p-type. For example, the bottom layer has 10a a thickness of about 0.6 µm to about 1.0 µm and a width of about 0.6 µm to about 1.0 µm and is with boron or aluminum in a concentration of about 1.0 × 10 ¹⁷ / cm ³ to about 1.0 × 10 ¹⁹ / cm ³ doped. Then the mask 20th away.

(Procedure shown in FIGS. 5A and 5B)

The current scattering layer 30th n-type becomes epitaxial on the surfaces of the drift layer 2 of the n ^- type and the deep layer 10 grown up of p-type. For example, the current scattering layer has 30th of the n-type, a thickness of 0.3 µm, for example. In this case it is the current scattering layer 30th n-type with an n-type foreign atom (foreign ion) such as B. phosphorus, doped in a concentration of, for example 2.0 × 10 ¹⁵ / cm ³ to 1.0 × 10 ¹⁷ / cm ³ , so that the concentration of the current scattering layer 30th n-type may be higher than that of the drift layer 2 of the n ^- type, preferably the channel layer 7th of the n-type.

(Procedure shown in FIGS. 6A and 6B)

Having a mask 21st on the surface of the current scattering layer 30th is n-type, an opening is formed in the mask by a photolithographic process 21st in a position where the deep layer 10 of the p-type is to be formed. Then, ion implantation and activation of a p-type foreign atom (foreign ion) (e.g. boron or aluminum) are performed through the mask 21st performed to the top layer 10b the deep layer 10 of the p-type. In this case, the concentration of foreign atoms (foreign ions) becomes p-type and the width of the upper layer 10b substantially the same as the concentration of p-type foreign atoms (foreign ions) and the width of the lower layer 10a made. That way are the bottom layer 10a and the top layer 10b connected to each other and form the deep layer 10 p-type. Then the mask 21st away.

(Procedure shown in FIGS. 7A and 7B)

A p-type foreign atom (foreign ion) layer becomes epitaxial on the surface of the drift layer 2 of the n ^- type grown up around the base area 3 of the p-type. For example, the p-type foreign atom (foreign ion) layer has a thickness of about 2.0 µm and is covered with a p-type foreign atom (foreign ion) such as. B. boron or aluminum, doped in a concentration of about 5.0 × 10 ¹⁶ / cm ³ to about 2.0 × 10 ¹⁹ / cm ³ .

(Procedure shown in FIGS. 8A and 8B)

After a mask (not shown) formed from, for example, LTO on the base area 3 is p-type, an opening is formed by a photolithographic process in the mask at a position where the source region 4th of the n ⁺ type is to be formed. Then, ion implantation of an n-type foreign atom (foreign ion) (e.g., phosphorus) is performed. Next, the mask is removed and another mask (not shown) is formed. Then an opening is formed by a photolithographic process in the other mask in a position where the body layer 5 of the p ⁺ type is to be formed. Then, ion implantation of a p-type foreign atom (foreign ion) (e.g. boron or aluminum) is performed. Then the implanted ions are activated so that the source area 4th of the n ⁺ type and the body layer 5 of the p ⁺ type can be formed. For example, the source area has 4th from the n ⁺ -type a thickness of about 0.3 µm and is with an impurity atom (foreign ion) of the n-type, such as. B. phosphorus, doped in a concentration (surface concentration) of about 1.0 × 10 ²¹ / cm ³ . For example, the body layer has 5 from the p ⁺ -type a thickness of about 0.3 microns and is with a foreign atom (foreign ion) of the p-type such. B. boron or aluminum, doped in a concentration (surface concentration) of about 1.0 × 10 ²¹ / cm ³ . Then the other mask is removed.

(Procedure shown in FIGS. 9A and 9B)

After an etching mask (not shown) on the base area 3 of the p-type, the source region 4th of the n ⁺ type and the body layer 5 is formed from the p ⁺ -type, an opening in the etching mask in a position where the trench 6th should be formed, formed. Then anisotropic etching is performed by using the etching mask to form the trench 6th used. If necessary, isotropic etching and sacrificial oxidation can be carried out following the anisotropic etching. Then the etching mask is removed.

(Procedure illustrated in FIGS. 10A and 10B)

The channel layer 7th n-type becomes epitaxial on the entire surface of the substrate including the trench 6th grown up. For example is the channel layer 7th n-type with an n-type foreign atom (foreign ion) such as B. phosphorus, doped in a concentration of about 1.0 × 10 ¹⁶ / cm ³ . In this case, for example, due to the dependency of the epitaxial growth in the direction of the front side, the thickness of the channel layer becomes 7th n-type larger on the bottom wall of the trench 6th than on the side wall of the trench 6th . Next is having unnecessary parts of the channel layer 7th of the n-type, ie parts that are attached to the base region 3 of the p-type, the source region 4th of the n ⁺ type and the body layer 5 of the p ⁺ type are removed, the gate oxide layer 8th formed by performing a formation process for the gate oxide film. In particular, the gate oxide layer 8th formed by gate oxidation (thermal oxidation), which is achieved by a pyrogenic technique in a wet atmosphere.

Then, a polysilicon layer doped with an n-type impurity (foreign ion) and having the thickness of about 440 nm is formed on the surface of the gate oxide layer 8th formed at a temperature of about 600 ° C. Then an etch back process is performed so that the gate oxide layer 8th and the gate electrode 9 in the ditch 6th can be left.

Methods following the above-described methods are not shown in the figures because the following methods are the same as the usual methods. In particular, after the interlayer insulation layer is formed 12 the interlayer insulation layer 12 patterned to form a contact hole leading to the source region 4th of the n ⁺ type and the body layer 5 of the p ⁺ type, and also patterned to form a contact hole leading to the gate electrode 9 leads to a different cross-section. Next, electrode material is formed to fill the contact holes and then patterned around the source electrode 11 and to form the gate wire. This way, the in 1 MOSFET shown completed.

According to the method described above, make the bottom layer 10a and the top layer 10b the deep layer 10 formed separately from the p-type. With such an approach, the deep layer 10 of the p-type are formed deep, compared with the case that the deep layer 10 of p-type at a time. Furthermore, it is not necessary to increase the energy required to carry out the ion implantation as the lower layer 10a and the top layer 10b the deep layer 10 be formed separately from the p-type. Accordingly, there is no need to manufacture an ion implantation apparatus that can perform ion implantation using an enormous amount of energy.

Since the process continues the deeper formation of the deep layer 10 of the p-type, it is ensured that the bottom of the deep layer 10 p-type deeper than the bottom wall of the trench 6th is arranged. It is therefore not necessary to carry out a control of the trench depth, which is difficult to implement.

The deep layer 10 is made by performing ion implantation from the surface of the current scattering layer 30th educated. In such a case, since the ion implantation is performed at high energy, a defect due to the ion implantation may occur. However, according to the present embodiment, it is not necessary to perform the ion implantation at high energy. Therefore, the defect due to the ion implantation can be avoided.

Incidentally, it is assumed that the longitudinal direction of the trench 6th parallel to the longitudinal direction of the deep layer 10 is arranged in the p-type. In such a case, the device properties are impaired when the separation distance between the trench 6th and the deep layer 10 p-type is not uniform. This is why it becomes important to have one to form the trench 6th used mask with a mask used to form the deep layer 10 p-type is used, is arranged in the same direction. Of course, since the orientation of the masks is not completely the same, it is impossible to completely eliminate the influence of the incomplete orientation on the device properties. In contrast, according to the SiC semiconductor device of the present invention, the longitudinal direction is the trench 6th perpendicular to the longitudinal direction of the deep layer 10 arranged p-type to prevent the incomplete alignment from affecting device properties. Therefore, different properties between the products are avoided, so that the production rates can be improved.

(Second embodiment)

A second embodiment of the present invention will be described. The difference between the first and second embodiments is the relationship between the lower layer 10a and the top layer 10b the deep layer 10 p-type. Since the basic structure is the same between the first and second embodiments, only the difference will be described.

11 FIG. 13 is a diagram illustrating a cross-sectional view of a trench gate MOSFET of a SiC semiconductor device according to the second embodiment. Parts of the second embodiment according to the in 1 and the 2A-2C parts shown are almost the same as those of the first embodiment, and a part of the second embodiment corresponding to that of FIG 2D part shown is different from that of the first embodiment. 11 FIG. 13 is a cross-sectional view of the portion corresponding to that of FIG 2D part shown.

As in 11 shown is the separation distance L2 between adjacent upper layers 10b greater than the separation distance L1 between adjacent lower layers 10a . With such an approach, the current path becomes in the current scattering layer 30th wider so that the ON current can be increased. The SiC semiconductor device having such a structure can be made by modifying the size and the separation distance of those in the mask 21st the opening formed in the first embodiment can be made.

(Third embodiment)

A third embodiment of the present invention will be described. A difference between the first and third embodiments is the relationship between the lower layer 10a and the top layer 10b the deep layer 10 p-type. Since the basic structure is the same in the first and third embodiments, only the difference will be described.

12 Fig. 13 is a diagram showing a cross-sectional view of a trench gate MOSFET of the SiC semiconductor device according to the third embodiment. Parts of the third embodiment according to the in 1 and the 2A-2C parts shown are almost the same as those of the first embodiment, and a part of the third embodiment corresponding to that of FIG 2D part shown is different from that of the first embodiment. 12 FIG. 13 is a cross-sectional view of the portion corresponding to that of FIG 2D part shown.

As in 12 shown is the width W2 the bottom side of the top layer 10b lower than the W1 of the lower layer 10a , and the width W3 the surface side of the upper layer 10b is larger than the width W1 the lower layer 10a . With such an approach, the current path becomes in the current scattering layer 30th becomes wider and the surge current resistance becomes small. The SiC semiconductor device having such a structure can be manufactured by causing the in the mask 21st the opening formed in the first embodiment has a wedge shape. For example, the use of isotropic etching, such as e.g. B. wet etching, in the photolithographic process of forming the opening of the mask 21st to that the opening has a wedge shape.

(Fourth embodiment)

A fourth embodiment of the present invention is described below. The difference between the fourth embodiment and the first to third embodiments is that the MOSFET is an inversion type. Since the basic structure of the fourth embodiment is the same as that of the first to third embodiments, only the difference will be described.

13th Fig. 13 is a diagram showing a cross-sectional perspective view of a trench gate MOSFET of a SiC semiconductor device of the fourth embodiment. True shows 13th a structure formed by modifying the MOSFET of the first embodiment into an inversion type MOSFET, however, the respective MOSFETs of the second and third embodiments can also be modified into an inversion type MOSFET.

As in 13th shown, in the fourth embodiment, the gate oxide film 8th on the surface of the trench 6th formed, and the channel layer 7th n-type of the first embodiment is not formed. Hence the gate oxide layer 8th in contact with the ground area 3 of p-type and the source region 4th of the n ⁺ type on the side wall of the trench 6th .

In a MOSFET having such a structure, when a gate voltage is applied to the gate electrode 9 part of the basic area 3 p-type that is in contact with the gate oxide layer 8th is that on the side wall of the trench 6th is arranged, a channel of the inversion type, so that an electric current between the source electrode 11 and the drain electrode 13th can flow.

As with the first embodiment, the deep layer 10 p-type is formed in the inversion type MOSFET. Therefore, when a high voltage is applied as a drain voltage, the barrier layer largely extends to the drift layer side 2 of the n ^- type at the PN zone transition between the deep layer 10 p-type and the drift layer 2 of the n ^- type. Therefore, it is unlikely that the high voltage due to the drain voltage is applied to the gate oxide layer 8th is created. Thus, the electric field concentration in the gate oxide layer 8th be reduced, especially on the bottom wall of the trench 6th so that punching through of the gate oxide layer 8th can be prevented.

Because the bottom layer 10a and the top layer 10b the deep layer 10 formed separately, the same advantage as the first embodiment can be obtained.

The method of manufacturing the SiC semiconductor device having such an inversion type MOSFET is basically the same as the method of manufacturing the SiC semiconductor device of the first embodiment. A difference between the methods is that the method used to form the channel layer 7th n-type is omitted and the gate oxide layer 8th right on the ditch 6th is formed.

(Modifications)

The above-described embodiments can be modified in various ways. For example, in the above-described embodiments, the MOSFET is of the n-channel type, an n-conductivity type is defined as a first conductivity type, and a p-conductivity type is defined as a second conductivity type. Alternatively, the present invention can be applied to a p-channel MOSFET by reversing the conductivity type of each element. While a trench gate MOSFET is taken as an example of the embodiments, the present invention can also be applied to the trench gate IGBT by determining the conductivity type of the substrate 1 of the first and second embodiments changes from n-conductivity type to p-conductivity type.

In the embodiments, the base area becomes 3 p-type and the source region 4th of the n ⁺ type before formation of the trench 6th educated. Alternatively, the basic area 3 p-type and the source region 4th of the n ⁺ type by ion implantation after formation of the trench 6th are formed. In the event that the source area 4th of the n ⁺ -type is formed by ion implantation, it is irrelevant that the source region 4th of the n ⁺ type in contact with the gate oxide layer 8th is. Furthermore, in the event that the basic area 3 p-type is formed by ion implantation, the base region 3 of p-type at a distance from the side wall of the trench 6th be. Therefore, part of the drift layer 2 of the n ^- type, which is between the side wall of the trench 6th and the basic area 3 p-type is arranged as a channel layer 7th act of n-type. In this case it does not matter that the basic area 3 p-type and the source region 4th of the n ⁺ type before or after the formation of the trench 6th are formed.

In the embodiments, the source region 4th of the n ⁺ type and the body layer 5 of the p ⁺ -type formed by ion implantation. Alternatively, the source area 4th n ⁺ -type and / or the p ⁺ -type body layer are formed by epitaxial growth.

In the embodiments, the basic range is 3 p-type electrically with the source electrode 11 over the body layer 5 connected by the p ⁺ type. Alternatively, the body layer 5 of the p ⁺ type as a simple contact part for electrical connection of the base area 3 p-type and the source electrode 11 be educated. The gate oxide layer 8th formed by thermal oxidation is used as a gate insulating layer. Alternatively, the gate insulation layer may contain a nitride layer or an oxide layer which is formed by a method other than thermal oxidation. Furthermore, the drain electrode 13th be formed after the source electrode 11 is formed.

Claims (6)

A method of manufacturing a silicon carbide semiconductor device having an accumulation mode MOSFET, in which an accumulation mode channel formed by controlling an application voltage to a gate electrode (9) is controlled so that an electric current is passed between a source electrode ( 11) and a drain electrode (13) flowing through a source region (4) and a drift layer (2), comprising: making a substrate (1) from silicon carbide having a first or second conductivity type; Formation of the drift layer (2) on the substrate (1), the drift layer (2) being made of silicon carbide and having a first conductivity type, the concentration of impurity of the drift layer (2) being lower than the concentration of impurity of the substrate (1) ); Formation of a current scattering layer (30) on the drift layer (2), the current scattering layer (30) being made of silicon carbide and having the first conductivity type, the concentration of foreign atoms of the current scattering layer (30) being higher than the concentration of foreign atoms of the drift layer (2) ); Forming a base region (3) on the current scattering layer (30), the base region (3) being made of silicon carbide and having the second conductivity type; Formation of the source region (4) on the base region (3), the source region (4) being made of silicon carbide and having the first conductivity type, the concentration of impurities of the source region (4) being higher than the concentration of impurities of the drift layer (2 ); Formation of a trench (6) which extends deeper than the source region (4) and the base region (3) in order to reach the current scattering layer (30) or the drift layer (2), the source region (4) and the base region (3 ) are arranged on each side of the trench (6); Forming the channel layer (7) on a side wall of the trench (6), the channel layer (7) being made of silicon carbide and having the first conductivity type; Forming a gate insulation layer (8) on a surface of the channel layer (7), the gate insulation layer (8) being arranged at a predetermined distance from the base region (3); Forming the gate electrode (9) on the gate insulation layer (8) within the trench (6); Forming the source electrode (11) which is electrically connected to the source region (4) and the base region (3); Forming the drain electrode (13) on the back of the substrate (1); and formation of a deep layer (10) which is arranged below the base region (3) and reaches the drift layer (2) by penetrating the current scattering layer (30), the deep layer (10) extending deeper than the trench (6) and extends in a direction perpendicular to the side wall of the trench (6), the deep layer (10) having the second conductivity type, the formation of the deep layer (10) the formation of a lower layer (10a) of the deep layer (10) and an upper one Layer (10b) of the deep layer (10), the lower layer (10a) extending in one direction, the upper layer (10b) being arranged in a position corresponding to the lower layer (10a) and with the lower layer (10a) is connected, the formation of the lower layer (10a) comprises the application of a first mask (20) on a surface of the drift layer (2) and performing ion implantation using the first mask (20), and the formation of the upper layer (1 0b) comprises the application of a second mask (21) on a surface of the current scattering layer (30) and the implementation of ion implantation using the second mask (21) (corresponding to the method in FIG 1 semiconductor device shown). Procedure according to Claim 1 wherein the formation of the upper layer (10b) further comprises forming a greater separation distance (L2) between adjacent upper layers (10b) than the separation distance (L1) between adjacent lower layers (10a). Procedure according to Claim 1 or 2 wherein the formation of the upper layer (10b) further comprises the formation of a smaller width (W2) of a bottom part of the upper layer (10b) than the width (W1) of the lower layer (10a) and the formation of a greater width (W3) of a surface part of the upper layer (10b) as the width (W1) of the lower layer (10a). A method of manufacturing a silicon carbide semiconductor device having an inversion type MOSFET, wherein an inversion type channel formed in a surface part of a base region (3) disposed on a side wall of a trench (6) by controlling an application voltage to a gate electrode ( 9) is formed, is controlled so that an electric current flows between a source electrode (11) and a drain electrode (13) through a source region (4) and a drift layer (2), comprising: producing a substrate (1) from Silicon carbide is made and has a first or second conductivity type; Formation of a drift layer (2) on the substrate (1), the drift layer (2) being made of silicon carbide and having the first conductivity type, the concentration of foreign atoms of the drift layer (2) being smaller than the concentration of foreign atoms of the substrate (1) ); Formation of a current scattering layer (30) on the drift layer (2), the current scattering layer (30) being made of silicon carbide and having the first conductivity type, the concentration of foreign atoms of the current scattering layer (30) being higher than the concentration of foreign atoms of the drift layer (2) ); Forming a base region (3) on the current scattering layer (30), the base region (3) being made of silicon carbide and having the second conductivity type; Formation of the source region (4) on the base region (3), the source region (4) being made of silicon carbide and having the first conductivity type, the concentration of impurities in the source region (4) being greater than the concentration of impurities in the drift layer (2) ; Formation of the trench (6), which extends deeper than the source region (4) and the base region (3) in order to reach the current scattering layer (30) or the drift layer (2), the source region (4) and the base region (3 ) are arranged on each side of the trench (6); Forming a gate insulation layer (8) on the surface of the trench (6); Forming the gate electrode (9) on the gate insulation layer (8) within the trench (6); Forming the source electrode (11) which is electrically connected to the source region (4) and the base region (3); Forming the drain electrode (13) on a back side of the substrate (1); and formation of a deep layer (10) which is arranged below the base region (3) and reaches the drift layer (2) by penetrating the current scattering layer (30), the deep layer (10) extending deeper than the trench (6) and extends in a direction perpendicular to the side wall of the trench (6), the deep layer (10) having the second conductivity type, the formation of the deep layer (10) the formation of a lower layer (10a) of the deep layer (10) and an upper one Layer (10b) of the deep layer (10), the lower layer (10a) extending in one direction, the upper layer (10b) being arranged in a position corresponding to the lower layer (10a) and with the lower layer (10a) connected is, forming the lower layer (10a) comprises attaching a first mask (20) to a surface of the drift layer (2) and performing ion implantation using the first mask (20), and forming the upper layer (10b) comprises attaching a second mask (21) on a surface of the current scattering layer (30) and performing ion implantation using the second mask (21) (corresponding to the method shown in FIG 13th semiconductor device shown). Procedure according to Claim 4 wherein the formation of the upper layer (10b) further comprises establishing a greater separation distance between adjacent upper layers (10b) than the separation distance between adjacent lower layers (10a). Procedure according to Claim 4 or 5 wherein the formation of the upper layer (10b) furthermore the production of a smaller width (W2) of a bottom part of the upper layer (10b) than the width (W1) of the lower layer (10a) and the production of a larger width (W3) of a surface part of the upper layer (10b) as the width (W1) of the lower layer (10a).

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