CS219745B1 - Wiring for program control of analog-to-digital converter and storage of digitized signals in memory - Google Patents

Abstract

Connection for program control of an analog-to-digital converter and storage of digitized signals in memory. The invention relates to pulse technology and solves the problem of accelerating the recording and storage of digitized analog signals in digital memory. Each of the two units is identically equipped with a clock pulse counter, a program register and a comparator block connected to their outputs. After the states match, the output from the comparator block of the first unit for setting the start of sampling unlocks the gate that triggers the second unit for setting the sampling interval. Here too, after the states match, the output pulse of the comparator block triggers the (A/D) converter and generates the address of the memory counter. The essence is that the units (NZV and NIV] are connected by a gate (H) and the output of the comparator block (Kj of the second unit (NIV) is connected to the input of the address counter (A) and the trigger input (A/D) of the converter.

Description

The invention relates to a circuit for programmatically controlling an analog-to-digital converter and storing the digitized signals in a memory connected to its output, provided with an address counter.

The known circuitry for creating an address for storing data from an analog-to-digital converter calculates the necessary data from the values in the programming registers using a binary adder. Because of their complexity, this circuitry requires a large number of integrated circuits which, due to the overall circuitry concept, cannot fully utilize their limit speeds.

The above drawbacks eliminate the circuit according to the invention, which consists of a signal sampling start setting unit and a signal sampling interval setting unit, each of which are equally equipped with a programming register to which input data is input, a counter connected to a clock pulse source and to their outputs connected by a logic comparator block, wherein the clock pulse source is connected to a counter of the gate sampling rate setting unit, the second input of which is output of the logical comparator block of the start sampling unit, The sampling interval adjuster unit is connected to the memory addressing counter input and the analog-to-digital converter trigger input.

. The advantage of the circuitry according to the invention is that the analog start and sample interval setting units operate with counters whose state in the logical comparator block is compared with the data in the programming registers, thus achieving a minimum time for obtaining the memory address and controlling the analogue. -digital converter. Due to the identical equipment of both units, wiring is simple.

An example of a wiring according to the invention is further described with the aid of the drawing in which two units are shown, namely the unit for setting the start of the NZV sampling rate and the unit for setting the sampling interval NIV. Both units are equipped identically and therefore only the first reference numbers are given, of which C stands for n-decade counter or preset counter, R programming register and K block of logic comparators. The input registers are input to the programming registers to set the start or the sampling interval respectively. The decade counter G or the preset counter of the NZV sampling start setting unit is directly connected to the fhod time pulse source, whereas the NIV sampling interval counter unit is connected to it by means of a gate H, the second input of which is the logical comparator block output K to set the start of NZV sampling.

The logic comparator output K of the NIV sampling interval setting unit is connected to the A / D converter trigger input and the address memory counter A of the P memory. The counter state of the NZV sampling start unit with the number of decades given the desired accuracy and set time associated with the clock pulse source In the logical comparator block K, fhod is compared with the input data in the programming register R with the capacity given by the counter capacity Nr.

After the counter state C is in agreement with the state of the programming register R, the output pulse from the logic comparator block K unlocks the gate H, enabling the control signals to be transferred from the fhod clock source to the counter input N of the NIV sampling interval unit. data to set the sampling interval. After matching, the output pulse from the logic comparator block K of the NIV starts the A / D converter and the generated address in the address counter A of the memory P.

In this comparative way and a direct way to generate the memory address, simplicity of connection and short write time are achieved.

Claims (1)

pThe subject Wiring for programmable control of an A / D converter and storage of digitized signals in a memory connected to its output, equipped with an address counter, characterized in that it consists of a signal sampling start setting unit (NZV) and a signal sampling interval setting unit (NIV); each of which is equally equipped with a programming register (R) for input data input, a counter (C) connected to a clock source (fhod) and to their outputs connected by a logic comparator block (K), the clock source (fhod) being connected to counter (C) of the sample interval setting unit (NIV) of the gate (H) to which the other input is connected, output from the logic comparator block (K) of the sample start unit (NZV), while output of the logical comparator block the sampling interval setting (NIV) is connected to the addressing input counters (Aj of the memory (Pj and to the trigger input of the A / D converter).