CO2019001630A2 - Corrección de error de enlace en el sistema de memoria - Google Patents
Corrección de error de enlace en el sistema de memoriaInfo
- Publication number
- CO2019001630A2 CO2019001630A2 CONC2019/0001630A CO2019001630A CO2019001630A2 CO 2019001630 A2 CO2019001630 A2 CO 2019001630A2 CO 2019001630 A CO2019001630 A CO 2019001630A CO 2019001630 A2 CO2019001630 A2 CO 2019001630A2
- Authority
- CO
- Colombia
- Prior art keywords
- increasing
- correction
- memory
- proposed
- link error
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/31—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining coding for error detection or correction and efficient use of the spectrum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Human Computer Interaction (AREA)
- Computer Security & Cryptography (AREA)
- Probability & Statistics with Applications (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
- Memory System (AREA)
Abstract
RESUMEN Las técnicas convencionales de corrección de errores de enlace en los subsistemas de memoria incluyen ampliar el ancho de I/O o aumentar la longitud de ráfaga. Sin embargo, ambas técnicas tienen inconvenientes. En uno o más aspectos, se propone incorporar la corrección de errores de enlace tanto en el host como en los dispositivos de memoria para abordar los inconvenientes asociados con las técnicas convencionales. El subsistema de memoria propuesto es ventajoso porque se puede mantener la arquitectura de interfaz de los sistemas de memoria convencionales. Además, la capacidad de corrección de errores de enlace se proporciona con el subsistema de memoria propuesto sin aumentar el ancho de I/O y sin aumentar la longitud de ráfaga.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662380104P | 2016-08-26 | 2016-08-26 | |
US15/643,455 US10331517B2 (en) | 2016-08-26 | 2017-07-06 | Link error correction in memory system |
PCT/US2017/041129 WO2018038813A1 (en) | 2016-08-26 | 2017-07-07 | Link error correction in memory system |
Publications (1)
Publication Number | Publication Date |
---|---|
CO2019001630A2 true CO2019001630A2 (es) | 2019-05-10 |
Family
ID=61242685
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CONC2019/0001630A CO2019001630A2 (es) | 2016-08-26 | 2019-02-22 | Corrección de error de enlace en el sistema de memoria |
Country Status (20)
Country | Link |
---|---|
US (1) | US10331517B2 (es) |
EP (1) | EP3479241B1 (es) |
JP (1) | JP6630869B2 (es) |
KR (1) | KR102045712B1 (es) |
CN (1) | CN109643257B (es) |
AU (2) | AU2017315303B2 (es) |
BR (1) | BR112019003473A2 (es) |
CA (1) | CA3032278C (es) |
CO (1) | CO2019001630A2 (es) |
ES (1) | ES2829331T3 (es) |
IL (1) | IL264303B (es) |
MX (1) | MX2019002194A (es) |
MY (1) | MY201067A (es) |
PH (1) | PH12019500160A1 (es) |
RU (1) | RU2710977C1 (es) |
SA (1) | SA519401035B1 (es) |
SG (1) | SG11201900375YA (es) |
TW (1) | TWI684102B (es) |
WO (1) | WO2018038813A1 (es) |
ZA (1) | ZA201901194B (es) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107039086A (zh) * | 2017-05-17 | 2017-08-11 | 西安紫光国芯半导体有限公司 | 具有兼容不同数据长度的纠错功能的存储器和纠错方法 |
US10387242B2 (en) | 2017-08-21 | 2019-08-20 | Qualcomm Incorporated | Dynamic link error protection in memory systems |
US10725912B2 (en) | 2018-12-19 | 2020-07-28 | Micron Technology, Inc. | Power loss protection in memory sub-systems |
US11537464B2 (en) * | 2019-06-14 | 2022-12-27 | Micron Technology, Inc. | Host-based error correction |
US11372717B2 (en) * | 2019-08-30 | 2022-06-28 | Qualcomm Incorporated | Memory with system ECC |
CN110750406B (zh) * | 2019-10-29 | 2023-10-31 | 湖南国科微电子股份有限公司 | 一种检测方法、装置和soc芯片 |
US11493949B2 (en) * | 2020-03-27 | 2022-11-08 | Qualcomm Incorporated | Clocking scheme to receive data |
US11728003B2 (en) * | 2020-05-12 | 2023-08-15 | Qualcomm Incorporated | System and memory with configurable error-correction code (ECC) data protection and related methods |
US11157359B2 (en) * | 2020-09-24 | 2021-10-26 | Intel Corporation | Techniques to implement a hybrid error correction code scheme |
KR20230021409A (ko) | 2021-08-05 | 2023-02-14 | 에스케이하이닉스 주식회사 | 트레이닝동작을 수행하기 위한 반도체시스템 |
US11687273B2 (en) * | 2021-09-29 | 2023-06-27 | Micron Technology, Inc. | Memory controller for managing data and error information |
CN114006819A (zh) * | 2021-11-03 | 2022-02-01 | 北京天融信网络安全技术有限公司 | 一种检测策略生成及装置、数据传输方法及装置 |
US20230170037A1 (en) * | 2021-11-30 | 2023-06-01 | Qualcomm Incorporated | Hybrid memory system with increased bandwidth |
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DE69624059T2 (de) * | 1995-04-03 | 2003-08-14 | Matsushita Electric Ind Co Ltd | Datenubertragungsvorrichtung, datenaufzeichnungs- und wiedergabegerat sowie aufzeichnungsmedium beide mit datenstruktur fur fehlerkorrekturkode |
US7032056B2 (en) * | 2003-05-08 | 2006-04-18 | International Business Machines Corporation | Encoding of message onto strobe signals |
KR100978268B1 (ko) * | 2004-07-15 | 2010-08-26 | 엘에스산전 주식회사 | 분산 제어 시스템의 고속 이중화 데이터 복사 보드 |
KR100755371B1 (ko) | 2005-05-03 | 2007-09-04 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 데이터 스트로우브 신호발생방법 |
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US8255783B2 (en) | 2008-04-23 | 2012-08-28 | International Business Machines Corporation | Apparatus, system and method for providing error protection for data-masking bits |
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US8707133B2 (en) * | 2011-12-05 | 2014-04-22 | Lsi Corporation | Method and apparatus to reduce a quantity of error detection/correction bits in memory coupled to a data-protected processor port |
CN102546755A (zh) * | 2011-12-12 | 2012-07-04 | 华中科技大学 | 云存储系统的数据存储方法 |
US8990670B2 (en) * | 2012-09-28 | 2015-03-24 | Intel Corporation | Endurance aware error-correcting code (ECC) protection for non-volatile memories |
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CN105468292B (zh) * | 2014-09-05 | 2019-04-23 | 群联电子股份有限公司 | 数据存取方法、存储器储存装置及存储器控制电路单元 |
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KR102438552B1 (ko) * | 2015-02-04 | 2022-09-01 | 에스케이하이닉스 주식회사 | 메모리 시스템 및 그 동작방법 |
US9965352B2 (en) * | 2015-11-20 | 2018-05-08 | Qualcomm Incorporated | Separate link and array error correction in a memory system |
US20180059976A1 (en) * | 2016-08-26 | 2018-03-01 | Sandisk Technologies Llc | Storage System with Integrated Components and Method for Use Therewith |
-
2017
- 2017-07-06 US US15/643,455 patent/US10331517B2/en active Active
- 2017-07-07 CN CN201780051324.XA patent/CN109643257B/zh active Active
- 2017-07-07 KR KR1020197005234A patent/KR102045712B1/ko active IP Right Grant
- 2017-07-07 JP JP2019510446A patent/JP6630869B2/ja active Active
- 2017-07-07 AU AU2017315303A patent/AU2017315303B2/en active Active
- 2017-07-07 MX MX2019002194A patent/MX2019002194A/es unknown
- 2017-07-07 MY MYPI2019000091A patent/MY201067A/en unknown
- 2017-07-07 CA CA3032278A patent/CA3032278C/en active Active
- 2017-07-07 WO PCT/US2017/041129 patent/WO2018038813A1/en active Search and Examination
- 2017-07-07 ES ES17740597T patent/ES2829331T3/es active Active
- 2017-07-07 SG SG11201900375YA patent/SG11201900375YA/en unknown
- 2017-07-07 BR BR112019003473-0A patent/BR112019003473A2/pt unknown
- 2017-07-07 RU RU2019104878A patent/RU2710977C1/ru active
- 2017-07-07 EP EP17740597.4A patent/EP3479241B1/en active Active
- 2017-07-28 TW TW106125466A patent/TWI684102B/zh active
-
2019
- 2019-01-17 IL IL264303A patent/IL264303B/en active IP Right Grant
- 2019-01-22 PH PH12019500160A patent/PH12019500160A1/en unknown
- 2019-02-05 SA SA519401035A patent/SA519401035B1/ar unknown
- 2019-02-22 CO CONC2019/0001630A patent/CO2019001630A2/es unknown
- 2019-02-25 ZA ZA2019/01194A patent/ZA201901194B/en unknown
- 2019-08-30 AU AU2019222960A patent/AU2019222960B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP3479241B1 (en) | 2020-08-19 |
ZA201901194B (en) | 2020-12-23 |
ES2829331T3 (es) | 2021-05-31 |
NZ750205A (en) | 2020-10-30 |
PH12019500160A1 (en) | 2019-11-11 |
AU2019222960B2 (en) | 2020-10-15 |
KR102045712B1 (ko) | 2019-11-15 |
SA519401035B1 (ar) | 2021-11-06 |
AU2019222960A1 (en) | 2019-09-26 |
CN109643257A (zh) | 2019-04-16 |
RU2710977C1 (ru) | 2020-01-14 |
MX2019002194A (es) | 2019-06-24 |
JP2019525356A (ja) | 2019-09-05 |
TW201810056A (zh) | 2018-03-16 |
EP3479241A1 (en) | 2019-05-08 |
IL264303A (en) | 2019-02-28 |
WO2018038813A1 (en) | 2018-03-01 |
IL264303B (en) | 2019-08-29 |
CA3032278C (en) | 2021-01-12 |
TWI684102B (zh) | 2020-02-01 |
AU2017315303A1 (en) | 2019-02-07 |
US10331517B2 (en) | 2019-06-25 |
AU2017315303B2 (en) | 2020-06-18 |
SG11201900375YA (en) | 2019-03-28 |
KR20190043540A (ko) | 2019-04-26 |
BR112019003473A2 (pt) | 2019-05-21 |
MY201067A (en) | 2024-02-01 |
JP6630869B2 (ja) | 2020-01-15 |
CA3032278A1 (en) | 2018-03-01 |
US20180060171A1 (en) | 2018-03-01 |
CN109643257B (zh) | 2020-07-03 |
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