CN2746498Y - Multilayer interdigitated metal capacitor structure - Google Patents
Multilayer interdigitated metal capacitor structure Download PDFInfo
- Publication number
- CN2746498Y CN2746498Y CN 200420084862 CN200420084862U CN2746498Y CN 2746498 Y CN2746498 Y CN 2746498Y CN 200420084862 CN200420084862 CN 200420084862 CN 200420084862 U CN200420084862 U CN 200420084862U CN 2746498 Y CN2746498 Y CN 2746498Y
- Authority
- CN
- China
- Prior art keywords
- type electrode
- electrode
- level
- odd
- multilayer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
The utility model provides a multilayer interdigitated metal capacitor structure, each layer consists of two metal electrodes with the comb-like structures of the different polarities, the two metal electrodes are interdigitated with each other, the comb-like structures of the metal electrodes of any two adjacent layers are mutually perpendicular, and via on the edges of the comb-like structures are connected with the metal electrode of the same polar. Wherein, any two metal electrodes are isolated by a dielectric material.
Description
Technical field
The utility model relates to a kind of multilayer fork and closes (Interdigitated) metal capacitor structure, particularly the multilayer fork metal capacitance structure that is perpendicular to one another relevant for a kind of electrode of adjacent layer.
Background technology
When continuing to promote, make to be widely used in passive component on the integrated circuit that capacitor etc. for example is also thereupon constantly towards the trend development that promotes integration along with the integration of integrated circuit.In response to this trend, developed at present a kind of multilayer fork that forms by several layers of metal stack and close capacitance structure.Because this kind multilayer fork closes capacitance structure and can be formed by multiple layer metal electrode storehouse, therefore has higher integration, makes unit are have higher capacitance density.In addition, on making, existing mask and fabrication steps can be used, therefore the processing procedure cost can be reduced because this kind multilayer fork closes capacitance structure.
Please refer to Fig. 1, Fig. 1 is the schematic top plan view that illustrates prior art multilayer fork metal capacitance structure.Because, the all parallel to each other and last push-down stack of pectinate texture of each layer of present multilayer fork metal capacitance structure, therefore the fork of the multilayer in Fig. 1 metal capacitance structure top view can be represented the top view of the fork metal capacitance structure of the superiors, also can represent the top view of each layer fork metal capacitance structure.This layer fork metal capacitance structure is made of electrode 104 and electrode 112, and wherein electrode 112 is anodal, and electrode 104 is a negative pole.Electrode 104 comprises shank 100 and a plurality of pars pectinatas 102, and wherein these pars pectinatas 102 are parallel to each other and separated by a distance and be engaged on one side of shank 100.Similarly, electrode 112 is made of shank 108 and a plurality of pars pectinata 110, and wherein these pars pectinatas 110 are parallel to each other and separated by a distance each other and be engaged on one side of shank 108.
In addition, the below of the shank 100 of electrode 104 has more in the dielectric materials layer (not illustrating) of a plurality of interlayer holes (Via) 106 between two-layer capacitance structure, in order to electrically connect electrode 104 and the same polarity electrode (see also Fig. 2, only illustrate pars pectinata 118 wherein) under it.And the below of the shank 108 of electrode 112 also has the dielectric materials layer of a plurality of interlayer holes 114 between two-layer capacitance structure, in order to electrically connect electrode 112 and the same polarity electrode (see also Fig. 2, only illustrate pars pectinata 116 wherein) under it.The pars pectinata 102 of electrode 104 is pitched mutually with the pars pectinata of electrode 112 110 and is closed, and pars pectinata 102 and pars pectinata 110 are staggered.In addition, more be filled with dielectric material (not illustrating) between electrode 104 and the electrode 112, electrode 104, electrode 112 and the dielectric material between electrode 104 and electrode 112 then constitute one deck fork and close capacitance structure.
Then, please refer to Fig. 2, Fig. 2 illustrates the generalized section that is obtained along the I-I hatching of the multilayer of Fig. 1 fork metal capacitance structure, wherein for the storehouse mode of clear expression electrode, does not show the dielectric materials layer between the two-layer electrode.Because the pars pectinata of the electrode of same polarity is parallel to each other and last push-down stack, therefore the pars pectinata 102 of the pars pectinata 110 of the electrode 112 of the superiors and electrode 104 respectively storehouses at it down on the pars pectinata 116 and pars pectinata 118 of the electrode of one deck, pars pectinata 116 and pars pectinata 118 then respectively storehouse at it down on the pars pectinata 120 and pars pectinata 122 of the electrode of one deck.
Because each layer fork closes the pectinate texture electrode of electric capacity and all needs storehouse parallel to each other, so on making, produce skew because of fabrication errors causes electrode position quite easily, therefore processing procedure window (Process Window) can dwindle, and the processing procedure degree of difficulty also can significantly improve.And the skew of electrode position not only can cause the capacitance between layer and the layer to change, and more can influence the total capacitance value of whole capacitor structure.
Summary of the invention
In above-mentioned prior art multilayer fork metal capacitance structure, the pectinate texture of the metal electrode in wantonly two adjacent layers must be parallel and superimposed, thus, alignment error takes place in manufacturing process very easily, and cause the capacitance between layer and the layer to change, and then influence total capacitance value.
Therefore, one of main purpose of the present utility model is exactly that a kind of multilayer fork metal capacitance structure is being provided, and the pectinate texture of the electrode of its wantonly two adjacent layers is orthogonal, and can as existent technique each layer all accurately be aimed at.So not only processing procedure is simply easy to implement, and has wider processing procedure window.
A purpose more of the present utility model is exactly at the mutually perpendicular multilayer fork of the electrode pectinate texture that a kind of two adjacent layers up and down are provided metal capacitance structure, can effectively improve the alignment error problem.Therefore, can reduce the capacitance variation that is caused because of levels electrode alignment error.
According to above-described purpose, the utility model more provides a kind of multilayer fork metal capacitance structure, comprises a plurality of odd-levels at least; A plurality of even levels lay respectively between per two odd-levels, wherein each odd-level and each even level all comprise one first type electrode and one second type electrode at least, and this first type electrode and the second type electrode all comprise a first and a plurality of second portions that are parallel to each other at least, these second portions predeterminable range of being separated by is bonded on respectively on one side of first, and the second portion fork parallel to each other of these second portions of the first type electrode and the second type electrode closes, and the second portion of the first type electrode of each even level and the second type electrode is perpendicular to the first type electrode of each odd-level and the second portion of the second type electrode; A plurality of interlayer holes lay respectively between the adjacent odd-level and even level, in order to the first type electrode that electrically connects each odd-level respectively and the first type electrode of each even level, and the second type electrode of the second type electrode of each odd-level and each even level; And a plurality of dielectric layers lay respectively between the first type electrode and the second type electrode of each odd-level, between the first type electrode of each even level and the second type electrode and between the adjacent odd-level and even level.
Because, the first type electrode of odd-level is vertical with the second portion that is parallel to each other of the second type electrode with the first type electrode of even level with the second portion that is parallel to each other of the second type electrode, therefore, not only have bigger processing procedure window, more can obtain than stable capacitance value.
Description of drawings
Fig. 1 is the schematic top plan view that illustrates prior art multilayer fork metal capacitance structure;
Fig. 2 illustrates the generalized section that is obtained along the I-I hatching of the multilayer of Fig. 1 fork metal capacitance structure;
Fig. 3 is the perspective view that illustrates the multilayer fork metal capacitance structure of a preferred embodiment of the present utility model, wherein only illustrate the wherein two-layer capacitance structure that this multilayer is pitched the metal capacitance structure, and do not illustrate the dielectric layer between two-layer capacitance structure in order to clearly demonstrate;
Fig. 4 is the schematic top plan view that illustrates the multilayer fork metal capacitance structure odd-level of a preferred embodiment of the present utility model;
Fig. 5 is the schematic top plan view that illustrates the multilayer fork metal capacitance structure even level of a preferred embodiment of the present utility model;
Fig. 6 illustrates the generalized section that is obtained along the II-II hatching of the multilayer of Fig. 3 fork metal capacitance structure.
Embodiment
The utility model discloses a kind of multilayer fork metal capacitance structure, and the pectinate texture of the metal capacitance of its two adjacent layer is orthogonal, therefore can obtain bigger processing procedure window, and can reduce the variation of integral capacitor value.In order to make narration of the present utility model more detailed and complete, can be with reference to the icon of following description and cooperation Fig. 3 to Fig. 6.
Please refer to Fig. 3, Fig. 3 is the perspective view that illustrates the multilayer fork metal capacitance structure of a preferred embodiment of the present utility model, wherein only illustrate the wherein two-layer capacitance structure that this multilayer is pitched the metal capacitance structure, and do not illustrate the dielectric layer between two-layer capacitance structure in order to clearly demonstrate.And please in the lump with reference to Fig. 4 and Fig. 5, wherein Fig. 4 is the schematic top plan view that illustrates the multilayer fork metal capacitance structure odd-level of a preferred embodiment of the present utility model, and Fig. 5 is the schematic top plan view that illustrates the multilayer fork metal capacitance structure even level of a preferred embodiment of the present utility model.In odd-level 216, comprise electrode 204 and electrode 212 at least.Wherein, electrode 204 comprises shank 200 and a plurality of pars pectinata parallel to each other 202 at least.In addition, shank 200 is the L type, and is to be formed by engaging with the vertical and parallel two parts of pars pectinata 202 respectively.And these pars pectinatas 202 are engaged in the interval of a predeterminable range on one side of a wherein part of shank 200.In the same manner, electrode 212 comprises shank 208 and a plurality of pars pectinata parallel to each other 210 at least.Wherein, shank 208 is the L type, and is to be formed by engaging with the vertical and parallel two parts of pars pectinata 210 respectively.And these pars pectinatas 210 also are on one side of the wherein part that is engaged in shank 208 of the interval with a predeterminable range.
In addition, the pars pectinata 202 of electrode 204 is pitched mutually with the pars pectinata of electrode 212 210 and is closed, and arranges and make pars pectinata 202 and pars pectinata 210 be staggered, as shown in Figure 4.And, therefore in Fig. 3 and Fig. 4, do not show the dielectric material of being filled between electrode 204 and the electrode 212 for of the structure and the arrangement of clear expression electrode 204 with electrode 212.Wherein, electrode 204, electrode 212 and the dielectric material between electrode 204 and electrode 212 fork that constitutes this odd-level 216 closes capacitance structure.
Similarly, in even level 218, comprise electrode 224 and electrode 230 at least.Wherein, electrode 224 comprises shank 220 and a plurality of pars pectinata parallel to each other 222 that is the L type at least.Wherein, shank 220 is to be formed by engaging with the vertical and parallel two parts of pars pectinata 222 respectively.And these parallel pars pectinatas 222 are bonded on respectively on wherein a part of one side of shank 220 with the interval of a predeterminable range.Electrode 230 comprises shank 226 and a plurality of pars pectinata parallel to each other 228 of L type at least.Wherein, the shank 220 of L type is engaged by two parts to form with the shank 226 of L type.And on one side of the wherein part of these parallel pars pectinatas 228 to be interval with a predeterminable range equally be engaged in respectively shank 226.
In addition, in even level 218, the pars pectinata 222 of electrode 224 is pitched each other with the pars pectinata 228 of electrode 230 and is closed, and makes pars pectinata 222 and pars pectinata 228 interlaced arrangements, as shown in Figure 5.In Fig. 3 and Fig. 5, do not show the dielectric material of being filled between electrode 224 and the electrode 230, with of the structure and the arrangement of clearer expression electrode 224 with electrode 230.Wherein, the fork of the formation of the dielectric material between electrode 224, electrode 230 and electrode 224 and the electrode 230 even level 218 closes capacitance structure.
In odd-level 216 and even level 218, electrode 204 is identical with the polarity of electrode 224, and electrode 212 is identical with the polarity of electrode 230, and the polarity of electrode 204 and electrode 224 is different with the polarity of electrode 212 and electrode 230.That is when the polarity of electrode 204 and electrode 224 was positive pole, electrode 212 was a negative pole with the polarity of electrode 230; And when the polarity of electrode 204 and electrode 224 was negative pole, electrode 212 then was anodal with the polarity of electrode 230.
The storehouse mode of odd-level 216 and even level 218 is to make the pars pectinata 210 of pars pectinata 202 and electrode 212 of electrode 204 of odd-level 216 perpendicular to the pars pectinata 222 of the electrode 224 of even level 218 and the pars pectinata 228 of electrode 230, as shown in Figure 3.Wherein, odd-level 216 and even level 218 utilizes the interlayer hole 206 and 214 of the interlayer holes that are arranged in odd-level 216 and the dielectric materials layer of 218 of even levels to carry out the electric connection of the same polarity electrode of odd-level 216 and even level 218.Interlayer hole 206 can engage in the electrode 204 of odd-level 216 in the electrode 224 with vertical shank 200 of pars pectinata 202 and even level 218 shank 220 parallel with pars pectinata 222; And interlayer hole 214 can engage in the electrode 212 of odd-level 216 in the electrode 230 with vertical shank 208 of pars pectinata 210 and even level 218 shank 226 parallel with pars pectinata 228, as shown in Figure 3.Yet interlayer hole 206 also can engage in the electrode 204 of odd-level 216 in the electrode 224 of shank 200 parallel with pars pectinata 202 and even level 218 shank 220 vertical with pars pectinata 222; And interlayer hole 214 can engage in the electrode 212 of odd-level 216 in the electrode 230 of shank 208 parallel with pars pectinata 210 and even level 218 shank 226 vertical with pars pectinata 228, and the utility model is not limited to this.
That is to say that when one of interlayer hole 206 terminated in the electrode 204 of odd-level 216 shank 200 vertical with pars pectinata 202, the other end of interlayer hole 206 then was connected in the electrode 224 of even level 218 shank 220 parallel with pars pectinata 222; And when one of interlayer hole 206 terminated in the electrode 204 of odd-level 216 shank 200 parallel with pars pectinata 202, the other end of interlayer hole 206 then was connected in the electrode 224 of even level 218 shank 220 vertical with pars pectinata 222.Similarly, when one of interlayer hole 214 terminated in the electrode 212 of odd-level 216 shank 208 vertical with pars pectinata 210, the other end of interlayer hole 214 then was connected in the electrode 230 of even level 218 shank 226 parallel with pars pectinata 228; And when one of interlayer hole 214 terminated in the electrode 212 of odd-level 216 shank 208 parallel with pars pectinata 210, the other end of interlayer hole 214 then was connected in the electrode 230 of even level 218 shank 226 vertical with pars pectinata 228.
Please refer to Fig. 6, Fig. 6 illustrates the generalized section that is obtained along the II-II hatching of the multilayer of Fig. 3 fork metal capacitance structure.The pars pectinata 202 of the electrode 204 of odd-level 216 is staggered with the pars pectinata 210 of electrode 212, the cross-section structure of even level 218 then determines according to the position at hatching place, can be the part of electrode 230, a part or the dielectric materials layer between electrode 230 and electrode 224 of electrode 224.For example, the II-II hatching in Fig. 3 be positioned at even level 218 electrode 230 directly over, so the cross-section structure of the even level that is obtained under this II-II hatching is one of them and the part of shank 226 of the pars pectinata 228 of electrode 230.
A feature of the present utility model is exactly that the comb section of electrode of the odd-level of multilayer of the present utility model fork metal capacitance structure and even level is orthogonal, therefore pitch the metal capacitance structure in comparison with the prior art multilayer, have bigger processing procedure window, and be easier to make.
More noticeablely be, in the above-described embodiment, the direction of the fork composite electrode of odd-level and even level is not absolute, can adjust the direction of the fork composite electrode of odd-level and even level according to process requirement in the lump, only need make the pars pectinata of the fork composite electrode of odd-level and even level be vertical stack gets final product, the above only is in order to illustrate, and is not in order to limit the utility model.
Comprehensive the above, an advantage of the present utility model is exactly because the pectinate texture of the electrode of wantonly two adjacent layers of multilayer of the present utility model fork metal capacitance structure is orthogonal, therefore have wider processing procedure window, and processing procedure is simply easy to implement.
Another advantage of the present utility model is exactly because in the multilayer of the present utility model fork metal capacitance structure, the electrode pectinate texture of two adjacent layers is orthogonal up and down.Therefore can effectively improve the alignment error problem, reach the purpose of the capacitance variation that improvement caused because of the upper/lower electrode alignment error.
Though the utility model discloses as above with a preferred embodiment; right its is not in order to limiting the utility model, anyly has the knack of this skill person, in not breaking away from spirit and scope of the present utility model; when being used for a variety of modifications and variations, all within protection range of the present utility model.
Claims (10)
1, a kind of multilayer fork closes (Interdigitated) metal capacitor structure, it is characterized in that: comprise at least:
A plurality of odd-levels;
A plurality of even levels lay respectively between per two odd-levels, wherein each odd-level and each even level all comprise one first type electrode and one second type electrode at least, and this first type electrode and this second type electrode comprise at least that all a first and the parallel a plurality of second portions predeterminable range of being separated by is bonded on respectively on one side of this first, and this second portion fork parallel to each other of this second portion of this first type electrode and this second type electrode closes, and those second portions of this first type electrode of each even level and this second type electrode are perpendicular to this first type electrode of each odd-level and this second portion of this second type electrode;
A plurality of interlayer holes (Via) lay respectively between the adjacent odd-level and even level, in order to this first type electrode of electrically connecting each odd-level respectively and this first type electrode of each even level, and this second type electrode of this second type electrode of each odd-level and each even level; And
A plurality of dielectric layers lay respectively between this first type electrode and this second type electrode of each odd-level, between this first type electrode of each even level and this second type electrode and between the adjacent odd-level and even level.
2, multilayer fork metal capacitance structure according to claim 1, it is characterized in that, this first of this first of this of described each odd-level first type electrode and this second type electrode and this first type electrode of each even level and this second type electrode all has one first structure and one second structure, and this first structure is the L type with this second structure and engages.
3, multilayer fork metal capacitance structure according to claim 2, it is characterized in that, described interlayer hole is positioned at this first structure of this first of this first type electrode of each odd-level, and on this first structure of this first of this second type electrode.
4, multilayer fork metal capacitance structure according to claim 3, it is characterized in that, described interlayer hole engages this second structure of this first of this first type electrode of each this even level, and this second structure of this first of this second type electrode.
5, multilayer according to claim 2 fork metal capacitance structure is characterized in that, described interlayer hole is positioned at this first structure of this first of this first type electrode of each odd-level, and this second structure of this first of this second type electrode.
6, multilayer according to claim 5 fork metal capacitance structure is characterized in that, described interlayer hole engages this second structure of this first of this first type electrode of each even level, and this first structure of this first of this second type electrode.
7, multilayer fork metal capacitance structure according to claim 2, it is characterized in that, described interlayer hole is positioned at this second structure of this first of this first type electrode of each odd-level, and on this first structure of this first of this second type electrode.
8, multilayer according to claim 7 fork metal capacitance structure is characterized in that, described interlayer hole engages this first structure of this first of this first type electrode of each even level, and this second structure of this first of this second type electrode.
9, multilayer fork metal capacitance structure according to claim 2, it is characterized in that, described interlayer hole is positioned at this second structure of this first of this first type electrode of each odd-level, and on this second structure of this first of this second type electrode, and this interlayer hole engages this first structure of this first of this first type electrode of each even level, and this first structure of this first of this second type electrode.
10, multilayer fork metal capacitance structure according to claim 1 is characterized in that among described each odd-level and each even level, when this first type electrode was positive pole, this second type electrode was a negative pole; And work as this first type electrode is negative pole, and then this second type electrode is anodal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200420084862 CN2746498Y (en) | 2004-08-06 | 2004-08-06 | Multilayer interdigitated metal capacitor structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN 200420084862 CN2746498Y (en) | 2004-08-06 | 2004-08-06 | Multilayer interdigitated metal capacitor structure |
Publications (1)
Publication Number | Publication Date |
---|---|
CN2746498Y true CN2746498Y (en) | 2005-12-14 |
Family
ID=35583075
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN 200420084862 Expired - Lifetime CN2746498Y (en) | 2004-08-06 | 2004-08-06 | Multilayer interdigitated metal capacitor structure |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN2746498Y (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100359692C (en) * | 2003-03-04 | 2008-01-02 | 台湾积体电路制造股份有限公司 | Multilayer composite metal capacitor structure |
JPWO2020246444A1 (en) * | 2019-06-07 | 2020-12-10 |
-
2004
- 2004-08-06 CN CN 200420084862 patent/CN2746498Y/en not_active Expired - Lifetime
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100359692C (en) * | 2003-03-04 | 2008-01-02 | 台湾积体电路制造股份有限公司 | Multilayer composite metal capacitor structure |
JPWO2020246444A1 (en) * | 2019-06-07 | 2020-12-10 | ||
JP7156524B2 (en) | 2019-06-07 | 2022-10-19 | 株式会社村田製作所 | measuring instrument |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR101557157B1 (en) | Land grid feedthrough low esl technology | |
KR101018254B1 (en) | Multilayer chip capacitor | |
TWI399765B (en) | Laminated electronic components | |
US7348624B2 (en) | Semiconductor device including a capacitor element | |
CN1732570A (en) | Multilayer capacitor with multiple plates per layer | |
KR100887124B1 (en) | Multilayer Chip Capacitor | |
CN1794389A (en) | Multilayered chip capacitor and printed circuit board having embedded multilayered chip capacitor | |
CN1527385A (en) | Multilayer composite metal capacitor structure | |
KR20120058128A (en) | Multi-layered ceramic capacitor | |
CN1905099A (en) | Multilayer capacitor | |
CN1815643B (en) | Laminated electronic component | |
CN2746498Y (en) | Multilayer interdigitated metal capacitor structure | |
CN108091641A (en) | MIM capacitor and preparation method thereof | |
CN101141849B (en) | Built-in capacity cell structure and method for producing same | |
CN200950440Y (en) | Super micro-micron stacking parallel metal/insulator/metal structure capacitor | |
CN2686061Y (en) | Electric capacity pair structure capable of raising matching | |
CN108123037A (en) | MIM capacitor and preparation method thereof | |
TWI222089B (en) | Multilevel interdigitated metal capacitor structure | |
CN1665018A (en) | A small-area high-performance differential inductor with laminated construction | |
CN101043034A (en) | Capacitance structure | |
CN110858580A (en) | Dielectric capacitor | |
CN2838011Y (en) | Laminated wafer electronic component with inner poles | |
KR100951292B1 (en) | Multilayer chip capacitor | |
CN1231762A (en) | Method for manufacturing integrated semiconductor memory | |
CN206758278U (en) | A kind of multi-layer stacks ceramic capacitor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
AV01 | Patent right actively abandoned |
Effective date of abandoning: 20080102 |
|
C25 | Abandonment of patent right or utility model to avoid double patenting |