CN200950440Y

CN200950440Y - Super micro-micron stacking parallel metal/insulator/metal structure capacitor

Info

Publication number: CN200950440Y
Application number: CN 200620121192
Authority: CN
Inventors: 夏洪旭; 王政烈
Original assignee: Hejian Technology Suzhou Co Ltd
Current assignee: Hejian Technology Suzhou Co Ltd
Priority date: 2006-07-25
Filing date: 2006-07-25
Publication date: 2007-09-19
Anticipated expiration: 2016-07-25

Abstract

A deep-submicron stack parallel MIM capacitor has a multilayer stack MIM structure, a plurality of metal layers or polysilicon layers form the wiringlayers which are the down polar plates, the upper polar plates comprising conducting layers are above the down plate. The patterns of the upper polar plates are defined by a same MMC mask. The insulation dielectric is arranged between the parallel upper and down polar layers thus forming a fixed separate capacitor, the connection terminals which are educed from the upper and lower polar plates and pass through the through holes on the metal layers are the two nodes forming the MiM capacitor. The separate capacitors between wiring layers construct the series connection capacitors with the tracked structures through wiring. Under the same graph layout area, the capacitor of the utility has a huger capacitance, and the additional masks are not needed, therefore the goal of saving the layout area is achieved.

Description

Deep-submicron piles up metal/insulator in parallel/metal structure capacitor

Technical field

The utility model relates to a kind of deep-submicron metal/insulator/metal (Metal insulatorMetal) (hereinafter to be referred as MiM) structure capacitive device, particularly a kind ofly piles up deep-submicron MiM capacitor in parallel.

Background technology

In deep-submicron (0.25 μ m, 0.18 μ m, 0.13 μ m) level semiconductor preparation technology, MiM structure capacitive device is the fixed capacity element that a kind of quilt generally adopts.Because this class component is usually located between top layer and the following layer of metal, so, capacitor and other metal for fear of high-frequency operation produce coupling effect (Coupling) and produce unnecessary circuit noise (Noise), MiM below need avoid metal line (routing) and ground floor metal to want ground connection to lower this ghost effect (shielding) usually, but also so and cause the entire circuit layout, be the increase of chip size (chip size) area.Therefore, how to increase its electric capacity under the area of identical MiM, be the problem that each semiconductor producer and integrated circuit (IC) Chevron Research Company (CRC) are concerned about always.

Traditional MiM capacitor is usually located between top layer and the following layer of metal (as shown in Figure 1), suppose to have in the manufacturing process 6 layers of metal, top-level metallic 1 (Top Metal) is METAL 6, its pattern is defined by the M6 mask, layer metal 2 second from the bottom (Last Second Metal) is METAL5, pattern is defined by the M5 mask, bottom crown as the MiM capacitor, the top crown 22 of MiM capacitor (for example Ti/TiN) is defined by one deck mask (being referred to as MMC usually), on, be thin layer insulation dielectric 21 (Dielectric) between following two parallel electrode plates, constitute a fixed capacity element.The via 11 (VIA) of metal interlevel is drawn from upper and lower pole plate respectively and is connected to two nodes of M6 as the MiM capacitor.

The dielectric coefficient (ε) of the dielectric 21 between the unit-area capacitance value of MiM capacitor and the upper and lower parallel electrode plate is directly proportional, and is inversely proportional to distance between the upper and lower parallel electrode plate 2,22.Because the restriction of manufacturing process, these parameters are difficult to have remarkable change to improve the leeway of unit-area capacitance value again.

The utility model content

The utility model is developed at above-mentioned problem, its objective is the problem that exists for the high capacity capacitor that overcomes present preparation.

To achieve these goals, the deep-submicron MiM that the utility model proposes a kind of novelty piles up the parallel-connection structure capacitor, its traditional on the single MiM electric capacity basis between top layer and the following layer of metal, utilize each layer metal of MiM below, use same mask (mask) to make single MiM capacitor and its parallel connection become and pile up the parallel-connection structure capacitor, make its total capacitance value increase several times, do not increase extra mask, significantly save the purpose of layout area thereby reach.

A kind of deep-submicron MiM of the present utility model piles up the MiM structure that the parallel-connection structure capacitor has multiple-level stack.

Deep-submicron MiM of the present utility model piles up the parallel-connection structure capacitor, a plurality of metals or polysilicon layer are arranged as wiring layer, constitute bottom crown, its top has conductive layer to constitute top crown, between upper and lower two parallel electrode plates insulation dielectric is arranged, constitute single fixed capacitor, the via of metal interlevel is drawn two nodes of connection as the MiM capacitor from upper and lower pole plate respectively, and the single fixed capacitor between each wiring layer constitutes the parallel-connection structure capacitor by wiring.Like this, for the MiM shunt capacitor structure that the n layer piles up, its unit-area capacitance roughly is n a times of traditional MiM capacitor.

Via between every layer has 3 groups, is respectively on this layer capacitor top crown, connects the bottom crown of a top capacitor; On this layer capacitor bottom crown, connect the top crown of a top capacitor; And on independent metal level, connect layer capacitor bottom crown and this layer capacitor top crown down.

The pattern of single MiM capacitor top crown is defined by same MMC mask, and its upright position is fixed.For avoiding having more expensive mask cost, the utility model uses same MMC mask to reuse repeatedly.

Since the utility model traditional on the MiM capacitor basis between top layer and the following layer of metal, between the more following several layers metal and even between metal and the polysilicon, utilize same MiM mask, make capacity cell and with its parallel connection, so same layout area, the electric capacity after the parallel connection enlarges markedly, and does not need extra mask, do not increase extra mask thereby reach, significantly save the purpose of layout area.

Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.For those skilled in the art that, to the detailed description of the present utility model, above-mentioned and other purposes of the present utility model, feature and advantage will be apparent.

Description of drawings

Fig. 1 is the structural representation of traditional MiM capacitor.

Fig. 2 is the structural representation of piling up of a preferred embodiment of the present utility model MiM capacitor in parallel.

Fig. 3 is the equivalent circuit diagram that piles up MiM electric capacity in parallel.

Fig. 4 is a kind of typical placement-and-routing of the present utility model conceptual scheme.

Embodiment

Fig. 2 is the structural representation of piling up of a preferred embodiment of the present utility model MiM capacitor in parallel.As shown in Figure 2, second from the bottom layer metal 2 (Last second metal) top has insulating barrier (Insulator) (indicate among the figure, can referring to Fig. 1), conductive layer (Ti/TiN) 22 to constitute single MiM capacitor; There are insulating barrier (Insulator), conductive layer (Ti/TiN) 22 to constitute single MiM capacitor equally in layer metal 3 third from the bottom (Last third metal) top; Similarly, more between the metal level of below (even between polysilicon) also can constitute and pile up the MiM capacitor.In a preferred embodiment of the present utility model, for avoiding increasing extra mask, the top crown pattern of all MiM capacitors is defined by same MMC mask, promptly these Ti/TiN conductive layers 22 in vertical direction pattern fix.Metal wiring layer (top-level metallic 1, layer metal 2...... second from the bottom) is defined by different masks, and its pattern can be inequality.

Piling up the MiM capacitor connects by parallel way.Via 11 between every layer has 3 groups, is respectively on this layer capacitor top crown, connects the bottom crown of a top capacitor; On this layer capacitor bottom crown, connect the top crown of a top capacitor; And on independent metal level, connect layer capacitor bottom crown and this layer capacitor top crown down.

The resistance of ignoring metal and via, piling up MiM structure capacitive device in parallel can equivalence be the parallel connection of the MiM capacitor of several equal capacitance, as shown in Figure 3.According to the physics formula, n identical capacitor parallel connection, the n that its total capacitance is single capacitor is doubly.Therefore under the layout area of same distribution, for the MiM parallel-connection structure capacitor that has the n layer to pile up, its electric capacity is n times of traditional MiM capacitor.

Fig. 4 is based on the above-mentioned a kind of typical placement-and-routing conceptual scheme that piles up the structural requirement of MiM electric capacity in parallel.As shown in Figure 4, suppose to have in the manufacturing process 6 layers of metal, top-level metallic MTEAL6, layer metal M ETAL 4 third from the bottom, layer 5 metal M ETAL 2...... pattern reciprocal is identical, it is a MiM capacitor bottom crown at MMC mask pattern 22 upper areas, and the below is independent pocket, as connecting layer capacitor bottom crown and this layer capacitor top crown down; Layer metal M TEAL 5 second from the bottom, fourth from the last layer metal M ETAL 3, layer 6 metal M ETAL1...... pattern reciprocal is identical, it is independent pocket at MMC mask pattern 22 upper areas, as connecting layer capacitor bottom crown and this layer capacitor top crown down, lower zone is a MiM capacitor bottom crown.Via 11 between every layer has 3 groups, is respectively on independent pocket, on MMC mask pattern 22, on bulk zone (MiM capacitor bottom crown).The structure that defines out according to this kind Butut mode just as shown in Figure 2, for piling up MiM structure capacitive in parallel.

Traditional MiM capacitor is brought into use the MMC manufacturing process at layer second from the bottom, piles up MiM capacitor in parallel and brings into use the MMC manufacturing process at the metal level that needs MiM electric capacity.Dielectric layer is arranged on metal level, and second layer conductive layer (as Ti/TiN) etc. utilize metal mask and MMC mask to define the bottom crown and the top crown of MiM capacitor respectively.After via is finished, use upper strata metal mask and same MMC mask to define a last MiM structure capacitive device, by that analogy to finishing MiM structure capacitive device topmost with same method.Use the mask of design producing shown in Figure 4 in the process, just obtain piling up MiM structure capacitive device in parallel.

Piling up being manufactured on of MiM structure capacitive device in parallel only needs the change technological process on the method, do not need to increase any extra mask, the unit-area capacitance value of the capacitor that can be multiplied.

Certainly; the utility model also can have other embodiment; under the situation that does not deviate from the utility model spirit and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection range of claim of the present utility model.

Claims

1. a deep-submicron piles up metal/insulator in parallel/metal structure capacitor, it is characterized in that having the metal/insulator/metal structure of multiple-level stack.

2. deep-submicron according to claim 1 piles up metal/insulator in parallel/metal structure capacitor, it is characterized in that having a plurality of metals or polysilicon layer as wiring layer, constitute bottom crown, its top has conductive layer to constitute top crown, between upper and lower two parallel electrode plates insulation dielectric is arranged, constitute single fixed capacitor, the via of metal interlevel is drawn two nodes of connection as metal/insulator/metal capacitor from upper and lower pole plate respectively, and the single fixed capacitor between each wiring layer piles up the parallel-connection structure capacitor by the wiring formation.

3. deep-submicron according to claim 1 and 2 piles up metal/insulator in parallel/metal structure capacitor, and the via between it is characterized in that every layer has 3 groups, is respectively on this layer capacitor top crown, connects the bottom crown of a top capacitor; On this layer capacitor bottom crown, connect the top crown of a top capacitor; And on independent metal level, connect layer capacitor bottom crown and this layer capacitor top crown down.

4. deep-submicron according to claim 1 and 2 piles up metal/insulator in parallel/metal structure capacitor, it is characterized in that, the pattern of single metal/insulator/metal capacitor top crown is defined by same mask, and its upright position is fixed.