CN2742580Y - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN2742580Y
CN2742580Y CNU200420118791XU CN200420118791U CN2742580Y CN 2742580 Y CN2742580 Y CN 2742580Y CN U200420118791X U CNU200420118791X U CN U200420118791XU CN 200420118791 U CN200420118791 U CN 200420118791U CN 2742580 Y CN2742580 Y CN 2742580Y
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semiconductor device
dielectric layer
substrate
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黄建朝
陈光鑫
杨富量
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本实用新型提供一种半导体装置,包括:一个基底;位于基底上的多个栅极;位于栅极和基底之间的栅介电层,各栅介电层的厚度大体相同;栅极中至少一个的材料为第一材料;以及栅极中至少一个的材料为不同于第一材料的第二材料。本实用新型提供的半导体装置,不同栅极具有不同的材料,并且具有不同厚度的栅介电层,因而能够提高半导体装置的性能。

Description

半导体装置
技术领域
本实用新型涉及一种半导体装置,特别是涉及一种具有金属栅极的半导体装置。
背景技术
金属氧化物场效应晶体管(metal-oxide-semiconductorfield effect transistor,MOSFET)栅介电层的完整性与MOSFET装置的可靠性和使用寿命密切相关。栅介电层的厚度随产品尺寸的缩小而变薄,因而导致栅极漏电流,增加了耗电量,降低了装置的性能。
高介电常数材料是指介电常数大于5的材料,例如SiON、HfOxSiy或HfO2,可以用来实现漏电流与等效栅极氧化层厚度(equivalent oxide thickness,EOT)的最小化。金属栅极可以用来降低栅极阻抗。此外,金属栅极还可以降低来自多晶硅栅极的硼离子的隧道效应所造成的栅极漏电流。
在栅极的形成方面,存在着许多制程因素所造成的问题,例如化学机械研磨的终点侦测、隔离物和衬垫所造成的失效,以及栅极多晶硅的失效。在源极与漏极的接点形成方面,其问题包括浅沟槽隔离的失效和隔离物氧化物衬垫的失效。这些制程通常具有繁复的步骤,因而增加了制程成本。
实用新型内容
有鉴于此,本实用新型的主要目的在于提供一种半导体装置,以改善现有半导体装置的栅极所面临的问题。
为了实现上述目的,本实用新型提供一种半导体装置,包括:一个基底;多个位于所述基底上的栅极;分别位于各个所述栅极与所述基底之间的第一栅介电层,所述第一栅介电层的厚度大体相同;所述栅极中至少一个的材料为第一材料;以及所述栅极中至少一个的材料为不同于所述第一材料的第二材料。
本实用新型所述的半导体装置,所述第一材料为多晶硅。
本实用新型所述的半导体装置,所述第二材料是金属、金属合金、金属硅化物中的一个或其组合。
本实用新型所述的半导体装置,所述第一栅介电层中至少一个是氧化物。
本实用新型所述的半导体装置,所述第一栅介电层中至少一个是高介电常数材料。
本实用新型所述的半导体装置,所述半导体装置还包括:至少一个位于所述基底上的第二栅极,所述第二栅极的材料是不同于所述第一材料和所述第二材料的第三材料;以及位于所述第二栅极与所述基底之间的第二栅介电层,所述第二栅介电层的厚度不同于所述第一栅介电层的厚度。
本实用新型所述的半导体装置,所述第三材料是金属硅化物。
本实用新型所述的半导体装置,所述第三材料是混合物。
本实用新型所述的半导体装置,所述第二栅介电层是氧化物或高介电常数材料。
为了实现上述目的,本实用新型还提供一种半导体装置,包括:一个基底;多个位于所述基底上的第一栅极;分别位于各所述第一栅极与所述基底之间的第一栅介电层,所述第一栅介电层的厚度大体相同;所述第一栅极中至少一个的材料为第一材料;所述第一栅极中至少一个的材料为不同于所述第一材料的第二材料;至少一个位于所述基底上的第二栅极,所述第二栅极的材料为所述第一材料或所述第二材料;以及位于所述第二栅极与所述基底之间的第二栅介电层,所述第二栅介电层的厚度不同于所述第一栅介电层的厚度。
为了实现上述目的,本实用新型还提供一种半导体装置,包括:一个基底;多个位于所述基底上的第一栅极;分别位于各所述第一栅极与所述基底之间的第一栅介电层,所述第一栅介电层的厚度大体相同;所述第一栅极中至少一个的材料为第一材料;所述第一栅极中至少一个的材料为不同于所述第一材料的第二材料;至少一个位于所述基底上的第二栅极,所述第二栅极的材料为不同于所述第一材料与所述第二材料的第三材料;以及位于所述第二栅极与所述基底之间的第二栅介电层,所述第二栅介电层的厚度不同于所述第一栅介电层的厚度。
为了实现上述目的,本实用新型还提供一种半导体装置,包括:一个基底;一个位于所述基底上的金属栅极;以及多个隔离物,所述金属栅极的旁边具有第一隔离物,所述第一隔离物的旁边具有第二隔离物。
本实用新型所述的半导体装置,所述金属栅极为金属硅化物。
本实用新型所述的半导体装置,所述第一隔离物和所述第二隔离物是氮氧化硅、氮化硅、碳化硅中的一个或其组合。
本实用新型所述的半导体装置,所述第一隔离物位于所述栅极的周围,两者之间界有一个间隔区域,并且所述第二隔离物位于所述间隔区域的内外。
本实用新型所述的半导体装置,所述第二隔离物位于所述第一隔离物的旁边,并且位于所述栅极的周围,所述第二隔离物与所述栅极之间界有一个间隔区域,并且所述间隔区域的内外还包括一个第三隔离物。
本实用新型所述的半导体装置,所述第一隔离物为二氧化硅。
本实用新型所述的半导体装置,所述第二隔离物和所述第三隔离物是氮氧化硅、氮化硅、碳化硅中的一个或其组合。
为了实现上述目的,本实用新型还提供一种半导体装置,包括:一个基底;一个位于所述基底上的栅极;位于所述栅极周围的第一隔离物,两者之间界有一个间隔区域;以及位于所述间隔区域内外的第二隔离物。
为了实现上述目的,本实用新型还提供一种半导体装置,包括:一个基底;一个位于所述基底上的栅极;位于所述基底上且位于所述栅极旁边的第一隔离物;位于所述第一隔离物旁边且位于所述栅极周围的第二隔离物,所述第二隔离物与所述栅极之间界有一个间隔区域;以及位于所述间隔区域内外的第三隔离物。
本实用新型提供的半导体装置,栅极可以具有不同材料,并且具有不同厚度的栅介电层。因此,可以在核心元件使用较薄的栅介电层以增进其效能,而在其它核心元件与输入/输出元件(input/output device)使用较厚的栅介电层以减少栅极漏电流,从而获得高性能的核心元件。
附图说明
图1是剖面图,显示一个基底,其上具有一个介电层和一个栅极。
图2是剖面图,显示位于栅极旁边的偏移隔离物和基底上的轻掺杂漏极。
图3是剖面图,显示位于栅极旁边的第一隔离物和位于第一隔离物旁的第二隔离物。
图4是剖面图,显示基底上的源极和漏极。
图5是剖面图,显示刻蚀后的第一隔离物,其上表面约与第二隔离物的下表面等高。
图6是剖面图,显示在装置上刻蚀第一隔离物后所留下来的位置上沉积一个金属层。
图7是剖面图,显示使金属层与装置反应后所形成的金属栅极、源极和漏极的接点,并将未反应的金属层蚀除。
图8是剖面图,显示在装置上形成的接点刻蚀停止层。
图9是剖面图,显示在一个基底上形成多个不同材料的栅极,各栅极具有大约相同厚度的介电层。
图10是剖面图,显示在一个基底上形成多个不同材料的第一栅极,各第一栅极具有大约相同厚度的介电层;以及在上述基底上形成的第二栅极,其材料与第一栅极中的一个相同;第二栅极的介电层厚度不同于第一栅极的介电层厚度。
图11是剖面图,显示在一个基底上形成多个不同材料的第一栅极,各第一栅极具有大约相同厚度的介电层;以及在上述基底上形成的第二栅极,其材料不同于第一栅极;第二栅极的介电层厚度不同于第一栅极的介电层厚度。
具体实施方式
为使本实用新型的上述和其它目的、特征和优点更明显易懂,以下给出较佳实施例,并结合附图详细说明。
如图1所示,在一个实施例中,半导体装置100的制造始于一个基底102。有许多种材料可以作为基底102,包括但不限于体硅(bulk silicon)、SOI(silicon on insulator,绝缘体上长多晶硅膜)、硅锗(SiGe)或其它适当的半导体材料。在基底102上形成一个栅介电层104和一个栅极106。有许多种材料可以作为栅介电层104,包括但不限于氧化物和高介电常数材料,包括介电常数大于5的材料,例如SiON、HfOxSiy、HfO2或上述材料的组合。有许多种材料可以作为栅极106,包括但不限于多晶硅。图1所示的基底102上的栅介电层104及其上的栅极106,可以使用适当的光刻、刻蚀等现有技术,形成图形化的栅介电层104与栅极106。例如,图形化下层材料表面的制程包括光刻胶的图形化、干刻蚀以及光刻胶的剥除。光刻胶的图形化包括下列步骤:光刻胶涂布、软烤(soft bake)、掩膜版对准、曝光、显影以及硬烤(hard bake)。
如图2所示,形成栅极106与栅介电层104之后,形成一个偏移隔离物108。有许多种材料可以作为偏移隔离物108,包括但不限于氧化物,例如二氧化硅。偏移隔离物108的形成,可以选择适当的现有技术,例如化学气相沉积法及其后的刻蚀。形成偏移隔离物108之后,可以使用离子注入技术,在基底102形成轻掺杂漏极110。由于偏移隔离物108的存在,轻掺杂漏极110自栅极106与栅介电层104之处,偏移了D长度。为了突出本实用新型的重点,后续附图将省略轻掺杂漏极110。
如图3所示,接下来,在基底102上和栅极106与栅介电层104的旁边形成一个隔离物112。隔离物112可以形成于偏移隔离物108上,而使偏移隔离物108成为隔离物112的一部分。隔离物114形成于隔离物112的旁边。有许多种材料可以作为隔离物112,包括氧化物,例如二氧化硅。有许多种材料可以作为隔离物114,包括氮氧化硅、氮化硅、碳化硅或上述材料的组合。隔离物112、114的形成,可以选择适当的现有技术,例如化学气相沉积法及其后的刻蚀。
如图4所示,在形成隔离物之后,使用掺杂方法(例如离子注入)在基底102形成一个漏极118,然后对装置100施以退火。
如图5所示,刻蚀隔离物112,移除相邻于栅极106和隔离物114的部分,形成隔离物112′。在本实施例中,将隔离物112刻蚀至与隔离物114的下表面120的高度大体相同的程度。
然后,如图6所示,在装置100上沉积一个金属层122。金属层122可以是单一金属或金属合金,包括但不限于镍、钴、钼、钨、钛、钽或其它性质相近的合金。金属层122的沉积可以使用适当的现有方法,例如化学气相沉积或物理气相沉积。金属层122的沉积量应该足以与栅极106反应而形成一个金属栅极。
如图7所示,将装置100升温一段时间,使得金属层122与栅极106发生反应而形成金属硅化物栅极(金属栅极)106′。所需的温度与时间取决于所选用的金属层122及栅极106。对镍金属层和多晶硅栅极而言,在350至600℃的温度下维持10秒至5分钟,即足以形成硅化镍栅极。金属层122还可以与基底102发生反应以形成源极116与漏极118的接点126。然后,将未反应的金属蚀除。
如图8所示,在形成金属栅极106′之后,在装置100上形成一个薄膜128。有许多种材料可以作为薄膜128,包括但不限于氮化硅、氮氧化硅或上述材料的组合。薄膜128还可以作为接点刻蚀停止层。薄膜128的形成可以使用适当的现有方法,例如化学气相沉积法。
在图8中,形成有金属栅极106′与薄膜128的装置100具有位于基底102上的金属栅极106′,栅介电层104介于金属栅极106′与基底102之间,隔离物112′则位于基底102上且在金属栅极106′的旁边。隔离物114位于隔离物112′的旁边和金属栅极106′的周围,且与金属栅极106′分离,两者之间介有一个间隔区域130。薄膜128位于间隔区域130的内外,覆于装置100的上面。
本实用新型可以形成不同材料的栅极,并且具有不同厚度的栅介电层。因此,可以在核心元件使用较薄的栅介电层以增进其效能,而在其它核心元件与输入/输出元件(input/outputdevice)使用较厚的栅介电层以减少栅极漏电流,从而获得高性能的核心元件。
如图9所示,在一个实施例中,基底200的表面上具有栅极202和204。有许多种材料可以作为基底200,包括但不限于体硅或SOI。在基底200,每个栅极202与204均有相对应的源极116与漏极118。栅极202具有一个介电层206a,位于其与基底200之间。栅极204具有一个介电层206b,位于其与基底200之间。有许多种材料可以作为介电层206a与206b,包括但不限于氧化物与高介电常数材料,其中包括介电常数大于5的材料,例如SiON、HfOxSiy或HfO2。为了突出本实用新型的特点,装置上的隔离物、接点以及其它结构均被省略。介电层206a与206b具有大体相同的厚度H。栅极202的材料为材料A,包括但不限于多晶硅、金属、金属合金、金属硅化物或上述材料的组合。栅极204的材料为材料B,不同于材料A,包括但不限于多晶硅、金属、金属合金、金属硅化物或上述材料的组合。
如图10所示,在另一个实施例中,基底200的表面上具有栅极202、204和206。有许多种材料可以作为基底200,包括但不限于体硅或SOI。在基底200,每个栅极202、204、206均有相对应的源极116和漏极118。栅极202具有一个介电层208a,位于其与基底200之间。栅极204具有一个介电层208b,位于其与基底200之间。栅极206具有一个介电层210,位于其与基底200之间。有许多种材料可以作为介电层208a、208b和210,包括但不限于氧化物与高介电常数材料,其中包括介电常数大于5的材料,例如SiON、HfOxSiy或HfO2。为了突出本实用新型的特点,装置上的隔离物、接点以及其它结构均被省略。介电层208a与208b具有大体相同的厚度H,介电层210的厚度I大于厚度H。此外,厚度I也可以小于厚度H。栅极202的材料为材料A,包括但不限于多晶硅、金属、金属合金、金属硅化物或上述材料的组合。栅极204的材料为材料B,不同于材料A,包括但不限于多晶硅、金属、金属合金、金属硅化物或上述材料的组合。栅极206的材料则为材料A或B。
如图11所示,在另一个实施例中,基底200的表面上具有栅极202、204、206。有许多种材料可以作为基底200,包括但不限于体硅或SOI。在基底200,每个栅极202、204、206均有相对应的源极116和漏极118。栅极202具有一个介电层208a,位于其与基底200之间。栅极204具有一个介电层208b,位于其与基底200之间。栅极206具有一个介电层210,位于其与基底200之间。有许多种材料可以作为介电层208a、208b和210,包括但不限于氧化物与高介电常数材料,其中包括介电常数大于5的材料,例如SiON、HfOxSiy或HfO2。为了突出本实用新型的特点,装置上的隔离物、接点以及其它结构均被省略。介电层208a与208b具有大体相同的厚度H,介电层210的厚度I大于厚度H。此外,厚度I也可以小于厚度H。栅极202的材料为材料A,包括但不限于多晶硅、金属、金属合金、金属硅化物或上述材料的组合。栅极204的材料为材料B,不同于材料A,包括但不限于多晶硅、金属、金属合金、金属硅化物或上述材料的组合。栅极206的材料为材料C,不同于材料A或B,包括但不限于多晶硅、金属、金属合金、金属硅化物或上述材料的组合。
虽然本实用新型已通过较佳实施例说明如上,但该较佳实施例并非用以限定本实用新型。本领域的技术人员,在不脱离本实用新型的精神和范围内,应有能力对该较佳实施例做出各种更改和补充,因此本实用新型的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下:
100:半导体装置                128:薄膜
102:基底                      130:间隔区域
104:栅介电层                  200:基底
106:栅极                      202:栅极
106′:金属栅极                204:栅极
108:偏移隔离物                206:栅极
110:轻掺杂漏极                206a:栅介电层
112:隔离物206                 b:栅介电层
112′:隔离物                  208a:栅介电层
114:隔离物                    208b:栅介电层
116:源极                      210:栅介电层
118:漏极                      A、B、C:材料
120:下表面                    D:长度
122:金属层                    I、H:厚度
126:接点

Claims (16)

1、一种半导体装置,其特征在于包括:
一个基底;
多个位于所述基底上的栅极;
分别位于各所述栅极与所述基底之间的第一栅介电层,所述第一栅介电层的厚度大体相同;
所述栅极中至少一个的材料为第一材料;以及
所述栅极中至少一个的材料为不同于所述第一材料的第二材料。
2、根据权利要求1所述的半导体装置,其特征在于所述第一材料为多晶硅。
3、根据权利要求1所述的半导体装置,其特征在于所述第二材料是金属、金属合金、金属硅化物中的一个或其组合。
4、根据权利要求1所述的半导体装置,其特征在于所述第一栅介电层中至少一个是氧化物。
5、根据权利要求1所述的半导体装置,其特征在于所述第一栅介电层中至少一个是高介电常数材料。
6、根据权利要求1所述的半导体装置,其特征在于所述半导体装置还包括:
至少一个位于所述基底上的第二栅极,所述第二栅极的材料是不同于所述第一材料和所述第二材料的第三材料;以及
位于所述第二栅极与所述基底之间的第二栅介电层,所述第二栅介电层的厚度不同于所述第一栅介电层的厚度。
7、根据权利要求6所述的半导体装置,其特征在于所述第三材料是金属硅化物。
8、根据权利要求6所述的半导体装置,其特征在于所述第三材料是混合物。
9、根据权利要求6所述的半导体装置,其特征在于所述第二栅介电层是氧化物或高介电常数材料。
10、一种半导体装置,其特征在于包括:
一个基底;
一个位于所述基底上的金属栅极;以及
多个隔离物,所述金属栅极的旁边具有第一隔离物,所述第一隔离物的旁边具有第二隔离物。
11、根据权利要求10所述的半导体装置,其特征在于所述金属栅极为金属硅化物。
12、根据权利要求10所述的半导体装置,其特征在于所述第一隔离物和所述第二隔离物是氮氧化硅、氮化硅、碳化硅中的一个或其组合。
13、根据权利要求10所述的半导体装置,其特征在于所述第一隔离物位于所述栅极的周围,两者之间界有一个间隔区域,并且所述第二隔离物位于所述间隔区域的内外。
14、根据权利要求10所述的半导体装置,其特征在于所述第二隔离物位于所述第一隔离物的旁边,并且位于所述栅极的周围,所述第二隔离物与所述栅极之间界有一个间隔区域,并且所述间隔区域的内外还包括一个第三隔离物。
15、根据权利要求10所述的半导体装置,其特征在于所述第一隔离物为二氧化硅。
16、根据权利要求14所述的半导体装置,其特征在于所述第二隔离物和所述第三隔离物是氮氧化硅、氮化硅、碳化硅中的一个或其组合。
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