CN2739791Y - 半导体装置 - Google Patents
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- CN2739791Y CN2739791Y CNU2004200778109U CN200420077810U CN2739791Y CN 2739791 Y CN2739791 Y CN 2739791Y CN U2004200778109 U CNU2004200778109 U CN U2004200778109U CN 200420077810 U CN200420077810 U CN 200420077810U CN 2739791 Y CN2739791 Y CN 2739791Y
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
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Abstract
本实用新型揭示一种半导体装置,其包括一不含氮的介电抗反射结构以及一不含氮的氧化硅层。不含氮的介电抗反射结构是设置于一基底上方,而不含氮的氧化硅层是设置于不含氮的介电抗反射结构上方,用以作为一保护层,且其折射率在1.4到1.7的范围。
Description
技术领域
本实用新型是关于一种半导体装置,特别是有关于一种包括一不含氮的介电抗反射结构以及一不含氮的氧化硅层的半导体装置。
背景技术
一般而言,微影制程是用以在一如硅芯片的半导体基底上方形成一预定的电路图案,或是在制程期间形成预定的电路图案于半导体基底上的特定层上方。典型的微影制程是将一可触发光化学反应的光阻材料涂覆于基底上。之后,实施一软烤(soft baking)步骤以去除光阻材料中的溶剂。接着,对光阻材料实施曝光及显影程序以在基底上方形成具有预定图形尺寸的光阻层。此图案化的光阻层是作为一蚀刻罩幕以选择性蚀刻该半导体基底或是形成于其上方的特定层。若为影制程之后所形成的图案不正确,例如关键图形尺寸(critical dimension,CD)改变或形成错误的图案(mispatterning),则半导体基底上的光阻层必须完全去除,并再次于基底上重新涂覆一光阻层,用以形成一新的图案。此称作光阻重做(rework)。
光阻重做比直接报废芯片具有经济性。然而,在剥除光阻层期间所使用的含氧电浆可能使其下方的抗反射层受损。举例而言,在剥除光阻期间,抗反射层与电浆中的氧原子发生反应而氧化,导致抗反射层材料原有的折射率及消光系数(extinction coefficient)发生变化而使抗反射层失去作用。
美国专利第6,352,922号揭示一种具有双层抗反射层的半导体装置的制造方法。其中,该方法利用一氮化层及一仅藉由碳氢气体所形成的上层作为双层抗反射层,其可降低其反射率而利于微影制程的进行。然而,其并未考量关于光阻重做期间抗反射层受损的问题。
发明内容
有鉴于此,本实用新型的目的在于提供一种半导体装置,其利用一氧化硅层保护下方的抗反射结构受到电浆的损害,藉以防止其折射率及消光系数发生变化。
根据上述的目的,本实用新型提供一种防止去除光阻期间损坏抗反射结构的方法。首先,在一抗反射结构上方原位(in-situ)形成一不含氮的氧化硅层以作为一保护层,其折射率在1.4到1.7的范围且消光系数在0到0.5的范围。接着,在不含氮的氧化硅层上方形成一光阻图案层。最后,去除光阻图案层。
再者,可利用硅烷(SiH4)及二氧化碳(CO2)作为反应气体而藉由电浆增强化学气项沉积(PECVD)原位形成不含氮的氧化硅层。
再者,不含氮的氧化硅层可为一二氧化硅层或是一碳氧化硅层,其厚度在10到500埃的范围。
又根据上述的目的,本实用新型提供一种半导体装置,适用于防止去除光阻期间损坏抗反射结构,其包括一不含氮的介电抗反射结构及一不含氮的氧化硅层。不含氮的介电抗反射结构是设置于一基底上而不含氮的氧化硅层则设置于不含氮的介电抗反射结构上方以作为一保护层,其折射率在1.4到1.7的范围且其消光系数在0到0.5的范围。
再者,可利用硅烷及二氧化碳作为反应气体而藉由电浆增强化学气项沉积原位形成不含氮的氧化硅层。
再者,不含氮的氧化硅层可为一二氧化硅层或是一碳氧化硅层,其厚度在10到500埃的范围。
附图说明
图1a到图1f图绘示出根据本实用新型实施例的防止去除光阻期间损坏抗反射结构的方法剖面示意图。
符号说明:
100~基底;102~待定义层;104~抗反射结构;106~不含氮的氧化硅层;108、112~能量敏感层;108a、112a~光阻图案层;110~含氧电浆。
具体实施方式
为让本实用新型的上述目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下:
以下配合图1a到图1f说明本实用新型实施例的防止去除光阻期间损坏抗反射结构的方法剖面示意图。
首先,请参照图1a,提供一基底100,例如一硅芯片。在本实施例中,基底100中包含不同的组件,例如晶体管、二极管、及其它现有的半导体组件(未绘示)。另外,此基底100同样包含其它金属内联机层。为了简化图式,此处仅绘示出一平整基底。接着,在基底100上方沉积一待定义层102。此处,待定义层102可为一导电层,例如一掺杂的复晶硅层或是其它半导体制程所习用的金属层。再者,该待定义层102可为一介电层用以作为内层介电层(ILD)或是金属层间介电层(IMD)。举例而言,此介电层可由二氧化硅、磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、或如掺杂氟的硅玻璃(FSG)的低介电材料所构成。
接着,在待定义层102上形成一抗反射结构104,例如一抗反射层,其可为一藉由化学气相沉积所构成的氮氧化硅层,其中利用如硅烷、氧气、及氮气等作为反应气体。再者,抗反射层104亦可为一不含氮的介电抗反射层,例如一利用硅烷及氧气作为反应气体并藉由化学气相沉积所构成的富含硅的氧化层(SiOx),其中x<2。
接着,在抗反射层104上方形成一不含氮的氧化硅薄层106。在本实施例中,不含氮的氧化硅层106可为一完全氧化的材料,例如二氧化硅或是碳氧化硅。此不含氮的氧化硅薄层106的厚度在10到500埃的范围。较佳地,不含氮的氧化硅薄层106的厚度约为50埃。
再者,不含氮的氧化硅层106可藉由现有沉积技术而形成之,例如电浆增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、常压化学气相沉积(APCVD)、高密度电浆化学气相沉积(HDPCVD)、或其它合适的化学气相沉积。在本实施例中,不含氮的氧化硅层106是藉由电浆增强化学气相沉积形成,其中利用以下至少一种气体作为第一反应气体以提供硅原子:SiH4、SiH6、四甲基硅烷(tetramethylsilane,4MS)、三甲基硅烷(trimethylsilane,3MS)、及四乙基硅酸盐(TEOS)。再者,利用以下至少一种气体作为第二反应气体以提供氧原子:CO2、O2、及H2O。较佳地,第一反应气体为SiH4且第二反应气体为CO2。再者,可使用氦气、氩气、或其它惰性气体作为载气。另外,需注意的是若采用不含氮的介电抗反射材料作为抗反射层104,不含氮的氧化硅薄层106可藉由电浆增强化学气相沉积法原位形成之,以进一步简化制程步骤并缩短制造时间。
不含氮的氧化硅薄层106的折射率在1.4到1.7的范围而较佳的范围在1.4到1.5。再者,不含氮的氧化硅薄层106的消光系数0到0.5的范围。此处,不含氮的氧化硅薄层106是作为一保护层,避免在以电浆剥除光阻图案层期间损坏下方的抗反射层104。
接着,藉由现有制程,例如旋转涂布法,在不含氮的氧化硅薄层106上方形成一能量敏感层108,例如一正型或负型光阻材料层,再接着烘烤此光阻层108。
接下来,请参照图1b,藉由现有微影制程图案化光阻层108以形成具有任何预定图案的光阻图案层108a。接着,检测光阻图案层108a中的图案是否正确。举例而言,藉由显影后检视(after development inspection,ADI)程序决定光阻图案层108a中的线宽或是线距是否符合规格。若线宽或线距符合规格,则进行后续制程以继续制造半导体装置。
相反地,若线宽或线距不符合规格,则光阻图案层108a必须去除以进行光阻重做。接着,请参照图1c中,可藉由含氧电浆110剥除具有非预定图案的光阻图案层108a。
图1d是绘示出完全去除光阻图案层108a之后的结构。在剥除期间,下方未被光阻图案层108a覆盖的抗反射结构部分可能会受到损害。举例而言,未完全氧化的抗反射材料会与含氧电浆发生反应,改变其原有的光学特性,例如折射率及消光系数,使抗反射结构失去作用。在本实施例中,抗反射层104上方的不含氮的氧化硅层106是作为一保护层,防止电浆中的氧原子与抗反射层104发生反应。因此,下方未受损害的抗反射层104可维持其原有的折射率及消光系数,藉以改善微影制程的品质。
接下来,请参照图1e,藉由现有制程在不含氮的氧化硅薄层106上方形成另一能量敏感层112,例如一正型或负型光阻材料层。
最后,请参照图1f,藉由微影制程图案化能量敏感层112以形成一具有预定图案的光阻图案层112a。
再者,请参照图1d,其亦绘示出一半导体装置,用以防止去除光阻期间损坏抗反射结构,其包括一基底100,其上具有一待定义层102。一不含氮的介电抗反射结构104是设置于待定义层102上方。再者,一不含氮的氧化硅薄层106是设置于不含氮的介电抗反射结构104上方以作为一保护层,其折射率在1.4到1.7的范围且其消光系数在0到0.5的范围。不含氮的氧化硅薄层106可为一二氧化硅层或是碳氧化硅层且其厚度在10到500埃的范围。较佳地,不含氮的氧化硅薄层106的厚度约在50埃。再者,不含氮的氧化硅薄层106可藉由现有沉积技术形成之,例如电浆增强化学气相沉积。
根据本实用新型,由于抗反射层可受到上方氧化硅层的保护而免于电浆的损害,因此可维持抗反射层的光学特性而提升微影制程的品质,藉以增加后续蚀刻制程的品质。
虽然本实用新型已以较佳实施例揭露如上,然其并非用以限定本实用新型,任何熟习此技艺者,在不脱离本实用新型的精神和范围内,当可作些许的更动与润饰,因此本实用新型的保护范围当视所附的权利要求范围所界定者为准。
Claims (7)
1.一种半导体装置,适用于防止去除光阻期间损坏抗反射结构,其特征在于,包括:
一不含氮的介电抗反射结构,设置于一基底上方;以及
一不含氮的氧化硅层,设置于该不含氮的介电抗反射结构上方,用以作为一保护层,且其折射率在1.4到1.7的范围。
2.根据权利要求1所述的半导体装置,其特征在于,该不含氮的氧化硅层的消光系数在0到0.5的范围。
3.根据权利要求1所述的半导体装置,其特征在于,该不含氮的氧化硅层是一二氧化硅层。
4.根据权利要求1所述的半导体装置,其特征在于,该不含氮的氧化硅层是一碳氧化硅层。
5.根据权利要求1所述的半导体装置,其特征在于,该不含氮的氧化硅层的厚度在10到500埃的范围。
6.根据权利要求1所述的半导体装置,其特征在于,该抗反射结构不含氮。
7.根据权利要求1所述的半导体装置,其特征在于,该抗反射结构至少包含一氮氧化硅层。
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US10/618,527 | 2003-07-11 | ||
US10/618,527 US20050009373A1 (en) | 2003-07-11 | 2003-07-11 | Semiconductor device and method for preventing damage to anti-reflective structure during removing an overlying photoresist layer |
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CN109219584A (zh) * | 2017-05-09 | 2019-01-15 | 法国圣戈班玻璃厂 | 具有导电涂层和减小的指纹可见性的玻璃板 |
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US20070004193A1 (en) * | 2005-07-01 | 2007-01-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for reworking low-k dual damascene photo resist |
CA2658210A1 (en) * | 2008-04-04 | 2009-10-04 | Sulzer Metco Ag | Method and apparatus for the coating and for the surface treatment of substrates by means of a plasma beam |
KR100995829B1 (ko) * | 2008-09-16 | 2010-11-23 | 주식회사 동부하이텍 | 반도체 소자 및 그의 제조방법 |
US7960835B2 (en) * | 2009-05-04 | 2011-06-14 | Macronix International Co., Ltd. | Fabrication of metal film stacks having improved bottom critical dimension |
CN102446808B (zh) * | 2011-09-23 | 2014-02-05 | 上海华力微电子有限公司 | 一种提高浅沟隔离多次曝光稳定性的方法 |
CN103137435B (zh) * | 2011-11-25 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | 介电抗反射涂层的形成方法及光刻方法 |
CN103928388A (zh) * | 2013-01-10 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其制造方法 |
US11522091B2 (en) * | 2016-01-27 | 2022-12-06 | Shangrao Jinko Solar Technology Development Co., Ltd | Solar cell |
CN108666208A (zh) * | 2017-03-30 | 2018-10-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
CN110890376B (zh) * | 2018-09-11 | 2022-08-02 | 长鑫存储技术有限公司 | 半导体器件的制备方法 |
CN112201569A (zh) * | 2020-09-10 | 2021-01-08 | 上海华力集成电路制造有限公司 | 光刻返工方法 |
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EP1115160A4 (en) * | 1998-08-26 | 2006-01-04 | Nippon Sheet Glass Co Ltd | PHOTOVOLTAIC DEVICE |
US6093973A (en) * | 1998-09-30 | 2000-07-25 | Advanced Micro Devices, Inc. | Hard mask for metal patterning |
US6232002B1 (en) * | 1998-11-06 | 2001-05-15 | Advanced Micro Devices, Inc. | Bilayer anti-reflective coating and etch hard mask |
US6191046B1 (en) * | 1999-03-11 | 2001-02-20 | Advanced Micro Devices, Inc. | Deposition of an oxide layer to facilitate photoresist rework on polygate layer |
US6057218A (en) * | 1999-05-07 | 2000-05-02 | Vanguard International Semiconductor Corporation | Method for simultaneously manufacturing poly gate and polycide gate |
KR100304708B1 (ko) * | 1999-07-14 | 2001-11-01 | 윤종용 | 이중층 반사방지막을 갖는 반도체소자 및 그 제조방법 |
US6174797B1 (en) * | 1999-11-08 | 2001-01-16 | Taiwan Semiconductor Manufacturing Company | Silicon oxide dielectric material with excess silicon as diffusion barrier layer |
US6174818B1 (en) * | 1999-11-19 | 2001-01-16 | Taiwan Semiconductor Manufacturing Company | Method of patterning narrow gate electrode |
US6376392B1 (en) * | 2001-05-18 | 2002-04-23 | Industrial Technology Research Institute | PECVD process for ULSI ARL |
US6720251B1 (en) * | 2001-06-28 | 2004-04-13 | Novellus Systems, Inc. | Applications and methods of making nitrogen-free anti-reflective layers for semiconductor processing |
US6656837B2 (en) * | 2001-10-11 | 2003-12-02 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
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CN109219584A (zh) * | 2017-05-09 | 2019-01-15 | 法国圣戈班玻璃厂 | 具有导电涂层和减小的指纹可见性的玻璃板 |
CN109219584B (zh) * | 2017-05-09 | 2022-04-12 | 法国圣戈班玻璃厂 | 具有导电涂层和减小的指纹可见性的玻璃板 |
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US20050009373A1 (en) | 2005-01-13 |
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