CN2727968Y - 层叠晶片结构 - Google Patents

层叠晶片结构 Download PDF

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CN2727968Y
CN2727968Y CNU2004200125297U CN200420012529U CN2727968Y CN 2727968 Y CN2727968 Y CN 2727968Y CN U2004200125297 U CNU2004200125297 U CN U2004200125297U CN 200420012529 U CN200420012529 U CN 200420012529U CN 2727968 Y CN2727968 Y CN 2727968Y
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资重兴
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Liang Xiwei
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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Abstract

本实用新型公开了一种层叠晶片结构，其由至少二个分别固装有一导线架的晶片及复数锡球所组成，其特征在于，晶片固装有导线架，该导线架具有数个形成排列的外电性引脚，各外电性引脚的外端凸设于晶片外部，晶片由外电性引脚与外界电子元件作电性连结；一晶片于其导线架的外电性引脚的外端上设有至少一锡球，另一晶片以其导线架的外电性引脚外端架设于该锡球上，二晶片以导线架的外电性引脚及锡球构成电性连结，以组成晶片层叠的结构，本实用新型藉由晶片外部电性连结结构，组成一种可任意叠置组装的层叠晶片，实现了层叠制程简易、可任意更换层叠数量、缩减占用面积，以及增进效率的效益。

Description

层叠晶片结构
技术领域
本实用新型涉及一种层叠晶片结构，特别涉及一种可缩减占用面积、增进效率的层叠晶片结构改良。
背景技术
请参阅图5所示，为一种传统的晶片封装结构，其主要是令半导体晶片10黏固于一具有复数引脚201的导线架20上，藉此于该晶片10的复数接点与导线架20之复数引脚201间，分别连接设有一电性连结的金属线30，使该晶片10可由导线架20的复数引脚201与外界电性连结，并于该晶片10外围实施有一密封包覆的绝缘性封胶体40，即可组成晶体提供电子产业利用；但是，其一导线架20单纯设有一晶片10的封装结构，无法在有限空间中增进该晶片10的运算效率，如特定电子产品需求庞大功能时，往往需要使用多数晶体，因而增加其成本，且无法达成精巧化电子产品设计趋势。
其后改良的晶片封装结构，请参阅图6所示，是将一晶片10黏固于一具有复数引脚201的导线架20后，实施有上述电性连结的金属线30，再于该晶片10上设有一支架50，藉此于支架50上另设一晶片10’，而再于该晶片10’与导线架20间实施有另一电性连结的金属线30’，藉此再于二晶片10、10’外实施有一密封包覆的绝缘性封胶体40，组成晶片层叠的晶体结构；但是，该层叠结构大幅改变金属线30的制程，往往因为电路设计变化，必须一再更动其制程，故有制程管理及质量管理上的困难，且无法任意随着实际需求而增加其晶片层叠数量，因此，对于该晶体效率的提升仍属有限。
实用新型内容
本实用新型的目的是要解决习知的晶片封装结构无法在有限空间中增进晶片的运算效率及金属线的制程变更频繁的问题，而提供一种可克服上述缺点的层叠晶片结构。
本实用新型是由至少二个分别固装有一导线架的晶片及复数锡球所组成，其特征在于，晶片固装有导线架，该导线架具有数个形成排列的外电性引脚，各外电性引脚的外端凸设于晶片外部，晶片由外电性引脚与外界电子元件作电性连结；一晶片于其导线架的外电性引脚的外端上设有至少一锡球，另一晶片以其导线架的外电性引脚外端架设于该锡球上，二晶片以导线架的外电性引脚及锡球构成电性连结，以组成晶片层叠的结构。
所述的晶片分别在外围设有一密封包覆的封胶体。
所述的晶片设有金属线连接于晶片及导线架各外电性引脚，并于金属线连接处设有一形成局部封装的封胶体。
所述的晶片在构成层叠结构后，再于外部设有共同封装晶片的封胶体。
本实用新型藉由晶片外部电性连结结构，组成一种可任意叠置组装的层叠晶片，实现了层叠制程简易、可任意更换层叠数量、缩减占用面积，以及增进效率的效益。
附图说明
图1为本实用新型的剖视示意图。
图2为本实用新型的立体示意图。
图3为本实用新型层置多晶片结构及另一种封胶体实施例的示意图。
图4为本实用新型层置多晶片结构及另一种封胶体实施例的示意图。
图5为习见单晶片封装结构的剖视示意图。
图6为习见层叠晶片封装结构的剖视示意图。
具体实施方式
请参阅图1、图2所示，本实用新型是由至少二个分别固装有一导线架2的晶片1及复数锡球3所组成，其中，晶片1是设有集成电路电子元件的半导体晶片，晶片1的选定面固装有一导线架2，该导线架2具有数个形成二排或矩阵排列的外电性引脚21，各外电性引脚21内端211供晶片1置设，而外电性引脚21的外端212凸设于晶片1二侧或周围，使晶片1可由外电性引脚21与外界电子元件作电性连结，例如在晶片1及外电性引脚21间设有相连接的金属线5，如图3所示。
藉此，一晶片1于其导线架2的外电性引脚21的外端212上设有至少一锡球3，并使另一晶片1以其导线架2的外电性引脚21外端212架设于该锡球3上，并可使二晶片1相黏固，使二晶片1间藉由导线架2的外电性引脚21及锡球3构成电性连结，以组成晶片层叠的结构，可提供电子产业使用。
如上所述，本实用新型令二晶片1藉外部导线架2的外电性引脚21组成层叠结构，其中各晶片1外围可实施有一密封包覆的封胶体4，如图1所示，使各晶片1获得保护作用。如图3所示，本实用新型的晶片1也可在设有金属线5连接于晶片1及导线架2各外电性引脚21处，并于金属线5连接处形成有一局部封装的封胶体4’，也可达成上述层叠实施结构。又如图4所示，本实用新型也可在至少二晶片1以外部导线架2的外电性引脚21及锡球3构成层叠结构后，再共同于晶片1外部实施有全面封装的封胶体4a，以组成晶片1层叠及具有保护作用的晶体。
本实用新型由于是以外部导线架2的外电性引脚21及锡球3组成层叠结构，故能使晶片1固装于导线架2上，以及实施有金属线5连接的制程，事先各别进行以方便管理，且可使各晶片1分别依其电路设计实施不同连接状态的金属线5，再进行层叠组合，改善前述习知晶片层叠结构需改变金属线连接状态，以及达成制程需因晶片层叠改变的麻烦，故可获得制程简易实施效果。其次，本实用新型各晶片1可在各别固设于导线架2上并实施有金属线5连接后，再透过导线架2的外电性引脚21及锡球3组成层叠结构，故可任意依需求而实施三晶片或更多晶片层叠结构，其实施多层层叠结构时，仅需依电路设计而于选定的外电性引脚21间设有锡球3，即可轻易达成，也能改善前述习知晶片层叠结构不易变化实施多层结构的缺点。另外，本实用新型均可获得缩减占用面积，以及增进效率等效益，以提供现今精巧化及功能强大的电子产品使用。

Claims (4)

1、一种层叠晶片结构，其是由至少二个分别固装有一导线架的晶片及复数锡球所组成，其特征在于：晶片固装有导线架，该导线架具有数个形成排列的外电性引脚，各外电性引脚的外端凸设于晶片外部，晶片由外电性引脚与外界电子元件作电性连结；一晶片于其导线架的外电性引脚的外端上设有至少一锡球，另一晶片以其导线架的外电性引脚外端架设于该锡球上，二晶片以导线架的外电性引脚及锡球构成电性连结。
2、根据权利要求1所述的一种层叠晶片结构，其特征在于：所述的晶片分别在外围设有一密封包覆的封胶体。
3、根据权利要求1所述的一种层叠晶片结构，其特征在于：所述的晶片设有金属线连接于晶片及导线架各外电性引脚，并于金属线连接处设有一形成局部封装的封胶体。
4、根据权利要求1所述的一种层叠晶片结构，其特征在于：所述的晶片在构成层叠结构后，再于外部设有共同封装晶片的封胶体。
CNU2004200125297U 2004-09-23 2004-09-23 层叠晶片结构 Expired - Fee Related CN2727968Y (zh)

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