CN102185470A - 具有双面冷却及电磁干扰屏蔽功能的夹层结构 - Google Patents

具有双面冷却及电磁干扰屏蔽功能的夹层结构 Download PDF

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CN102185470A
CN102185470A CN2011100485668A CN201110048566A CN102185470A CN 102185470 A CN102185470 A CN 102185470A CN 2011100485668 A CN2011100485668 A CN 2011100485668A CN 201110048566 A CN201110048566 A CN 201110048566A CN 102185470 A CN102185470 A CN 102185470A
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CN102185470B (zh
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印健
蒋航
姚凯卫
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Chengdu Monolithic Power Systems Co Ltd
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Abstract

本发明提出了一种对微型组件进行双面冷却、屏蔽电磁干扰以及载流的新型夹层结构及其方法。所述夹层结构包括顶层结构和底层结构以达到双面冷却的目的。同时，顶层结构还用于屏蔽电磁干扰。所述夹层结构还包括第一组连接结构以用于将微型组件中的器件和顶层结构连接起来，以及第二组连接结构以用于将顶层结构和底层结构连接起来。所述连接结构具有载流功能。利用本发明实施例，可以实现微型组件的双面冷却，提高了微型组件的散热能力，并且减小了微型组件的功率耗散和提高了微型组件的抗电磁干扰能力。

Description

具有双面冷却及电磁干扰屏蔽功能的夹层结构
技术领域
本发明的实施例涉及一种微型组件，更具体地，涉及一种在微型组件中用于热冷却和EMI屏蔽的夹层结构。
背景技术
当今，微型组件由于具有小尺寸、低功耗等优点而发展迅速。目前，微型组件的封装形式主要采用引线键合技术。然而，由于引线键合技术中键合引线较长，引线阻抗较大，使得微型组件的功率损耗增大，效率降低。这限制了承载大电流的能力。而且，由于键合引线较细，将产生寄生电感，使得微型组件中的开关在切换时将产生振荡环路，而振荡环路的产生将使得电路中产生额外的损耗以及产生电磁干扰(electromagnetic interference，EMI)噪声。另外，引线键合技术只能将微型组件产生的热量从底面散发出去，因此，其散热能力较差。随着现今负载电流越来越大，对组件散热能力的要求越来越高，引线键合技术已不再是微型组件的优选封装形式。
因此，需要一种新型的封装结构，以减小微型组件中的功率损耗及电磁干扰，并能提高其散热能力。
发明内容
针对现有技术中的一个或多个问题，本发明的一个目的是提供一种用于微型组件的夹层结构和方法。
在本发明的一个方面，本发明的实施例提供了一种用于微型组件的夹层结构，所述夹层结构包括：
顶层结构，所述顶层结构用于热冷却、电磁干扰屏蔽以及载流，其中，所述顶层结构具有顶面和底面；
底层结构，所述底层结构用于热冷却、载流以及电路控制，其中，所述底层结构具有顶面和底面；
内部组件，其中，所述内部组件包括第一组组件，第一组组件包括一个或多个组件，且其中，每个组件的第一面均安装在所述底层结构的顶面上；
第一组连接结构，其中，第一组连接结构包括一个或多个连接结构，所述第一组连接结构中的每一个连接结构均用于将第一组组件中的每个组件连接至所述顶层结构的底面；
第二组连接结构，其中，第二组连接结构包括一个或多个连接结构，所述第二组连接结构连接于所述顶层结构的底面和所述底层结构的顶面之间，用于为所述内部组件提供一条或多条电流通道。
在本发明的另一个方面，本发明的实施例提供了一种用于冷却微型组件、屏蔽微型组件电磁干扰以及载流的的方法，包括：
在底层结构的顶面上安装第一组组件，其中，第一组组件包括一个或多个组件，所述底层结构用于热冷却、载流以及电路控制；
将第一组连接结构中的每一个的第一面连接至顶层结构，其中，第一组连接结构包括一个或多个连接结构，所述顶层结构用于热冷却、电磁干扰屏蔽以及载流；
将第二组连接结构中的每一个的第一面连接至所述顶层结构的底面，其中，第二组连接结构包括一个或多个连接结构，所述第二组连接结构用于为微型组件提供一条或多条电流通道；
将第一组连接结构中的每一个的第二面分别连接至第一组组件中每一个组件；以及
将第二组连接结构中的每一个的第二面连接至所述底层结构的顶面。
利用本发明实施例，可以实现微型组件的双面冷却，提高了微型组件的散热能力，并且减小了微型组件的功率耗散和提高了微型组件的抗电磁干扰能力。
附图说明
图1示出一典型的直流/直流(DC/DC)降压转换器电路10。
图2A示出根据本发明一实施例的实现图1所示DC/DC降压转换器电路10的微型组件结构的侧视图。
图2B示出根据本发明一实施例的实现图1所示DC/DC降压转换器结构10的微型组件结构的俯视图。
图3示出根据本发明另一实施例的微型组件结构的侧视图。
图4示出根据本发明另一实施例的微型组件结构的侧视图。
具体实施方式
下面详细说明本发明实施例的用于微型组件的夹层结构。在接下来的说明中，一些具体的细节，都用于对本发明的实施例提供更好的理解。本技术领域的技术人员可以理解，即使在缺少一些细节或者其他方法、元件、材料等结合的情况下，本发明的实施例也可以被实现。
图1示出一典型的直流/直流(DC/DC)降压转换器电路10。如图1所示，电路10包含一控制器，其耦接至一上管FET1以及一下管FET2的栅极。上管FET1的漏极耦接至输入端VIN，其源极耦接至下管FET2的漏极。下管FET2的源极耦接至地。电感L的一端耦接至上管FET1和下管FET2的公共端，其另一端耦接至输出端VOUT。在本实施例中，控制器和上管FET1集成于同一芯片101中。
图2A和图2B示出根据本发明一实施例的实现图1所示DC/DC降压转换器电路10的新型夹层结构。如图2A和2B所示，芯片101通过倒装焊技术安装在位于底面的衬底上，以使得芯片101的正面为地，其反面通过例如焊锡膏等导电胶附着在衬底上。下管FET2和电感L亦通过导电胶安装在衬底上。所述安装工艺可以通过传统的常规回流工艺实现。
金属通孔A和C分别用于将芯片101和下管FET2连接至位于顶面的金属引线框，所述金属引线框通过银环氧树脂或者焊锡膏与微型组件的各个器件连接，且所述金属引线框覆盖住微型组件的所有器件。由于存在金属通孔A和C，芯片101和下管FET2产生的热量不仅能够通过传统方法从衬底散发出去，还能够通过金属通孔A和C从金属引线框散发出去，即利用金属通孔实现了微型组件的双面冷却。而金属引线框作为功率地屏蔽层，能够阻挡EMI噪声。图2A和图2B中的衬底可以是具有不同类型芯材(core material)的印刷电路板(PCB)，或者是金属薄膜。金属引线框和衬底均可以用于载流或作为控制信号走线。金属通孔B直接连接于金属引线框和衬底之间，以将金属引线框的的功率地和衬底地连接起来。金属通孔B代替了传统引线键合连接，以提供一从下管FET2至衬底的电流通道用于载流。
在另一实施例中，金属通孔B可以用于在金属引线框和衬底之间传输信号或者载流。
在一个实施例中，金属引线框可以是平板或密封罩，并完全覆盖微型组件。
在一个实施例中，在金属引线框上可以具有多个开孔。
在一个实施例中，当金属引线框为平板时，在微型组件的空隙中填充绝缘材料。具体而言，可以通过金属引线框上的开孔向微型组件注入模具复合材料，这样形成的封装较坚固。在微型组件中注入模具复合材料还能起到电绝缘的作用。模具复合材料可以为硅树脂(silicone)。另外，所述开孔还能减小涡流，因而更有效地提高电磁屏蔽效果。
电感L通过银环氧树脂与金属引线框连接，可以帮助微型组件散热，进而提高效率。
虽然示出了3个金属通孔A、B和C作为连接结构的示例，但是本发明中连接结构的数目不限于该具体示例，在实际中可以根据应用需求采用任何适合数目的连接结构。
图3示出依据本发明另一实施例的改进的夹层结构。如图3所示，与图2A和2B所示的结构相比，微型组件的内部组件D1和D2分别通过第一组金属通孔D和第二组金属通孔E连接至金属引线框。采用多个小通孔的连接方式能够减小内部组件的热应力，且多个小通孔一起所承受的热应力亦小于一个金属通孔所承受的热应力，并能够避免内部组件D1和D2被压碎。
虽然示出了2个内部组件D1和D2作为内部组件的示例，但是本发明中内部组件的数目不限于该具体示例，在实际中可以根据应用需求采用任何适合数目的内部组件。
图4示出根据本发明另一实施例的一种改进的夹层结构。如图4所示，和图2A和图2B所示的结构相比，金属引线框被制造成只有底面开口的密封罩结构。所述密封罩通过银环氧树脂或者焊锡膏连接至衬底，并完全罩住整个微型组件。该结构不再需要模具复合材料，因而节省了成本。另外，密封罩防止了微型组件的侧边磁泄露，因而提高了EMI屏蔽效果。而且，图4所示的结构通过将金属引线框和衬底直接连接，还提供了额外的热路径用于为微型组件散热，因而提高了微型组件的热性能。
上述本发明的说明书和实施方式仅仅以示例性的方式对本发明实施例的用于微型组件的夹层结构及其方法进行了说明，并不用于限定本发明的范围。对于公开的实施例进行变化和修改都是可能的，其他可行的选择性实施例和对实施例中元件的等同变化可以被本技术领域的普通技术人员所了解。本发明所公开的实施例的其他变化和修改并不超出本发明的精神和保护范围。

Claims (15)

1.一种用于微型组件的夹层结构，其特征在于，所述夹层结构包括：
顶层结构，所述顶层结构用于热冷却、电磁干扰屏蔽以及载流，其中，所述顶层结构具有顶面和底面；
底层结构，所述底层结构用于热冷却、载流以及电路控制，其中，所述底层结构具有顶面和底面；
内部组件，其中，所述内部组件包括第一组组件，第一组组件包括一个或多个组件，且其中，每个组件的第一面均安装在所述底层结构的顶面上；
第一组连接结构，其中，第一组连接结构包括一个或多个连接结构，所述第一组连接结构中的每一个连接结构均用于将第一组组件中的每个组件连接至所述顶层结构的底面；
第二组连接结构，其中，第二组连接结构包括一个或多个连接结构，所述第二组连接结构连接于所述顶层结构的底面和所述底层结构的顶面之间，用于为所述内部组件提供一条或多条电流通道。
2.如权利要求1所述的夹层结构，其特征在于，所述第一组和第二组连接结构中的每一个连接结构包含一个或多个金属通孔。
3.如权利要求1所述的夹层结构，其特征在于，所述顶层结构和底层结构为衬底或金属引线框。
4.如权利要求1所述的夹层结构，其特征在于，所述第一组和第二组连接结构的第一面通过导电胶连接至所述顶层结构的底面，所述第一组连接结构的第二面通过导电胶连接至所述第一组组件，所述第二组连接结构通过导电胶连接至所述底层结构的顶面。
5.如权利要求1所述的夹层结构，其特征在于，所述顶层结构为平板或密封罩，所述顶层结构完全覆盖所述微型组件。
6.如权利要求1所述的夹层结构，其特征在于，所述顶层结构具有开孔。
7.如权利要求6所述的夹层结构，其特征在于，当所述顶层结构为平板时，微型组件的空隙中填充有绝缘材料。
8.如权利要求1所述的夹层结构，其特征在于，所述内部组件还包括第二组组件，所述第二组组件通过导电胶连接至所述顶层结构的底面或所述底层结构的顶面。
9.如权利要求8所述的夹层结构，其特征在于，所述第二组组件中的每一个组件的第一面安装在所述底层结构的顶面上，所述第二组组件中的每一个组件的第二面通过导电胶连接至所述顶层结构。
10.如权利要求1所述的夹层结构，其特征在于，所述夹层结构还包括安装在所述顶层结构的顶面上的第三组组件，第三组组件包括一个或多个组件。
11.一种用于冷却微型组件、屏蔽微型组件电磁干扰以及载流的方法，包括：
在底层结构的顶面上安装第一组组件，其中，第一组组件包括一个或多个组件，所述底层结构用于热冷却、载流以及电路控制；
将第一组连接结构中每一个连接结构的第一面连接至顶层结构的底面，其中，第一组连接结构包括一个或多个连接结构，所述顶层结构用于热冷却、电磁干扰屏蔽以及载流；
将第二组连接结构中每一个连接结构的第一面连接至所述顶层结构的底面，其中，第二组连接结构包括一个或多个连接结构，所述第二组连接结构用于为微型组件提供一条或多条电流通道；
将第一组连接结构中每一个连接结构的第二面分别连接至第一组组件中每一个组件；以及
将第二组连接结构中每一个连接结构的第二面连接至所述底层结构的顶面。
12.如权利要求11述的方法，其特征在于，所述方法还包括：将第二组组件每一个组件的第一面连接至所述底层结构的顶面，或者将第二组组件中每一个组件的第二面连接至所述顶层结构的底面。
13.如权利要求11所述的方法，其特征在于，所述方法还包括：在所述顶层结构的顶面上安装第三组组件，第三组组件包括一个或多个组件。
14.如权利要求11所述的方法，其特征在于，所述方法还包括：在所述顶层结构上开孔。
15.如权利要求11所述的方法，其特征在于其中，所述顶层结构为平板或者密封罩，且所述平板或密封罩完全覆盖所述微型组件，
其中，所述方法还包括：当所述顶层结构为平板时，在所述微型组件的空隙中填充绝缘材料。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990318A (zh) * 2015-03-23 2016-10-05 日月光半导体制造股份有限公司 半导体装置封装和其制造方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9093903B2 (en) 2011-09-28 2015-07-28 Monolithic Power Systems, Inc. Power converter with voltage window and the method thereof
KR20140115668A (ko) 2013-03-21 2014-10-01 삼성전자주식회사 방열판과 수동 소자를 갖는 반도체 패키지
US12002613B2 (en) 2019-11-22 2024-06-04 Toyota Motor Engineering & Manufacturing North America, Inc. Double-sided cooling package of inductor
US11594497B2 (en) * 2021-03-31 2023-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Electromagnetic shielding structure for a semiconductor device and a method for manufacturing the same
US11716806B1 (en) 2021-11-18 2023-08-01 Motorola Mobility Llc Processor heat dissipation in a stacked PCB configuration

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201355635Y (zh) * 2009-01-16 2009-12-02 深圳市航嘉驰源电气股份有限公司 开关电源dc线
US20100027228A1 (en) * 2008-07-31 2010-02-04 Ibiden Co., Ltd. Semiconductor device and method for manufacturing the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5886408A (en) * 1994-09-08 1999-03-23 Fujitsu Limited Multi-chip semiconductor device
US6304450B1 (en) * 1999-07-15 2001-10-16 Incep Technologies, Inc. Inter-circuit encapsulated packaging
JP3881488B2 (ja) * 1999-12-13 2007-02-14 株式会社東芝 回路モジュールの冷却装置およびこの冷却装置を有する電子機器
US6724631B2 (en) * 2002-04-22 2004-04-20 Delta Electronics Inc. Power converter package with enhanced thermal management
US7129577B2 (en) * 2003-02-27 2006-10-31 Power-One, Inc. Power supply packaging system
US7880282B2 (en) * 2003-12-18 2011-02-01 Rf Module & Optical Design Ltd. Semiconductor package with integrated heatsink and electromagnetic shield
US7119432B2 (en) * 2004-04-07 2006-10-10 Lsi Logic Corporation Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package
US7345885B2 (en) * 2004-12-22 2008-03-18 Hewlett-Packard Development Company, L.P. Heat spreader with multiple stacked printed circuit boards
JP5259059B2 (ja) * 2006-07-04 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
US7999369B2 (en) * 2006-08-29 2011-08-16 Denso Corporation Power electronic package having two substrates with multiple semiconductor chips and electronic components
US7646093B2 (en) * 2006-12-20 2010-01-12 Intel Corporation Thermal management of dies on a secondary side of a package
DE102008058003B4 (de) * 2008-11-19 2012-04-05 Infineon Technologies Ag Verfahren zur Herstellung eines Halbleitermoduls und Halbleitermodul

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100027228A1 (en) * 2008-07-31 2010-02-04 Ibiden Co., Ltd. Semiconductor device and method for manufacturing the same
CN201355635Y (zh) * 2009-01-16 2009-12-02 深圳市航嘉驰源电气股份有限公司 开关电源dc线

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105990318A (zh) * 2015-03-23 2016-10-05 日月光半导体制造股份有限公司 半导体装置封装和其制造方法

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