CN100414697C - 在基板栅格阵列封装中应用的dc-dc转换器 - Google Patents

在基板栅格阵列封装中应用的dc-dc转换器 Download PDF

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CN100414697C
CN100414697C CNB2004800001494A CN200480000149A CN100414697C CN 100414697 C CN100414697 C CN 100414697C CN B2004800001494 A CNB2004800001494 A CN B2004800001494A CN 200480000149 A CN200480000149 A CN 200480000149A CN 100414697 C CN100414697 C CN 100414697C
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CN1739197A (zh
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米索·P.·迪瓦卡
戴维·凯廷
安托恩·卢塞尔
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Abstract

一种半导体芯片封装，包括按照用于互连的基板栅格阵列即LGA封装应用并表面安装到印刷电路板上的DC-DC转换器。LGA封装集成了DC-DC电源转换器的所有必需的有源器件，包括同步降压PWM控制器、驱动电路和MOSFET器件。具体地，LGA封装包括具有顶表面和底表面的衬底，衬底上有DC-DC转换器。DC-DC转换器至少包括一个布置在衬底顶表面上的功率硅管芯。衬底的底表面上存在多个电和热传导焊盘，它们通过各自导电通路与DC-DC转换器进行电连接。多个焊盘包括具有第一表面区域的第一焊盘和具有第二表面区域的第二焊盘，第二表面区域基本上大于第一表面区域。DC-DC转换器产生的热通过多个焊盘传到LGA封装的外部。

Description

在基板栅格阵列封装中应用的DC-DC转换器
技术领域
本发明一般涉及使用微电子器件实现的电源。更具体地，本发明的实施方式将高电流降压调节器集成到基板栅格阵列(LGA)封装内，以满足在最小区域内封装板层分布电源结构的电和热需求。
背景技术
电子系统面临进一步的尺寸减小、器件密度以及更重要的电源密度的极大挑战。为了应对这些挑战，许多障碍需要克服。有效的热散失以及与低电阻和低电感的互连相联系的管理，结合提供低成本封装的需要，仅仅是许多障碍中的一些。
传统的功率半导体封装或管芯包括一个或多个功率半导体管芯。功率半导体管芯，例如电源MOSFET，具有限定漏极接点或电极的底表面和包括限定源极接点或电极的第一金属化区域和限定栅极接点或电极的第二金属化区域的顶表面。通常，每个功率半导体管芯与外部焊盘进行电和热连接。
目前，市场上已经存在包括DC-DC转换器的功率半导体封装或管芯。通常，该产品封装在不容易容纳大量分立无源器件的微型引线框(MLF)内。因此，分立无源器件必须位于外部，这减小了封装在尺寸减小方面的可行性。例如，电路(如升压电路)和补偿器件常常位于产品的外部并消耗额外的板空间。
DC-DC转换器需要大量有源和无源器件。传统的DC-DC转换器需要功率MOSEFETs、控制集成电路(IC’s)、设定PWM控制器操作的器件、反馈补偿器件、电容过滤元件、充电泵器件以及电源级滤波器LC(电感和电容)器件。某些情况下，DC-DC转换器可能由多达30个器件组成。这些单独安置的器件占据了印刷电路板(PCB)上的大量空间。这些器件需要细心设计和迹线布线以避免产生漏电感，漏电感可能导致使用性能差，或在某些情况下，可能导致器件失效。
希望减少大量器件需要的板空间、将这些器件组合为高密度的、简单封装的部件，该部件容纳关键半导体器件及其相关器件作为DC-DC转换器的标准部件。由于尺寸因素以及使用输出电压可以获得这种滤波器的事实，希望不包括输出LC滤波器。希望这种简单的封装使漏电感最小，提供器件之间的高导电性互连，提供到外部互连点的高导电性低电感路径，并提供将转换器内部产生的热传到外部环境中的有效方法。还希望这种封装是低成本的。
发明内容
本发明涉及通过在LGA平台内封装DC-DC转换器而解决上述许多问题，为实现器件密度、整体封装尺寸减小和非常高的功率密度的结合提供机会。
本发明的一方面是将DC-DC转换器集成到LGA封装内。根据这个方面，功率半导体管芯、控制半导体管芯以及分立无源器件电和热连接在一起并装在衬底的顶表面以制成DC-DC转换器。封装的底部包括多个形成LGA的焊盘。全部的半导体管芯与各自的外部焊盘电和热连接。
特别地，LGA封装包含具有顶表面和底表面的衬底，衬底上有DC-DC转换器。DC-DC转换器至少包含一个布置在衬底顶表面上的功率硅管芯。衬底的底表面具有大量的热和电传导焊盘，这些焊盘通过各自的导电通路与DC-DC转换器电连接。大量的焊盘包括具有第一表面积的第一焊盘和具有第二表面积的第二焊盘，第二表面积基本上大于第一表面积。DC-DC转换器产生的热通过大量的焊盘传到LGA封装的外部。
更具体地，至少一个功率硅管芯与至少一个第二焊盘基本上对齐。第一焊盘基本上位于底表面的外围区域，第二焊盘基本上位于底表面的中间区域。作为选择，第一焊盘可以基本上位于底表面的第一侧，第二焊盘可以基本上位于底表面的第二侧。至少一个半导体管芯还可以包括第一对MOSFET器件，该器件与布置在底表面第一侧附近的第二焊盘中相应的第一对基本上对齐，而且第二对MOSFET器件与布置在底表面第二侧附近的第二焊盘中相应的第二对基本上对齐。
本发明的另一方面是提供热增强的衬底。在一个具体实施方式中，衬底包括多个高密度通路阵列。每个高密度通路阵列直接位于功率半导体管芯的下面。在更好的具体实施方式中，每个高密度通路阵列与功率半导体管芯和LGA的外部焊盘进行电和热连接。
本发明还有另一个方面就是在功率半导体管芯与LGA的外部焊盘之间提供低的电阻和热阻路径。一个具体实施方式中，衬底由两层组成，管芯表面和底表面。每个高密度通路阵列在管芯表面和底表面之间提供直接的电和热路径，衬底由多于两层组成，每层都包含管芯表面和底表面。
本发明的另一个方面是增加封装的散热特性。一个具体实施方式中，高密度通路阵列与每个半导体管芯电和热连接。高密度通路阵列使处于半导体管芯下面(功率半导体管芯的物理轮廓之内)的通路的总数量最优化。每个高密度通路阵列比传统通路阵列更有效地耗散半导体管芯产生的热。
附图说明
图1是本发明具体实施方式的顶面视图，说明基本的封装器件；
图2是本发明具体实施方式的顶面视图，说明器件之间的电互连；
图3是本发明具体实施方式的底面视图，说明LGA封装的插脚分配；
图4是本发明具体实施方式的示意图；
图5本发明具体实施方式的侧边剖面视图，说明功率半导体管芯与通路阵列电和热连接；
图6是根据现有技术的通路设计的顶面视图；
图7是本发明具体实施方式的顶面视图，说明高密度通路设计；
图8是本发明替代具体实施方式的示意图；和
图9是本发明替代具体实施方式的底面视图，说明LGA封装的插脚分配。
具体实施方式
一般地，本发明将DC-DC转换器集成到LGA封装内，以满足在最小区域内分布电源结构的封装层的电和热的需求。更具体地，本发明提供高效率的负荷点的DC-DC转换器，该转换器适合于以非常接近负荷的高电流传送低电压。LGA封装集成了DC-DC电源转换器的所有必需的有源器件，包括同步降压PWM控制器、驱动电路和MOSFET器件。
图1-2说明根据本发明一个方面的功能半导体封装100。功率半导体封装100包括，除其它的将在后面论述的器件之外，衬底102、第一功率半导体管芯104、第二功率半导体管芯106、第三半导体管芯108、第四半导体管芯1 10以及多个分立无源器件(例如电阻R1-R8和电容C1-C9)。在优选的实施方式中，四个半导体片104、106、108、110和分立无源器件电连接在一起以形成DC-DC转换器。装在衬底1 02上的分立无源器件的数量可以根据封装100的性能要求而不同。对于封装，只包含部分DC-DC转换器也在本发明的范围内。
衬底102最好是包括管芯表面112和底表面114的两层衬底(见图3)。衬底102也可以包括多层。衬底102包括分别由第一和第二隔离边界116、118以及前面和后面边界120、122限定的边缘。衬底102的管芯表面112包括有每个功率半导体管芯104、106和半导体管芯108、110安装在上面的管芯粘附焊盘以及用于安装每个分立无源器件的基板。铜线CT使不同的分立无源器件和四个半导体片104、106、108、110电连接。衬底102的底表面114(见图3)包括形成LGA的多个外部导电焊盘，它们为印刷电路板提供表面安装互连。
图2提供了管芯表面112和安装在该表面上的各种电路器件的更详细的说明。衬底102的表面112包括多个使基板和器件(例如半导体片、电容和电阻)安装在上面的焊盘(未示出)进行电连接的铜线CT。铜线CT也在第三半导体管芯108和分立无源器件之间提供电连接。例如，铜线CT1使半导体管芯108的插脚8电连接到分立无源器件电阻R1。本技术中在衬底102上制作铜线CT的方法是众所周知的，不需要过多的说明。
最好是由功率MOSFETs提供功率半导体片104、106。功率半导体片104(高侧MOSFET)和106(低侧MOSFET)的每个都包括第一金属化表面104a、106a(源极电极)，第二金属化表面104b、106b(栅极电极)以及相反的金属化表面104c、106c(漏极电极)。功率半导体片104、106的第一金属化表面104a、106a(源极电极)和第二金属化表面104b、106b(栅极电极)由大量的键合线128连接到衬底102的管芯表面112上的键合焊盘126。功率半导体管芯104、106的相反的金属化表面104c、106c(漏极电极)被安装到管芯粘附焊盘130(见图5)。最好是使用导热和/或导电的管芯插脚粘合剂132将功率半导体片104、106安装到管芯粘附焊盘130上。
第三半导体管芯108最好是为DC-DC转换器提供控制/驱动的集成电路(“IC”)。半导体管芯108粘合在衬底102的管芯表面112上，并安装在管芯焊盘130上。例如，半导体管芯108为第一和第二功率半导体片104、106提供栅极驱动。此外，为了调节第一和第二功率半导体片104、106的准时，半导体管芯108为第二金属化表面104b、106b提供了脉宽调制(“PWM”)控制。
第四半导体管芯110最好是二极管。与电容和电阻组合，第四半导体110包括为第一功率半导体管芯104的驱动提供升压的充电泵。
半导体片104、106、108、110和衬底102的管芯表面112上的分立无源器件的物理布置意在使LGA封装的效率最大化。第一和第二功率半导体管芯104、106最好是彼此靠近或相距最近以使两个器件之间的互连感应系数最小。第三半导体管芯108相对于第一和第二功率半导体片104、106的位置使漏电感相关的栅极驱动阻抗最小。
图4说明LGA封装100内DC-DC转换器的一个具体实施方式的电路图。如图4所示，DC-DC转换器包括用于将输入DC电压Vin转换为应用于阻抗负荷(未示出)的输出DC电压Vo的传统降压转换器布局。DC-DC转换器包括高侧MOSFET104、低侧MOSFET106以及由电感和电容提供的输出滤波器。高侧MOSFET104的漏极端子与输入电压Vin相连，低侧MOSFET106的源极端子接地，而且高侧MOSFET104的源极端子和低侧MOSFET106的漏极端子连在一起以设定相位节点。输出滤波器的电感串联在相位节点和提供输出电压Vo的端子之间，输出滤波器的电容与电阻负荷并联。第三半导体管芯108提供的控制器/驱动器包括脉宽调节(PWM)电路，该电路对用于控制MOSFETs104、106的启动时间的方波信号的占空比进行控制。通过适当的补偿网络将反映输出电压和/或电流的反馈信号提供到控制器/驱动器，以确定PWM信号的占空比。MOSFETs104、106的断开和闭合在相位节点上提供具有大体矩形波形的中间电压，由电感和电容形成的输出滤波器将矩形波转换为实质上的DC输出电压Vo。DC-DC转换器也可以包括过电流保护(OCP)网络和用于为PWM电路确定时钟频率的无源器件，与该技术中普遍知道的一样。
封装内升压电路器件的位置是本发明的另一个方面。升压电路使第一功率半导体管芯104的第一金属化表面104a相应的电压升高，升高的电压足以驱动第二金属化表面104b。漏电感可能使升压电压减小，因此，本发明通过将升压电路放入到封装内从而使电路内的漏电感最小。为了在器件打开时为第一和第二功率半导体片104、106相关的传导电流提供低阻抗路径，滤波器电容最好相对于第三半导体管芯108进行定位。
工作期间，封装产生的多数热量是由第一和第二功率半导体片104、106产生的。这些热必须被有效地从第一和第二功率半导体片104、106的反面104c、106c散失到LGA的外部焊盘P1-P23。由于LGA封装的尺寸小，希望LGA封装的最多热量散失是通过LGA封装所连接的主板。因此，有效的热量设计对于成功的操作是十分重要的。而且，关键的电路路径需要低的寄生阻抗以维持电路的性能。
由于放入到LGA封装内部的半导体管芯具有依赖于工作条件的功率消耗率，因此LGA封装的热阻参数是通过考虑DC-DC的全部工作条件而最优化确定的。对具有最关键温度的管芯，确定封装连接温度TJ、相关的热阻以及热学参数。在本DC-DC转换器应用中，多数的功率被高侧开关的MOSFET管芯104消耗，该管芯并不位于封装的中央。因此，封装温度值Tc定在相应于开关的MOSFET管芯104的部位，而且所有测量的和模拟的封装温度均参照该部位。通过保证该部位的温度TC不超出预定的最大值，LGA封装的全部其它器件也因此将各自保持在安全工作限度之内。
图3说明在衬底102底表面114上形成的LGA的最好具体实施方式。LGA一般分为两个区域——内部区域IR和周围区域PR。内部区域IR最好包含衬底底表面114的中心部分。周围区域PR围在内部区域IR的周围，限定底表面114上位于内部区域IR和衬底的四个侧边116、118、120、122之间的空间。对于LGA，包括外部的焊盘设计也在本发明的范围和宗旨之内。
内部区域包括外部的焊盘P21、P22和P23。周围区域包含外部焊盘P1-P20。如上面已经提及的，封装100想要在每个功率半导体管芯和外部焊盘之间提供低的热阻。外部焊盘P21、P22专用于半导体片104、106。因此，由于在封装内第一和第二功率半导体片104、106散失最多热量，在LGA内外部焊盘P21、P22是最大的焊盘。大的焊盘提供了与主板的低热阻和低电阻连接。在优选的具体实施方式中，外部焊盘P22完全直接位于第一功率半导体管芯104的下面。在包括两层衬底的具体实施方式中，大的输入焊盘P22和第一功率半导体管芯104上相对的金属化表面104c之间的间距短(例如，小于1mm)。短的间距在大的输入焊盘P22和相对的金属化表面104c之间提供低电感的路径。短的路径还包括具有低漏互连电感的高导电特性。图3中功率半导体管芯104的区域显示为虚线以说明功率半导体管芯104相关的外部焊盘P22的物理位置。外部焊盘P22这样放置结果使所有的相对的金属化表面104c都直接位于外部焊盘P22的上面。
大的输入焊盘P21完全直接位于第二功率半导体管芯106的下面。P21的位置提供了具有与外部焊盘P22和第一功率半导体管芯104之间路径相似电和热特性的路径。外部焊盘P21还提供到处于外部的输出滤波器(未示出)的高导电路径和从第二功率半导体管芯106上相对的金属化表面106c到封装外部环境的高导热路径。外部焊盘P1-P20专用于分立无源器件。功率半导体管芯106所占区域显示于图3中。外部焊盘P21的位置为，基本上全部的功率半导体管芯106直接位于外部焊盘P21的上面。较小部分的半导体管芯104、106分别直接位于外部焊盘P22、P22的上面也是在本发明的范围和宗旨之内。
优选的具体实施方式中，LGA封装至少提供下列的I/O焊盘组合：电源转换器使能、频率调整、输出电压调整、第二功率半导体管芯106的Vcc、过电流保护输入以及第一功率半导体管芯104的源极与第二半功率导体管芯106上相对的金属化表面106c的连接。在一个具体实施方式中，与外部焊盘设计相关的I/O插脚分配如下：
  插脚     功能   名称
  P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15P16P17P18P19P20P21P22P23     输入电压输入电压输入电压输入电压升压电流调整频率调节未连接使用者控制的开/关输出电压调节正电压检测未连接负电压检测负电压检测电源接地电源接地电源接地电源接地电源接地电源接地开关电压输入电压负电压检测   V<sub>IN</sub>V<sub>IN</sub>V<sub>IN</sub>V<sub>IN</sub>V<sub>BOOST</sub>OCPFreqN/CEnableTrim+VsN/C-Vs-VsP<sub>GND</sub>P<sub>GND</sub>P<sub>GND</sub>P<sub>GND</sub>P<sub>GND</sub>P<sub>GND</sub>V<sub>sw</sub>V<sub>IN</sub>-Vs
表1
图8说明LGA封装200内的DC-DC转换器的替代实施方式的电路图。不像图4的实施方式，该替代实施方式包括具有适合于并联操作的两对MOSFET管芯的DC-DC转换器。与该技术中普遍知道的一样，并联操作提供减少了电压起伏的输出电压Vo。
如图8中所示，DC-DC转换器包括高侧MOSFET204、212，低侧MOSFET206、214以及由并联电感和电容提供的输出滤波器。高侧MOSFET204的漏极端子连接到输入电压Vin，低侧MOSFET206的源极端子接地，而且高侧MOSFET204的源极端子和低侧MOSFET206的漏极端子连接在一起以设定第一相位节点。输出滤波器的第一电感串联在第一相位节点和提供输出电压Vo的端子之间，而且输出滤波器的电容与电阻负荷并联。同样地，高侧MOSFET212的漏极端子连接到输入电压Vin，低侧MOSFET214的源极端子接地，而且高侧MOSFET211的源极端子和低侧MOSFET214的漏极端子连接在一起以设定第二相位节点。输出滤波器的第二电感串联在第二相位节点和提供输出电压Vo的端子之间，而且输出滤波器的电容与电阻负荷并联。MOSFETs204、206、212、214中的每个都可以由单独的半导体片提供。由另一个半导体管芯208提供的控制器/驱动器包括脉宽调节(PWM)电路，该电路对用于控制MOSFETs204、206、212、214的启动时间的方波信号的占空比进行控制。通过适当的补偿网络将反映输出电压V0和/或电流的反馈信号提供到控制器/驱动器，以确定PWM信号的占空比。MOSFETs204、206的断开和闭合在第一相位节点上提供具有大体矩形波形的第一中间电压，而且MOSFETs212、214的断开和闭合在第二相位节点上提供具有大体矩形波形的第二中间电压。由电感和电容形成的输出滤波器将矩形波转换为完全的DC输出电压Vo。DC-DC转换器也可以包括过电流保护(OCP)网络和用于为PWM电路确定时钟频率的无源器件，与该技术中普遍知道的一样。
与前面的实施方式一样，封装产生的多数热量是由功率半导体片204、206、212、214产生的。这些热必须被有效地从功率半导体片204、206、212、214散失到LGA的外部焊盘。
根据图8的DC-DC转换器，图9说明LGA封装的衬底202上输入焊盘排列的替代实施方式。LGA一般分成两个区域，包括第一侧边区域和第二侧边区域。如图8所示，第一侧边区域包含衬底底表面的左侧，第二侧边区域包含衬底底表面的右侧。第一侧边区域包括多个大的输入焊盘，第二侧边区域包括沿LGA封装周围排列的多个小的输入焊盘。与外部焊盘相关的I/O插脚分配如下：
  插脚     功能     名称
  P1P2P3P4P5P6P7P8P9P10P11P12P13P14P15P16P17P18P19P20P21P22P23     输入电压开关电压相位2电源良好标志电流限定调节使用者控制的开关负电压检测负电压检测电流分配相位/同步正电压检测输出电压调节基准电压时钟信号电源接地电源接地电源接地电源接地电源接地开关电压输入电压电源接地负电压检测负电压检测     V<sub>IN</sub>V<sub>SW2</sub>FLAGOCPEnable-Vs-VsI<sub>SHARE</sub>PHASE+VsTrimV<sub>REF</sub>CLKP<sub>GND</sub>P<sub>GND</sub>P<sub>GND</sub>P<sub>GND</sub>P<sub>GND</sub>VswV<sub>IN</sub>P<sub>GND</sub>-Vs-Vs
表2
如图9所示，第一侧边区域内大的输入焊盘还以对称的图案排列，第一终端上大的输入焊盘P1和P2，第二终端上大的输入焊盘P19和P20，排列在它们之间的大的焊盘P21、P22和P23。第一终端上的大的输入焊盘P1、P2被分配到输入电压VIN和第一相位开关电压VSW1，并分别直接位于提供第一相位MOSFETs204、206的半导体片的下面。第二终端上的大的输入焊盘P19、P20被分配到输入电压VIN和第二相位开关电压VSW2，并分别直接位于提供第一相位MOSFETs212、214的半导体片的下面。外部焊盘P3-P18专用于分立无源器件。通过在LGA封装的反面对最大的热量产生器进行处理，热量被有效地传导穿过衬底。大的输入焊盘P21、P22和P23还提供将热传到主板的表面。应该认识到改变上面所示的插脚也在本发明的宗旨和范围之内。
众所周知，电子器件产生热，而且，除非从器件上引出多余的热，否则器件可能过热，而且结果可能产生故障。在许多应用中，器件紧密相邻的环境几乎与器件一样热，因此，热量将不会从器件上自然地散失。将只参照功率半导体管芯104对通路设计进行说明，但认为该说明可用于本发明中任何一个功率半导体管芯。
按照惯例，衬底包括部分(例如，多层衬底)或完全(例如，如图5中所示)延伸穿过衬底的多个通路。该技术所知的通路为镀覆通孔。每条通路150由部分或全部延伸穿过衬底102的镀铜开口产生。优选的实施方式中，通路150被填充了导热材料156以保证电和热从功率半导体管芯104的反面金属化表面104c传输到外部焊盘P22。导热材料1 56是一种为通路150提供低热阻的良好导热性的材料。并不是每个通路150都必须填充或插入材料156。
对每个通路150进行填充改善了热传导并消除了衬底102的管芯表面112上焊料掩膜的需要，因此允许不需要键合线而使功率半导体管芯的反面金属化表面(漏极电极)与通路150进行电和热连接。这使功率半导体管芯104与外部焊盘P22之间的热阻成为最小。对每个通路150进行填充还消除了封装内的水分残留，并增强通过通路150的热传导。该设计、定位以及通路密度并不影响管芯粘附焊盘130的接触表面130t，焊盘的表面最好是平的以在接触表面130t与半导体管芯反面金属化表面之间实现可能的最大的接触面积。
对每个通路150进行填充还具有几个其它的优点。例如，对每个通路150进行填充将使加工和焊接的化学物质避开镀铜通路150。对通路进行柱塞或填充也使通路的铜环孔电绝缘并使信号短路最小。还防止了焊料通过毛细作用穿过每个通路150，因此消除了短路，特别是位于下层的器件。应该理解并不是所有的通路150都在功率半导体管芯的反面金属化层与位于LGA(例如，P21、P22或P23)的内部区域IR内的外部焊盘之间提供低热阻路径。有些通路150在分立无源器件和位于外围区域PR(例如，外部焊盘P1-P20)内的一个或多个外部焊盘之间提供电连接。
图5说明在第一功率半导体管芯104的反面金属化表面104c和外部焊盘P22之间提供多个低热阻路径的通路阵列。一般地，每个通路150包括两个相对的终端——位于管芯粘附焊盘130附近的第一终端152和位于衬底102底表面114附近的第二终端。和前面所提及的一样，通路150的内壁镀有一定厚度的电沉积铜。图5中所示的每个通路150的内部核心最好填充了密封材料，被认为是通路柱塞或通路填充。每个通路150的内部核心也可以是空的。不管怎样，每个通路150最好是在顶端和底端用电沉积铜盖在上面。对通路加帽按惯例被认为是“覆盖镀层”，“覆盖镀层”粘附到衬底的顶端和底端的铜薄片上。
一般地，通路150执行两个功能。第一，通路150为从反面的金属化表面104c进行的热散失提供出口。第二，通路150在功率半导体管芯104与外部导电焊盘P22之间提供电连接。因此，分布在功率半导体管芯104下层的通路150并行地起着热管的作用，即同时具有将热量从反面的金属化表面104c驱除的功能。在本实施方式中，衬底102包括两层。因此，每个通路150提供单一的基本上垂直的路径穿过衬底102。
图6说明用于从器件上并穿过衬底散失热量的传统的矩形通路阵列。在矩形排列中，通路可以将热量传到临近通路的范围以有效单元160表示。在图6所示的通路排列中，有效单元160包括被四个临近的通路151a、151b、151c和151d包围的中央通路151。取决于通路150的节距，功率半导体管芯与LGA的外部焊盘之间产生的热流路径或者是完全垂直的，或者是水平路径和垂直路径的组合。例如，如果通路150相互之间间隔足够近，当引导热量向下到衬底102的底表面114并到主板的同时，每个通路150将向临近的通路150横向传输热量。图6中，中央通路150可以有效地将热量传到每个临近的通路151a、151b、51c、151d。横向传热量取决于通路150的节距和纵横比以及通路150内器件的材料特性。只是为了举例，如果每个通路的节距(一个通路中心到临近通路的间距)为0.3mm，则有效单元160的面积为0.32mm2。
本发明对图6中所示的传统的矩形通路阵列进行了改善。图7说明本发明的高密度通路阵列的具体实施方式。图7显示通路150彼此之间的间隔是错排的。通路150可以将热量传到临近通路的范围以有效单元162表示。有效单元162包括被六个临近的通路150a、150b、150c、150d、150e和150f包围的中央通路150。因此，每个中央通路150可以有效地将热量传到六个临近的通路150a、150b、150c、150d、150e、150f中的每一个，这产生了更高热效率的封装。
假定每个通路的节距保持在0.3mm，则有效单元162的面积增加到0.48mm2——在传统的矩形通路阵列上增加50％。高密度通路阵列因此增加了可以装在功率半导体管芯下面的通路的数量。只是为了举例，图7中所示的高密度通路阵列将在每个半导体管芯下面包括五个以上的通路(考虑到衬底上由于其它器件而产生的设计限制)。这在能够将热量从每个功率半导体管芯到衬底底表面散失的通路的数量上表现出12.5％的增加。图7中所示的高密度通路阵列的在散热方面的总体效果与图6中所示的矩形通路阵列相比提高达到15％。
前面的本发明最好的具体实施方式的说明已用于提供说明和描述的目的。这并不是全部的或者并不是将本发明局限在已说明的确定的形式。明显地，对于本技术的技术人员进行许多更改或变化将是显然的。为了更好地解释本发明的原理及其实际应用，选择并说明了具体实施方式，因此使本技术的其他技术人员能够为各种具体实施方式以及各种更改(如适合于预定的特殊应用)而理解本发明。有意的是本发明的范围由权利要求书及其等同物而限定。

Claims (17)

1. 一种基板栅格阵列封装，包括：
具有顶表面和底表面的衬底；
在上述衬底上提供的DC-DC转换器，上述的DC-DC转换器包括至少一个布置在上述衬底的上述顶表面上的功率硅管芯；和
在上述衬底的上述底表面上提供的多个导电和导热的焊盘，这些焊盘通过各自的导电通路与上述的DC-DC转换器进行电连接，上述的多个焊盘包括具有第一表面积的第一焊盘和具有第二表面积的第二焊盘，上述的第二表面积基本上大于上述的第一表面积；
其中，通过上述的多个焊盘，上述DC-DC转换器产生的热被传导到上述的基板栅格阵列封装以外。
2. 权利要求1的基板栅格阵列封装，其中所述至少一个功率硅管芯包括至少一个功率MOSFET器件。
3. 权利要求1的基板栅格阵列封装，其中所述至少一个功率硅管芯与至少一个上述的第二焊盘基本上对齐。
4. 权利要求1的基板栅格阵列封装，其中所述第一焊盘基本上位于上述底表面的外围区域。
5. 权利要求4的基板栅格阵列封装，其中所述第二焊盘基本上位于上述底表面的内部区域。
6. 权利要求1的基板栅格阵列封装，其中所述第一焊盘基本上位于上述底表面的第一侧。
7. 权利要求6的基板栅格阵列封装，其中所述第二焊盘基本上位于上述底表面的第二侧。
8. 权利要求1的基板栅格阵列封装，其中所述至少一个功率硅管芯还包括高侧MOSFET器件和低侧MOSFET器件。
9. 权利要求1的基板栅格阵列封装，其中所述至少一个功率硅管芯还包括第一对MOSFET器件和第二对MOSFET器件。
10. 权利要求9的基板栅格阵列封装，其中所述第一对MOSFET器件基本上与布置在上述底表面第一侧附近的第二焊盘中相应的第一对对齐，上述的第二对MOSFET器件基本上与布置在上述底表面第二侧附近的第二焊盘中相应的第二对对齐。
11. 权利要求1的基板栅格阵列封装，其中所述衬底包括多个在上述顶表面上提供的管芯粘附焊盘，所述至少一个功率半导体管芯被安装到上述多个管芯粘附焊盘的相应的一个上。
12. 权利要求1的基板栅格阵列封装，其中所述DC-DC转换器还包括多个分立无源器件，这些无源器件与所述至少一个功率半导体管芯电连接。
13. 权利要求1的基板栅格阵列封装，其中上述导电通路延伸穿过上述衬底，上述导电通路中的每一个都有位于所述至少一个功率半导体管芯附近的第一终端和位于上述第二焊盘之一附近的第二终端。
14. 权利要求13的基板栅格阵列封装，其中所述导电通路被排列成位于所述至少一个功率半导体管芯下面的阵列。
15. 权利要求14的基板栅格阵列封装，其中所述阵列与所述至少一个功率半导体管芯和所述第二焊盘之一电和热连接。
16. 权利要求1的基板栅格阵列封装，其中所述DC-DC转换器还包括降压转换器。
17. 权利要求1的基板栅格阵列封装，其中所述DC-DC转换器还包括两相降压转换器。
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US6940724B2 (en) 2005-09-06
EP1676316A4 (en) 2007-09-19
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US20040212074A1 (en) 2004-10-28
KR100770482B1 (ko) 2007-10-25

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