CN2692833Y - 一种用于薄型芯片模塑封装的条带 - Google Patents

一种用于薄型芯片模塑封装的条带 Download PDF

Info

Publication number
CN2692833Y
CN2692833Y CN 200420021334 CN200420021334U CN2692833Y CN 2692833 Y CN2692833 Y CN 2692833Y CN 200420021334 CN200420021334 CN 200420021334 CN 200420021334 U CN200420021334 U CN 200420021334U CN 2692833 Y CN2692833 Y CN 2692833Y
Authority
CN
China
Prior art keywords
chip
utility
model
band
strip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 200420021334
Other languages
English (en)
Inventor
周怡
沈岚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN 200420021334 priority Critical patent/CN2692833Y/zh
Application granted granted Critical
Publication of CN2692833Y publication Critical patent/CN2692833Y/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种用于薄型芯片模塑封装的条带，包括在模塑区内的金属底板，其特征在于；在放置芯片的中心金属底板上，向下腐蚀或冲压一用以放置半导体芯片的凹面。下凹深度可为条带厚度的1/4至3/4，形成能放置芯片的下凹平面。本实用新型将芯片底面置于该下凹区，有效降低芯片的相对厚度，以达到整体封装厚度下降。另外，使用本实用新型条带，在不增加投资成本的前提下利用目前常规的非接触工艺，生产出更薄的非接触智能卡模块。

Description

一种用于薄型芯片模塑封装的条带
技术领域
本实用新型涉及微电子半导体封装技术，尤其涉及一种用于薄型芯片模塑封装的条带。
背景技术
现有芯片模塑封装，例如：非接触智能卡模块，如图1a和图1b所示，总厚度较薄，通常封装厚度0.40mm。封装时，首先将很薄的半导体芯片2，用快固化环氧树脂3，牢固地焊在条带1的封装区中部的金属底板4上。然后用金丝5将芯片2上的焊点与条带1上的接触片6互连。最后，将焊好金丝的整个器件用模塑料7封装成模块。其中，非接触模块的条带1为金属条带，厚度为0.06mm至0.10mm。
薄型卡需要非接触智能模块进一步减薄，必需将半导体芯片2减至更薄。进一步减薄半导体芯片2的厚度，导致成本大幅度升高。并且芯片2更容易碎裂，使成品率和可靠性下降。
实用新型内容
本实用新型的目的在于提供一种用于薄型芯片模塑封装的条带，从而有效地降低芯片的相对厚度，以达到整体封装厚度下降。
本实用新型所提供的一种用于薄型芯片模塑封装的条带，包括在模塑区内的金属底板，其特征在于；在放置芯片的中心金属底板上，向下腐蚀或冲压一用以放置半导体芯片的凹面。
上述的用于薄型芯片模塑封装的条带，在中心金属底板上腐蚀或冲压的下凹深度为条带厚度的1/4至3/4，形成能放置芯片的下凹平面。
采用了上述的技术解决方案，在条带的放置半导体芯片的金属底板的区域，用腐蚀或冲压方法形成一下凹区，将芯片底面置于该下凹区，有效降低芯片的相对厚度，以达到整体封装厚度下降。另外，使用本实用新型条带，在不增加投资成本的前提下利用目前常规的非接触工艺，生产出更薄的模塑封装芯片。
附图说明
图1a、图1b分别是现有非接触式智能卡用模块的结构主视剖面图和俯视剖面图。
图2a、图2b，图2a′、图2b′分别是本实用新型第一实施结构和第二实施例结构条带在智能卡用模块中的结构主视剖面图和俯视剖面图。
图3a、图3b分别是本实用新型第三实施结构条带在智能卡用模块中的结构主视剖面图和俯视剖面图。
图4a、图4b分别是本实用新型第四实施结构条带在智能卡用模块中的结构主视剖面图和俯视剖面图。
图5a、图5b分别是本实用新型第五实施结构条带在智能标签中的结构主视剖面图和俯视剖面图。
具体实施方式
本实用新型，即用于薄型芯片模塑封装的条带，例如：智能卡模块封装的条带，包括如图1a、图1b所示现有的在模塑区内的金属底板4，其特点是，在放置芯片2的中心金属底板上，向下腐蚀或冲压一个凹面，以放置半导体芯片2。
如图2a、2b中的a部分所示，金属底板中心腐蚀或冲压，形成环形下凹0.02mm到0.06mm的平面。
图2a′、图2b′中的a′部分所示，也可以形成断续环形下凹0.02mm到0.06mm的平面。
如图3a、3b中的b部分所示，金属底板中心腐蚀或冲压，形成对边槽形下凹0.02mm到0.06mm的平面。
如图4a、4b中的c部分所示，金属底板中心腐蚀或冲压，形成整个底座下陷0.02mm到0.06mm的平面。
本实用新型，即用于薄型芯片模塑封装的条带，例如：智能标签封装的条带，如图5a、5b中的d部分所示，金属底板中心腐蚀或冲压，形成环形下凹0.02mm到0.06mm的平面。
由于芯片2焊接在形成下凹的金属底板4上，在模塑封装时，相当于减薄了芯片，并增加了芯片的焊接强度。另外，该结构的形成，可以在腐蚀或冲制时，同时形成，不需增加额外成本。
本实用新型的下凹结构条带，完全与现有模块制造设备和工艺相兼容。与现有的芯片焊机，金丝球焊机和模塑机完全相容。

Claims (2)

1.一种用于薄型芯片模塑封装的条带，包括在模塑区内的金属底板，其特征在于；在放置芯片的中心金属底板上，向下腐蚀或冲压一用以放置半导体芯片的凹面。
2.根据权利要求1所述的用于薄型芯片模塑封装的条带，其特征在于：在所述中心金属底板上腐蚀或冲压的下凹深度为条带厚度的1/4至3/4，形成能放置芯片的下凹平面。
CN 200420021334 2004-03-29 2004-03-29 一种用于薄型芯片模塑封装的条带 Expired - Fee Related CN2692833Y (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200420021334 CN2692833Y (zh) 2004-03-29 2004-03-29 一种用于薄型芯片模塑封装的条带

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200420021334 CN2692833Y (zh) 2004-03-29 2004-03-29 一种用于薄型芯片模塑封装的条带

Publications (1)

Publication Number Publication Date
CN2692833Y true CN2692833Y (zh) 2005-04-13

Family

ID=34769920

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200420021334 Expired - Fee Related CN2692833Y (zh) 2004-03-29 2004-03-29 一种用于薄型芯片模塑封装的条带

Country Status (1)

Country Link
CN (1) CN2692833Y (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101341499A (zh) * 2005-12-05 2009-01-07 斯迈达Ip有限公司 芯片卡和生产芯片卡的方法
CN102446868A (zh) * 2011-12-28 2012-05-09 上海长丰智能卡有限公司 一种新型双界面智能卡模块及其实现方式

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101341499A (zh) * 2005-12-05 2009-01-07 斯迈达Ip有限公司 芯片卡和生产芯片卡的方法
CN102446868A (zh) * 2011-12-28 2012-05-09 上海长丰智能卡有限公司 一种新型双界面智能卡模块及其实现方式

Similar Documents

Publication Publication Date Title
CN102244016B (zh) 树脂密封型半导体装置及其制造方法、引线框
CN101611484A (zh) 无引脚半导体封装及其制造方法
US11495523B2 (en) Lead frame having a die pad with a plurality of grooves on an underside
CN104425400A (zh) 具有预成型腔体引脚框架的腔体封装
CN2692833Y (zh) 一种用于薄型芯片模塑封装的条带
CN107146777A (zh) 一种免切割封装结构及其制造工艺
CN108198804B (zh) 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN212303647U (zh) 一种半导体塑料封装结构
CN213401186U (zh) 一种具有应力释放结构的引线框架及封装料片
CN101447036B (zh) 一种非接触智能电子标签用微型模块及载带
CN210245488U (zh) 非接触式上下芯片封装结构
CN212587519U (zh) 一种led晶元封装结构
CN202855731U (zh) 一种超薄非接触模块用载带以及非接触模块
CN2626049Y (zh) 一种非接触智能卡条带
CN102915994A (zh) 一种超薄非接触模块用载带、非接触模块以及封装方法
CN221927651U (zh) 一种塑封贴片式电阻
CN101447465B (zh) 一种大尺寸非接触模块封装用金属载带
CN215496699U (zh) 一种贴片式二极管框架
CN220569672U (zh) 一种r6c短引线光伏旁路二极管
TW465065B (en) Fabrication of hybrid semiconductor devices
CN214411193U (zh) 一种封装天线结构及电子设备
CN216413073U (zh) 一种内置基板的引线框架
CN210466441U (zh) 一种双界面ic卡
CN217641396U (zh) 一种微型led芯片封装结构
US20030052393A1 (en) Semiconductor device

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee