CN2621378Y - Multimedia coding-decoding transmission device - Google Patents
Multimedia coding-decoding transmission device Download PDFInfo
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- CN2621378Y CN2621378Y CN 03256404 CN03256404U CN2621378Y CN 2621378 Y CN2621378 Y CN 2621378Y CN 03256404 CN03256404 CN 03256404 CN 03256404 U CN03256404 U CN 03256404U CN 2621378 Y CN2621378 Y CN 2621378Y
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Abstract
The utility model provides a multimedia coding and decoding transmission device. The circuit of the transmission device comprises a coder and a decoder. Both the coder and the decoder adopt a wavelet compression format video coder/decoder chip and DSP as a central processing unit, respectively. Peripheral equipments of each DSP comprise a microprocessor MCU, a sequential logic control, a buffer, an external storage SDRAM. The DSP is connected with an actuating ROM, a USB interface controller and a 10/100Baset interface controller through the buffer. Six-wire seamless connection is directly adopted between a digital signal processor DSP and an E1/T1 interface controller. The device supports comprehensive transmission of multiple services of forward audio, video and data services, and reverse audio and data services, can ensure quality of all of the services, supports transmission of the interfaces, such as USB, 10/100BaseT, E1/T1 and so on, and ensures expansibility and reliability of the system. The hardware circuit of the device is simple and is easy to be formed; the utility model works reliably, and has the advantages of high cost performance.
Description
Technical field
The present invention relates to a kind of multi-media decoding and encoding transmitting device, exactly, relate to a kind of total digitalization that can solve multimedia service, real-time Transmission multimedia motion image sequence, and the codec that on many interfaces such as E1/T1, USB, 10BaseT/100BaseT, transmits multimedia services such as forward audio frequency, video, data and reverse audio frequency, data.Belong to multimedia communication and technical field of video monitoring.
Background technology
In existing multimedia coding-decoder, can both support unidirectional vision signal (camera review) and audio signal greatly, but the multimedia coding-decoder that can support multi-service (forward audio frequency, video, data service, oppositely audio frequency, data service) comprehensive transmission seldom.Therefore, the realization of multimedia service normally relies on a plurality of separate operation systems (for example data service system, supervisory control system, communication system etc.) to work simultaneously and finish jointly at present.Operation department will carry out integrated service like this, just needs many cover systems of construction and network could realize the transmission of video, audio frequency, data, and the maintenance of not only cost height, and system is also quite difficult.Because this multiservice functionality of piecing together, interlock is poor in real time, stability is lower, also image and the nonsynchronous phenomenon of sound occur through regular meeting.In addition, the greatest drawback of this mode is that network management and control ratio are difficult, and the initial investment expense is huge.
At present, the transmission bandwidth that existing high resolution multimedia codec needs is mostly at 4Mbit/s～19Mbit/s, even wideer frequency band, all can not be under the condition that is lower than the 2Mbit/s code check, with adaptive frame per second, realize transmitting in real time 720 * 576 high-definition picture.That is to say that present most of multimedia coding-decoders are difficult in the specification requirement that realizes the real-time Transmission high-definition picture under the low bandwidth.Moreover, present multimedia coding-decoder, great majority are at concrete application and custom-designed, can only support the application of single face, and do not support the transmission (as USB, E1/T1,100BaseT/10BaseT etc.) of multiple interfaces, influenced their application in multiple Integrated Solution.
Summary of the invention
The purpose of this utility model provides a kind of multi-media decoding and encoding transmitting device that can overcome above-mentioned shortcoming and problem, realization digitlization, high-resolution, possess multiple coffret ability, this device is supported forward audio frequency, video, data service and oppositely multiple services comprehensive transmission such as audio frequency, data service, its multi-service inserts the service quality that can guarantee various access service, autgmentability and reliability that can also support system.This device adopts the multiple network interface in transmission: can support the transmission of multiple network interfaces such as E1/T1, USB, 10BaseT/100BaseT, therefore this device has autgmentability aspect Network Transmission, can realize various transmission plans easily, help the application of sorts of systems integrator.
The purpose of this utility model is achieved in that a kind of multi-media decoding and encoding transmitting device, and its control circuit is made up of encoder two parts; It is characterized in that: described encoder all is to adopt the video compression coding of wavelet compression form and the codec chip of reduction decoding, and adopting digital signal processor DSP as central processing unit, the ancillary equipment of each digital signal processor DSP comprises microprocessor MCU, sequential logic controller, buffer and external memory storage SDRAM; This digital signal processor DSP is connected with by buffer: starting ROM, usb interface controller and 10BaseT/100BaseT interface controller, then is directly to adopt six line seamless links between digital signal processor DSP and the E1/T1 Interface controller.
The Video Codec chip of described employing wavelet compression form has image is carried out wavelet compression/decompressing function, has digital I/O data/address bus; Include but not limited to the ADV6xx series small echo Video Codec chip of ADI's development and production.
The Video Codec chip of described employing wavelet compression form is connected with the sequential logic controller that the sequential logic of this codec chip is carried out conversion and control, this sequential logic controller is connected to digital signal processor by described buffer, and the HIRQ of codec chip directly is connected with the EXT_INT of digital signal processor, use the interruption of digital signal processor realize encoding and decoding synchronously.
The Video Codec chip of described employing wavelet compression form is connected with the DRAM memory that is used for coding and decoding video and inputs or outputs the video a/d converter or the video d/a transducer of end as it.
Described digital signal processor DSP has the data/address bus more than 32 or 32, has one or more McBSP communication interface; Include but not limited to that TIX produces, its model is the chip of TMS320C620X or TMS320C621X or TMS320C670X or TMS320C671X series.
The model of described E1/T1 Interface controller chip is DS21354 or DS21554, the following pin of this chip: receive clock RCLK, reception data RSER, received frame synchronizing signal RSYNC, tranmitting data register TCLK, transmission data TSER and transmit frame synchronizing signal FSYNC, realize seamless link with CLKR, DR, FSR, CLKX, DX and FSX six lines of described digital signal processor DSP chip respectively; Its model includes but not limited to DS21354, DS21554 and DS2X54.
Described encoder section control circuit and decoder section control circuit include respectively: with the direct-connected Data Interface Control Unit of digital signal processor DSP, this Data Interface Control Unit receives forward data input and reverse data output; With the direct-connected jtag port that is used for artificial debugging of digital signal processor DSP.
Described encoder section control circuit and decoder section control circuit include respectively: with the direct-connected audio coding/decoding device of digital signal processor DSP, this audio coding/decoding device is connected with audio A/D and D/A converter, and the latter is connected with reverse output interface with analogue audio frequency forward input interface by operational amplifier; Described digital signal processor DSP can directly link to each other with the audio frequency terminal.
Also be provided with respectively the clock circuit that clock information is provided to sequential logic controller and video a/d converter in the described encoder section control circuit.
Also be provided with respectively the clock circuit that clock information is provided to sequential logic controller and wavelet compression codec in the described decoder section control circuit.
Described microprocessor MCU has I
2C bus and 8 or above data/address bus, its model includes but not limited to T89C511C2; Video a/d converter has analog video signal sampling and digitized function, has the digital signal output bus more than 8 or 8, and its model includes but not limited to SAA7113; The video d/a transducer has the function that the digital video signal that will meet the ITU656 form is converted to analog video signal, has the digital signal input bus more than 8 or 8; Its model includes but not limited to: ADV7176 or ADV7175.
The utility model has the advantages that many-sided: at first, what the utility model adopted on the compressed format of vision signal is the compressed format of small echo.It is the focus that the research and extension of present academia is used that small echo is used for video compression, and small echo is used for video compression and has many good qualities: can overcome because the blocking artifact that traditional piece conversion is brought; Because what wavelet compression adopted is compression in the frame, thus be easy to realize rate controlled, and encoding time delay is less; Wavelet compression also has the high advantage of compression ratio with respect to other compress mode.
The utility model the coding/decoding of video section adopt be the development of analog device (AD, AnalogDevices Inc.) company small echo is used for the extremely successful ADV601 small echo coding/decoding chip of video compression.This chip can be realized accurate rate controlled.What adopt all is compression in the frame, does not have inter prediction, has lowered coding delay.Have on the space on the resolution and temporal autgmentability, can set resolution according to user's needs.Compression ratio is the highest can to reach 350 times, can realize transmitting with the high-resolution of adaptive frame per second and 720 * 576 specification requirement of realtime graphic under the condition of the code check that is lower than 2Mbit/s.Therefore, the utility model can be realized the Integrated Solution of real-time Transmission high-definition picture quickly and easily under the low bandwidth condition, makes the investment of operator on channel save greatly.
Secondly, this device is that the multiple business of a collection is the system equipment of one, the multimedia service that this device is supported includes: forward video, audio frequency, data service and the oppositely comprehensive transmission of audio frequency, data service, and, its multi-service inserts the service quality that can guarantee every kind of access service, can also guarantee the autgmentability and the reliability of system.Owing to height integration of the present utility model, improved the ability of validity, promptness and the fast processing accident of whole device greatly, these performances also are distinctive marks of modern multimedia system intelligent management.In addition, owing to the utility model does not need to lay other communication links in addition, so significantly reduced expense costs such as procuring equipment, link construction and working service on the whole.
Moreover, the utility model is also supported multiple interfaces such as E1/T1, USB, 10BaseT/100BaseT, use this device can realize multiple transmission plan easily, for example can be used for system integration schemes such as long distance control system, DVR, video server, help the application of sorts of systems integrator.
In addition, the utility model is at hardware aspect, because adopting DSP is that interface is changed, realized seamless link with the E1/T1 controller chip, hardware circuit is simple, realizes easily reliable operation, for industrialization of the present utility model provides good ratio of performance to price advantage, has good popularization and application prospect.Comprehensive above-mentioned some, the utility model has solved many shortcomings of existing multimedia coding-decoder.Represented the developing direction of multimedia coding-decoder.
Description of drawings
Fig. 1 is that the encoder circuit structure in the utility model is formed block diagram.
Fig. 2 is that the decoder circuit structure in the utility model is formed block diagram.
Fig. 3 is the schematic diagram of DSP device and peripheral circuit in the encoder circuit in the utility model.
Fig. 4 is the schematic diagram of the video coding circuit in the utility model.
Fig. 5 is the schematic diagram of the video decode circuit in the utility model.
Fig. 6 is the logical circuit schematic diagram of the E1 interface controller in the utility model.
Fig. 7 is the logical circuit schematic diagram of the usb interface controller in the utility model.
Fig. 8 is the logical circuit schematic diagram of the network interface controller in the utility model.
Embodiment
The utility model is a kind of multi-media decoding and encoding transmitting device, and its control circuit is made up of encoder two parts; Wherein encoder all is to adopt the video compression coding and the codec chip of decoding that reduces of the wavelet compression form of ADI's development and production, and its model is ADV601; And digital signal processor DSP (the Digital Signal Processor) chip that employing TIX produces is as central processing unit, its model is TMS320C620X, TMS320C621X, TMS320C670X, TMS320C671X series, and the ancillary equipment of each digital signal processor DSP comprises microprocessor MCU, sequential logic controller, buffer and external memory storage SDRAM (referring to Fig. 3); This digital signal processor DSP is connected with by buffer: starting the usb interface controller and the 10BaseT/100BaseT interface controller (referring to Fig. 1 and Fig. 2) of ROM, transmitted in both directions, then is directly to adopt six line seamless links (referring to Fig. 6) between digital signal processor DSP and the E1/T1 Interface controller.
Below in conjunction with each accompanying drawing, specifically introduce the control circuit structure and the operation principle thereof of encoder in the utility model.
Referring to Fig. 1 and Fig. 4, at first introduce the forward of encoder and the control circuit of reverse multi-service I/O, encoder of the present utility model is supported the single channel analog video signal, vision signal is by C terminal or the input of S terminal, carry out analog-to-digital conversion by video a/d converter 5 (model is SAA7113), finish the digitlization of analog video signal, output meets the digital video signal of ITU-656 form.Again its video signal sampling clock LLC, digital video signal VPO7～0 pin are connected directly to the input clock VCLK of encoder chip 7 (model is ADV601) of small echo video compression and the pin of inputting video data VDATA7～0 respectively, provide work clock and for the transfer of data of VPO7～0 provides synchronizing function by LLC to ADV601, so that to the encoding video signal compression of its output.The code stream that produces is input to dsp processor 1 after buffering, so constitute the forward video traffic.Simultaneously, amplified and audio A/D converter 17 analog-to-digital conversion through operational amplifier 19 by the input of audio frequency terminal forward, the digital audio and video signals through audio codec 15 encoding process also is input to dsp processor 1 with the forward data signal through Data Interface Control Unit 21 inputs again; Also the audio frequency terminal directly can be inserted DSP, audio frequency be carried out software coding by DSP.Be responsible for video, audio frequency and data code flow are sent to USB interface, 10BaseT/100BaseT interface or E1/T1 Interface chip by dsp processor 1, forward video traffic and forward audio frequency, data service have constituted forward multi-service input jointly.Reverse traffic output mainly is the reverse audio frequency and the output of data service.
Because the data of video a/d converter 5 (model: SAA711 3) output are the ITU-656 forms, its row synchronously and field synchronization information all be included in the dateout of VPO7～0 mouthful, RTS0 and RST1 are programmable, can export horizontal-drive signal and field sync signal.The utility model is finished by microprocessor 3 (MCU) the configuration of SAA711 3, the model of selecting for use is the T89C51IC2 of atmel corp, this device also by parallel port to E1/T1 Interface controller chip 13 (model: DS21354) configuration effort parameter.This microprocessor 3 is integrated I on sheet
2The C controller can pass through I easily
2The running parameter of C mouth configuration video a/d converter (model is SAA7113).
Referring to Fig. 4, the forward video input signals is behind ADV601 coding chip coding, the output video compressed bit stream, because the logic of external memory interface EMIF (External Memory Interface) on sequential of its interface sequence and digital signal processor DSP device 1 of the present utility model is inconsistent, so between the two, the utility model adopts a sequential logic controller 9 (CPLD) to finish AD601 and the conversion of DSP on sequential logic, data flow is sent into DSP device 1 again.Because DSP is to use asynchronous serial interface to read the code stream of ADV601 output, for guarantee ADV601 and DSP on sequential logic synchronously, also the HIRQ (being the INT1 of CPLD) of ADV601 is connected to the EXT INT of DSP, the interruption of use DSP realizes synchronously.In order to make the wavelet coders 7 can operate as normal, ADV601 also should connect the DRAM memory chip 23 that is used for video coding, and its circuit connects as shown in Figure 4, because be custom circuit, this paper does not give unnecessary details.
The following describes the DSP device 1 and the peripheral circuit thereof of encoder in the utility model,, through after the buffering, together enter DSP device 1 behind the forward video coding with forward data and audio code stream referring to Fig. 1.DSP device 1 of the present utility model is TMS320C620X, TMS320C621X, TMS320C670X, the TMS320C671X series of products that TIX produces.After this DSP device 1 is packed complex data, can select different interface output according to channel transmitted.For example: DSP can send packing data to E1/T1 Interface controller chip 13, by it data is delivered to the E1/T1 channel.In like manner, DSP also can send packing data to usb interface controller chip 33 or 10/100BaseT interface controller chip 35 through buffer 27, data is delivered on USB channel or the 10BaseT/100BaseT network channel respectively by it and is transmitted.Simultaneously, by the reverse audio signal that transmits on corresponding USB, E1/T1 of decoder 2 warps or the 10/100BaseT interface channel and the superpacket of reverse data, after 33,13,35 receptions of corresponding interface controller chip, output to DSP device 1, after unpacking by DSP device 1, output to reverse audio coding/decoding device 15 and Data Interface Control Unit 21 respectively, finished reverse multi-service transmission.
Because the external memory interface EMIF of the DSP device 1 in the encoder circuit will connect a plurality of outputs: start rom chip 25, usb interface controller chip 33 and 10/100BaseT interface controller chip 35, die buffer 27 should be set, link to each other with load again after first data to its output cushion.Its circuit is referring to Fig. 3.In order to make DSP device 1 operate as normal, DSP also should connect SDRAM chip 31 and start rom chip 25.The former directly links to each other with the EMIF interface of DSP by SDRAM chip 31.The EMIF interface of DSP links to each other with startup rom chip 25 through behind the buffer 27 again.In addition, be convenient to artificial debugging in order to make DSP device 1, the utility model has added jtag interface chip 29 in hardware designs.Because above-mentioned various connections are custom circuit, this paper repeats no more.
For the ease of the mutual communication between MCU chip 3 and the DSP device 1, MCU chip 3 is connected with HPI (the Host Port Interface) interface of DSP device 1.The HINT pin of DSP device 1 is received the INT pin of MCU chip 3.Other pins of HPI interface are received general purpose I/O pin of MCU.Its connecting circuit is referring to Fig. 3.
Need to prove: the encoder in the utility model is in many interface control circuits, it is on all four that DSP device 1 is connected with hardware between each interface controller chip, be DSP device 1 and control logic circuit on E1/T1 Interface, USB interface, the 10BaseT/100BaseT network interface is on all four, so, this paper lumps together the unified explanation of do to many interface control circuits of encoder, describes no longer respectively.
Realize the circuit diagram of six line seamless links referring to dsp chip of the present utility model shown in Figure 6 1/2 and E1/T1 Interface controller 13/14.Wherein E1 is 32 road PCM standards, and T1 is 24 road PCM standards.Because the receive clock RCLK of E1 interface controller chip 13/14 (model is DS21354/21554), reception data RSER, received frame synchronizing signal RSYNC, tranmitting data register TCLK, transmission data TSER, transmit frame synchronizing signal FSYNC have the sequential of the multichannel serial line interface MCBSP (Multi-Channel Buffered Serial Port) of buffering to fit like a glove respectively with in the dsp chip 1/2, can realize six line seamless links.Therefore, above-mentioned six pins are connected with CLKR, DR, FSR, CLKX, DX and the FSX pin of DSP device 1/2 respectively.The TRING of E1 interface controller 13/14 (model is DS21354/21554), TTIP pin send data, are sent on the E1 channel after E1 sends transformer.Data from the E1 channel is come are then received by the RRING of E1 interface controller 13/14, RTIP pin via the E1 receiving transformer.
Referring to Fig. 7, the external memory interface EMIF of the DSP device 1/2 in the utility model through buffering after, be connected by the output and the usb interface controller chip 11/12 (model is SL811HS) of buffer 27/28, and adopt asynchronous sequential logic.The pin that buffer 11/12 output is connected with SL811HS chip 17/27 has: ED8～0-forwards/reverse superpacket data, EA2-address signal, CE-chip selection signal, the asynchronous read signal of ARE-, AWE-asynchronous write signal.The utility model also is connected to the INTRQ pin of SL811HS chip 11/12 the EXT_INT pin of DSP device 1/2, uses the interruption of DSP to manage the USB incident.SL811HS chip 11/12 is connected to the USB channel by DATA+ and DATA-, carries out the reception and the transmission of data.
Referring to Fig. 8, the external memory interface EMIF of the DSP device 1/2 in the utility model through buffering after, be connected by the output and the 10/100BaseT interface controller chip 35/36 (model is CS8900) of buffer 27/28, and adopt asynchronous sequential logic.The output of buffer 27/28 has with the pin that CS8900 chip 35/36 is connected: ED15～0-forwards/reverse superpacket data, EA21～2-address signal, CE-chip selection signal, the asynchronous read signal of ARE-, AWE-asynchronous write signal.The utility model also is connected to the INTRQ pin of CS8900 chip 35/36 the EXT_INT pin of DSP device 1/2, uses the interruption of DSP to manage the 10/100BaseT incident.The TXD+ of CS8900 chip 35/36, TXD-pin send data, send transformer via network and are sent on the 10/100BaseT EtherChannel.The data that transmit from the 10/100BaseT EtherChannel are then received by the RXD+ of CS8900 chip 35/36, RXD-pin through the network receiving transformer.
Introduce the control circuit of decoder forward multi-service output in the utility model and reverse traffic input below, referring to Fig. 2, because video compression chip of the present utility model (ADV601) and audio compression chip both can have been made encoder and also can do decoder, therefore decoder is basic identical with encoder on the annexation of electrical schematic diagram, and wherein the annexation between ADV601 and the DSP is identical.Interface logic between them also is identical with the encoder control circuit, repeats no more here.Just the flow direction of data is just in time opposite, and video a/d converter 5 is substituted by video d/a converter 6 (model is ADV7176 or ADV7175).Be that ADV601 receives video code flow and decodes, the output digital video signal is to D/A converter 6.At ADV601 during as decoder 8, its work clock VCLK is that the crystal oscillator by 27M provides, and as shown in Figure 5, this point is different with encoder.The work clock of video d/a converter 6 is that the VCLKOUT pin by ADV601 provides, and the running parameter of video d/a converter 6 is also by microcontroller 4 (MCU) configuration, as encoder.The digital video signal of decoder 8 of the present utility model (model is ADV601) decoding output is converted to analog video signal through video d/a converter 6, can export by the C terminal of ADV7176, also can be by the output of S terminal.Simultaneously, the digital audio and video signals of decoder 8 output is through the analog-to-digital conversion of audio coding/decoding device 16 decoding processing and audio A/D converter 18, after sending into operational amplifier 20 again and amplifying, forms the output of forward audio frequency.From the output of decoding chip analog audio-video signal, add the multi-service output that has constituted forward through the data-signal of Data Interface Control Unit 22 outputs together jointly.Oppositely audio frequency input and reverse data input constituted reverse multi-service input jointly.
Referring to Fig. 5, because the data flow of logical AND small echo decoder chip 8 (model the be ADV601) output of the external memory interface EMIF of the digital signal processor DSP device 2 that adopts in the utility model decoder control circuit on sequential is inconsistent, so, the utility model adopts a slice sequential logic controller chip 10 (CPLD) to finish AD601 and the conversion of DSP on sequential logic between the two, data flow is sent into decoder chip 8 again.Need to prove that DSP device 2 is earlier the coherent signal of its output to be delivered to after the buffer 12, send CPLD chip 10 again to.Because DSP is to use asynchronous serial interface to read the code stream of ADV601 output, for guarantee ADV601 and DSP on sequential logic synchronously, also the HIRQ (being the INT1 of CPLD) of ADV601 is connected to the EXT_INT of DSP, the interruption of use DSP realizes synchronously.In order to make the small echo decoder 8 can operate as normal, ADV601 also should connect the external memory storage SDRAM 24 that is used for video coding, because be custom circuit, this paper does not give unnecessary details.
The utility model has been developed performance prototype and has been experimentized, simulates and implement and try out, facts have proved of test, this device can be lower than under the code check condition of 2Mbit/s, realization is with more than 352 * 288 (352 * 288,720 * 288,720 * 576 etc.) resolution transmits the specification requirement of real time kinematics image sequence; Can be implemented in the specification requirement that transmits the motion image sequence of 352 * 288 above resolution in real time on the E1 channel of 2Mbit/s bandwidth; Can support forward multimedia service (audio frequency, video, data service) and reverse audio frequency and data service comprehensively to transmit.In a word, realized goal of the invention.
Claims (11)
1, a kind of multi-media decoding and encoding transmitting device, its control circuit is made up of encoder two parts; It is characterized in that: described encoder all is to adopt the video compression coding of wavelet compression form and the codec chip of reduction decoding, and adopting digital signal processor DSP as central processing unit, the ancillary equipment of each digital signal processor DSP comprises microprocessor MCU, sequential logic controller, buffer and external memory storage SDRAM; This digital signal processor DSP is connected with by buffer: starting ROM, usb interface controller and 10BaseT/100BaseT interface controller, then is directly to adopt six line seamless links between digital signal processor DSP and the E1/T1 Interface controller.
2, multi-media decoding and encoding transmitting device according to claim 1 is characterized in that: the Video Codec chip of described employing wavelet compression form has image is carried out wavelet compression/decompressing function, has digital I/O data/address bus; Include but not limited to the ADV6xx series small echo Video Codec chip of ADI's development and production.
3, multi-media decoding and encoding transmitting device according to claim 1 and 2, it is characterized in that: the Video Codec chip of described employing wavelet compression form is connected with the sequential logic controller that the sequential logic of this codec chip is carried out conversion and control, this sequential logic controller is connected to digital signal processor by described buffer, and the HIRQ of codec chip directly is connected with the EXT_INT of digital signal processor.
4, multi-media decoding and encoding transmitting device according to claim 1 and 2 is characterized in that: the Video Codec chip of described employing wavelet compression form is connected with the DRAM memory that is used for coding and decoding video and inputs or outputs the video a/d converter or the video d/a transducer of end as it.
5, multi-media decoding and encoding transmitting device according to claim 1, it is characterized in that: described digital signal processor DSP has the data/address bus more than 32 or 32, has one or more McBSP communication interface; Include but not limited to that TIX produces, its model is the chip of TMS320C620X or TMS320C621X or TMS320C670X or TMS320C671X series.
6, multi-media decoding and encoding transmitting device according to claim 1 or 5, it is characterized in that: the model of described E1/T1 Interface controller chip is DS21354 or DS21554, the following pin of this chip: receive clock RCLK, reception data RSER, received frame synchronizing signal RSYNC, tranmitting data register TCLK, transmission data TSER and transmit frame synchronizing signal FSYNC, realize seamless link with CLKR, DR, FSR, CLKX, DX and FSX six lines of described digital signal processor DSP chip respectively; Its model includes but not limited to DS21354, DS21554 and DS2X54.
7, multi-media decoding and encoding transmitting device according to claim 1, it is characterized in that: described encoder section control circuit and decoder section control circuit include respectively: with the direct-connected Data Interface Control Unit of digital signal processor DSP, this Data Interface Control Unit receives forward data input and reverse data output; With the direct-connected jtag port that is used for artificial debugging of digital signal processor DSP.
8, multi-media decoding and encoding transmitting device according to claim 1, it is characterized in that: described encoder section control circuit and decoder section control circuit include respectively: with the direct-connected audio coding/decoding device of digital signal processor DSP, this audio coding/decoding device is connected with audio A/D and D/A converter, and the latter is connected with reverse output interface with analogue audio frequency forward input interface by operational amplifier; Described digital signal processor DSP can directly link to each other with the audio frequency terminal.
9, multi-media decoding and encoding transmitting device according to claim 1 is characterized in that: also be provided with respectively the clock circuit that clock information is provided to sequential logic controller and video a/d converter in the described encoder section control circuit.
10, multi-media decoding and encoding transmitting device according to claim 1 is characterized in that: also be provided with respectively the clock circuit that clock information is provided to sequential logic controller and wavelet compression codec in the described decoder section control circuit.
11, multi-media decoding and encoding transmitting device according to claim 1 is characterized in that: described microprocessor MCU has I
2C bus and 8 or above data/address bus, its model includes but not limited to T89C511C2; Video a/d converter has analog video signal sampling and digitized function, has the digital signal output bus more than 8 or 8, and its model includes but not limited to SAA7113; The video d/a transducer has the function that the digital video signal that will meet the ITU656 form is converted to analog video signal, has the digital signal input bus more than 8 or 8; Its model includes but not limited to: ADV7176 or ADV7175.
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|---|---|---|---|
| CN 03256404 CN2621378Y (en) | 2003-04-22 | 2003-04-22 | Multimedia coding-decoding transmission device |
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| CN 03256404 CN2621378Y (en) | 2003-04-22 | 2003-04-22 | Multimedia coding-decoding transmission device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194963A (en) * | 2018-09-27 | 2019-01-11 | 深圳市中新力电子科技有限公司 | A kind of network marketing net cast display systems |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109194963A (en) * | 2018-09-27 | 2019-01-11 | 深圳市中新力电子科技有限公司 | A kind of network marketing net cast display systems |
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