CN100413288C - System for transmitting data frame of Etheent based on insertion between frames - Google Patents
System for transmitting data frame of Etheent based on insertion between frames Download PDFInfo
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- CN100413288C CN100413288C CNB2005100867864A CN200510086786A CN100413288C CN 100413288 C CN100413288 C CN 100413288C CN B2005100867864 A CNB2005100867864 A CN B2005100867864A CN 200510086786 A CN200510086786 A CN 200510086786A CN 100413288 C CN100413288 C CN 100413288C
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Abstract
The present invention belongs to the field of electric communication, which is characterized in that after the medium independent interface data of a local net A in a sending direction is inputted to an Ethernet receiving circuit, an FIFO1, a framing circuit of a high level data link control protocol, a sending buffer control circuit, an E1 sending buffer and an E1 sending circuit which are orderly cascaded, the medium independent interface data is outputted to an E1 line interface circuit. After the input signal of the E1 line interface circuit in a receiving direction passes through an E1 receiving circuit, an E1 receiving buffer, a receiving buffer control circuit, a deframing circuit of the high level data link control protocol, an FIFO2 and an Ethernet sending circuit, the input signal of the E1 line interface circuit is outputted to a local area network B by a medium independent interface. After an Ethernet data frame arrives, E1 lines are orderly polled in the system. A complete data frame is sequentially transmitted on each detected idle line. Thus, the present invention can eliminate the problem of the time delay difference caused by using a plurality of E1 lines to together transmit one split Ethernet data frame.
Description
Technical field
The present invention is applied to the telecommunication field, is a kind of economy and effective method that connects remote ethernet.
Background technology
In the local area network (LAN) field, through the competition of the survival of the fittest for many years, simple and economic Ethernet has become current application technology the most widely.These dotted ethernet interconnects being got up, realize the resource-sharing of wider scope, is the inexorable trend of network development.Ethernet has made full use of abundant e1 resource to the reverse multiplexer of multichannel E1, is a kind of economy and the effective scheme that connects two remote ethernets.
Ethernet in the market arrives the reverse multiplexer of multichannel E1, transmission again after ethernet data frame is split.The E1 transmitting terminal is assigned to each road E1 and transmits after ethernet data frame is split.Because the transmission delay difference of each road E1, it is also different that the various piece of the same Frame of Ethernet arrives the time of E1 receiving terminal, the E1 receiving terminal must pass through the enough E1 frames of buffer memory, eliminate after the delay inequality on each road, the ethernet data frame that the correct recovery of ability is sent, therefore the delay inequality between each road E1 circuit there is strict restriction,, just causes reverse multiplexer cisco unity malfunction in case exceed the patient scope of designing institute.Ethernet data frame transmission system of inserting proposed by the invention based on interframe, also be that a kind of Ethernet is to the reverse multiplexer of multichannel E1, adopt each complete ethernet data frame to walk the method for one road E1 separately, overcome restricted problem, have wider range of application delay inequality.
Summary of the invention
The object of the present invention is to provide a kind of ethernet data frame transmission system of inserting, it is characterized in that based on interframe:
This system is a kind of data frame transfer system that the method that by telecommunications network each ethernet data frame inserted by interframe on Ethernet host-host protocol basis is walked one road E1 circuit separately, comprises sending subsystem and receiving subsystem two large divisions, wherein:
The transmission subsystem comprises: the Ethernet receiving circuit that is connected with local area network (LAN) A, and FIFO1, the High level data link control framer circuit sends cache control circuit, E1 transmit buffer, and E1 transtation mission circuit, wherein:
The Ethernet receiving circuit that is connected with local area network (LAN) A, cyclic redundancy check (CRC) is carried out in the data input of this circuit receiver media stand-alone interface, exports correct ethernet data frame;
FIFO1 receives the ethernet data frame that described Ethernet receiving circuit is sent;
The High level data link control framer circuit, this circuit is a framer circuit according to the High level data link control operation, this circuit reads ethernet data frame from described FIFO1, be packaged into described High level data link control predetermined data frame format, output High level data link control Frame;
Send cache control circuit, this transmission cache control circuit receives the High level data link control Frame that described High level data link control framer circuit is sent;
The E1 transmit buffer, this buffer sends buffer unit by n and forms, the method slotting according to described interframe, distribute one to send buffer unit for every road E1, each capacity that sends buffer unit is at least greater than the High level data link control Frame size of 1 maximum, described transmission cache control circuit is poll n transmission buffer unit successively, writes a complete High level data link control Frame in the transmission buffer unit that each does not overflow as yet;
The E1 transtation mission circuit, n E1 transmitting element arranged, and these E1 transmitting elements read described High level data link control Frame respectively from each corresponding described transmission buffer unit, form the E1 frame, and carry out the HDB3 coding, send to the interface circuit of E1 circuit;
Receiving subsystem comprises: the E1 receiving circuit, and the E1 reception buffer receives cache control circuit, and High level data link control is separated the frame circuit, FIFO2, and the Ethernet transtation mission circuit that is connected with local area network (LAN) B, wherein:
The E1 receiving circuit has n E1 receiving element, and each receives the E1 Frame since corresponding interface circuit of described E1 circuit these E1 receiving elements, and it is synchronous to carry out HDB3 decoding and E1, and therefrom solves the High level data link control Frame;
The E1 reception buffer, there be n E1 to receive buffer unit, each receives described High level data link control Frame since corresponding E1 receiving element, described each receive buffer unit at least greater than the size of the High level data link control Frame of 1 maximum;
Receive cache control circuit, receive the cache control circuit described n of poll reception buffer unit successively, if finding has High level data link control Frame complete more than 1 in certain reception buffer unit, then from this reception buffer unit, read 1 High level data link control Frame;
High level data link control is separated the frame circuit, and this High level data link control is separated the frame circuit and recover ethernet data frame from described High level data link control Frame;
FIFO2 receives described High level data link control and separates the ethernet data frame that the frame circuit is sent;
The Ethernet transtation mission circuit that links to each other with local area network (LAN) B, this Ethernet transtation mission circuit reads ethernet data frame from described FIFO2, send to ethernet interface circuit from medium independent interface according to reference format.
So-called interframe is inserted, just be meant that ethernet data frame arrives after, each road E1 channel of poll successively, the whole Frame of sequential delivery on the idle channel of finding on each road.Its concrete operations flow process is as follows:
At sending direction: system initialization, i puts 0 with counter; The ethernet data frame that buffer memory receives, and carry out the High level data link control framing and handle, the High level data link control Frame generated; Detect i road E1 channel, if i road E1 channel idle, then this High level data link control Frame is sent on the E1 channel of i road, after sending counter i is added 1, detect the E1 channel that step continues to seek next road free time otherwise directly counter i is added to return after 1; If i＞n then puts i=0; Ethernet data frame returns waiting step after sending and finishing, and waits for receiving next ethernet data frame.
At receive direction: system initialization, j puts 0 with counter; N E1 receiving element receives the E1 frame of E1 circuit separately respectively, and the High level data link control Frame data that solve are write corresponding reception buffer unit, a total n reception buffer unit; Detect j and receive buffer unit, if receive among the buffer unit j High level data link control Frame complete more than 1 arranged, then from this reception buffer unit, read 1 High level data link control Frame, carry out High level data link control and separate the ethernet data frame that frame processing back transmission solves, after sending counter j is added 1, return the detection step, otherwise directly counter j is added 1, return the detection step; If j＞n then puts j=0.
Operating process by receive direction can find that n reception buffer memory is relatively independent, does not need mutual wait, that is to say do not have strict requirement for the delay inequality between each road E1.The advantage that interframe is inserted just has been to overcome the restriction of network delay difference to using.In addition, because the transmission delay difference of the Frame of different E1 circuits experience, the order of the order of receiving data frames and transmission Frame has than big difference, and fortunately, the data link layer protocol that the rearrangement work of Frame can be left in the network interface card is finished.
On hardware designs, interframe is inserted and has been saved the circuit that multichannel E1 is carried out the delay inequality alignment, but because interframe is inserted with the High level data link control Frame is that unit interleaves, transmission and receiving terminal at every road E1 all need the buffer unit of a capacity greater than maximum High level data link control Frame frame length, therefore, the slotting scheme SDRAM control circuit of interframe will be complicated a lot.
Description of drawings
Fig. 1 typical case applied environment
Fig. 2 ethernet data frame transmission system entire block diagram
Fig. 3 clock equivalent schematic
Fig. 4 sending direction flow chart
Fig. 5 receive direction flow chart
Embodiment
Fig. 1 is the typical applied environment of the reverse multiplexer of Ethernet.The Media Independent Interface signal of local area network (LAN) A converts N road E1 signal to through reverse multiplexer A, and the E1 transmission network that enters telecommunications is transmitted.At far-end, oppositely multiplexer B reverts to the Media Independent Interface signal of Ethernet to the N road E1 signal that receives, and is transmitted to local area network (LAN) B, thereby has realized the communication between two remote ethernets.
Fig. 2 is the entire block diagram of ethernet data frame transmission system.According to the direction of data flow, the function of each several part circuit is described one by one below, wherein, the mapping process from the Ethernet to E1 has been realized in circuit module (1)～(6), and the mapping process from E1 to the Ethernet has been realized in circuit module (7)～(12):
(1) Ethernet receiving circuit: the irrelevant interface data input of Ethernet receiving circuit receiver media, carry out CRC check, correct ethernet data frame is write FIFO1.
(2) FIFO1: the ethernet data frame that buffer memory Ethernet receiving circuit is sent.
(3) High level data link control framer circuit: the High level data link control framer circuit reads ethernet data frame from FIFO1, is packaged into the Frame of High level data link control.
(4) send cache control circuit: send cache control circuit 8 transmissions of poll buffer unit tFIFO1～8 successively, in the transmission buffer unit that each does not overflow as yet, write a complete High level data link control Frame.
(5) tFIFO1～8: the transmission buffer unit that these 8 FIFO are every road E1, i.e. E1 transmit buffer in the claim 1.Based on the scheme that interframe is inserted, need to give every road E1 to distribute one to send buffer unit, this capacity that sends buffer unit is at least greater than the High level data link control Frame size of 1 maximum, i.e. the 1518*2=3036 byte.
(6) the E1 transmitting element 1～8: each E1 transmitting element is reading of data from transmission buffer unit separately respectively, forms the E1 frame, and carries out the HDB3 coding, sends to the E1 line interface circuit.These 8 E1 transmitting elements are the E1 transtation mission circuit in the claim 1.
(7) the E1 receiving element 1～8: each E1 receiving element receives the E1 Frame from corresponding E1 line interface circuit, it is synchronous to carry out HDB3 decoding and E1, then the Frame of the High level data link control that solves is write reception buffer unit rFIFO1～8 separately.These 8 E1 receiving elements are the E1 receiving circuit in the claim 1.
(8) rFIFO1～8: the reception buffer unit that these 8 FIFO are every road E1, i.e. E1 reception buffer in the claim 1.Each capacity that receives buffer unit is also at least greater than the High level data link control Frame size of 1 maximum.
(9) receive cache control circuit: receive cache control circuit 8 receptions of poll buffer unit rFIFO1～8 successively, in certain reception buffer unit High level data link control Frame complete more than 1 is arranged if find, then therefrom read 1 High level data link control Frame, give High level data link control and separate the frame circuit.
(10) High level data link control is separated the frame circuit: High level data link control is separated the frame circuit and recover ethernet data frame from the High level data link control Frame, and writes FIFO2.
(11) FIFO2: the buffer memory High level data link control is separated the ethernet data frame that the frame circuit is sent.
(12) Ethernet transtation mission circuit: the Ethernet transtation mission circuit reads ethernet data frame from FIFO2, sends to ethernet interface circuit from the Media Independent Interface interface according to reference format.
These 16 buffer units of tFIFO1～8 and rFIFO1～8 are realized with a SDRAM.
Fig. 3 is the clock equivalent schematic.High-frequency clock clkh and low-speed clock clkl, clkl and en are synchronous with clkh, then utilize the rising edge of clkl to drive, and logically are equivalent under the situation that en enables, and drive with clkh.
Generally speaking, the clock number is few more, and the effect of wiring is good more.12 clocks are arranged: Ethernet receive clock, Ethernet tranmitting data register, system clock, E1 tranmitting data register, 8 E1 receive clocks in the native system.12 clocks are competed the global clock network simultaneously, will be very severe problems.For this reason, we are optimized processing to clock.
In reverse multiplexer, 8 E1 receive clocks are to utilize system clock at a high speed, recover out by the method for digital timing recovery, satisfy relation shown in Figure 3, and therefore, these 8 clocks can add with system clock and to enable to substitute.After optimizing, 12 clocks of system are reduced to 4 clocks, have alleviated the wiring complexity of global clock greatly.
Fig. 4 is the sending direction flow chart: system initialization, and i puts 0 with counter; The ethernet data frame that buffer memory receives, and carry out the High level data link control framing and handle, the High level data link control Frame generated; Detect i road E1 channel, if i road E1 channel idle, then this High level data link control Frame is sent on the E1 channel of i road, after sending counter i is added 1, detect the E1 channel that step continues to seek next road free time otherwise directly counter i is added to return after 1; If i＞n then puts i=0; Ethernet data frame returns waiting step after sending and finishing, and waits for receiving next ethernet data frame.
Fig. 5 is the receive direction flow chart: system initialization, and j puts 0 with counter; N E1 receiving element receives the E1 frame of E1 circuit separately respectively, and the High level data link control Frame data that solve are write corresponding reception buffer unit, a total n reception buffer unit; Detect j and receive buffer unit, if receive among the buffer unit j High level data link control Frame complete more than 1 arranged, then from this reception buffer unit, read 1 High level data link control Frame, carry out High level data link control and separate the ethernet data frame that frame processing back transmission solves, after sending counter j is added 1, return the detection step, otherwise directly counter j is added 1, return the detection step; If j＞n then puts j=0.
Claims (2)
1. based on the slotting ethernet data frame transmission system of interframe, it is characterized in that: this system is a kind of data frame transfer system that the method that by telecommunications network each ethernet data frame inserted by interframe on Ethernet host-host protocol basis is walked one road E1 circuit separately, comprise sending subsystem and receiving subsystem two large divisions, wherein:
The transmission subsystem comprises: the Ethernet receiving circuit that is connected with local area network (LAN) A, and FIF01, the High level data link control framer circuit sends cache control circuit, E1 transmit buffer, and E1 transtation mission circuit, wherein:
The Ethernet receiving circuit that is connected with local area network (LAN) A, cyclic redundancy check (CRC) is carried out in the data input of the irrelevant interface of this circuit receiver media, exports correct ethernet data frame;
FIF01 receives the ethernet data frame that described Ethernet receiving circuit is sent;
The High level data link control framer circuit, this circuit is a framer circuit according to the High level data link control operation, this circuit reads ethernet data frame from described FIF01, be packaged into described High level data link control predetermined data frame format, output High level data link control Frame;
Send cache control circuit, this transmission cache control circuit receives the High level data link control Frame that described High level data link control framer circuit is sent;
The E1 transmit buffer, this buffer sends buffer unit by n and forms, the method slotting according to described interframe, distribute one to send buffer unit for every road E1, each capacity that sends buffer unit is at least greater than the High level data link control Frame size of 1 maximum, described transmission cache control circuit is poll n transmission buffer unit successively, writes a complete High level data link control Frame in the transmission buffer unit that each does not overflow as yet;
The E1 transtation mission circuit, n E1 transmitting element arranged, and these E1 transmitting elements read described High level data link control Frame respectively from each corresponding described transmission buffer unit, form the E1 frame, and carry out the HDB3 coding, send to the interface circuit of E1 circuit;
Receiving subsystem comprises: the E1 receiving circuit, and the E1 reception buffer receives cache control circuit, and High level data link control is separated the frame circuit, FIF02, and the Ethernet transtation mission circuit that is connected with local area network (LAN) B, wherein:
The E1 receiving circuit has n E1 receiving element, and each receives the E1 Frame since corresponding interface circuit of described E1 circuit these E1 receiving elements, and it is synchronous to carry out HDB3 decoding and E1, and therefrom solves the High level data link control Frame;
The E1 reception buffer, there be n E1 to receive buffer unit, each receives described High level data link control Frame since corresponding E1 receiving element, described each receive buffer unit at least greater than the size of the High level data link control Frame of 1 maximum;
Receive cache control circuit, receive the cache control circuit described n of poll reception buffer unit successively, if finding has High level data link control Frame complete more than 1 in certain reception buffer unit, then from this reception buffer unit, read 1 High level data link control Frame;
High level data link control is separated the frame circuit, and this High level data link control is separated the frame circuit and recover ethernet data frame from described High level data link control Frame;
FIF02 receives described High level data link control and separates the ethernet data frame that the frame circuit is sent;
The Ethernet transtation mission circuit that links to each other with local area network (LAN) B, this Ethernet transtation mission circuit reads ethernet data frame from described FIF02, send to ethernet interface circuit from Media Independent Interface according to reference format.
2. ethernet data frame transmission system of inserting based on interframe according to claim 1 is characterized in that: described n sends buffer unit and n reception buffer unit, and 2n buffer unit realized with a SDRAM altogether.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2005100867864A CN100413288C (en) | 2005-11-04 | 2005-11-04 | System for transmitting data frame of Etheent based on insertion between frames |
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| CNB2005100867864A CN100413288C (en) | 2005-11-04 | 2005-11-04 | System for transmitting data frame of Etheent based on insertion between frames |
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| CN100413288C true CN100413288C (en) | 2008-08-20 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100574231C (en) * | 2006-10-11 | 2009-12-23 | 鸿富锦精密工业（深圳）有限公司 | Network equipment and frame processing method thereof |
| CN101753578B (en) * | 2009-12-22 | 2012-09-05 | 电信科学技术第五研究所 | ETHERNET/EI protocol conversion method and protocol converter |
| CN103701715A (en) * | 2012-09-27 | 2014-04-02 | 京信通信系统（中国）有限公司 | Method and device for sending and receiving Ethernet data packet based on multiple E1 channels |
| CN103441949B (en) * | 2013-08-07 | 2017-02-08 | 中国能源建设集团广东省电力设计研究院有限公司 | Ethernet data transmission method and system based on E1 link |
| CN110445578B (en) * | 2019-07-29 | 2020-06-23 | 广芯微电子（广州）股份有限公司 | SPI data transmission method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5892768A (en) * | 1996-09-12 | 1999-04-06 | Etherwan System, Inc. | 10/100-base ethernet to T1/E1 HDSL converter and method of operation |
| CN2421781Y (en) * | 1999-12-03 | 2001-02-28 | 杭州南望电力科技有限公司 | Receiver-transmitter for ether net-E1 signal |
| CN1302140A (en) * | 1999-12-29 | 2001-07-04 | 深圳市华为电气股份有限公司 | Data enchange device and method |
| CN1501640A (en) * | 2002-11-14 | 2004-06-02 | 北京润光泰力科技发展有限公司 | Method and system for transmitting Ethernet data using multiple E1 lines |
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2005
- 2005-11-04 CN CNB2005100867864A patent/CN100413288C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5892768A (en) * | 1996-09-12 | 1999-04-06 | Etherwan System, Inc. | 10/100-base ethernet to T1/E1 HDSL converter and method of operation |
| CN2421781Y (en) * | 1999-12-03 | 2001-02-28 | 杭州南望电力科技有限公司 | Receiver-transmitter for ether net-E1 signal |
| CN1302140A (en) * | 1999-12-29 | 2001-07-04 | 深圳市华为电气股份有限公司 | Data enchange device and method |
| CN1501640A (en) * | 2002-11-14 | 2004-06-02 | 北京润光泰力科技发展有限公司 | Method and system for transmitting Ethernet data using multiple E1 lines |
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