CN2807612Y - ADPCM digital code converter - Google Patents
ADPCM digital code converter Download PDFInfo
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- CN2807612Y CN2807612Y CNU2005200408996U CN200520040899U CN2807612Y CN 2807612 Y CN2807612 Y CN 2807612Y CN U2005200408996 U CNU2005200408996 U CN U2005200408996U CN 200520040899 U CN200520040899 U CN 200520040899U CN 2807612 Y CN2807612 Y CN 2807612Y
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Abstract
The utility model provides an ADPCM digital code converter, which comprises a PCM end E1 interface and first framer chip, an IMA-ADPCM end E1 interface and second framer chip, a CPU processor and an FPGA, wherein the FPGA comprises a clock signal reception end which can receive the clock signals of the first and the second framer chips, a frame header signal reception end which can receive the frame header signal of the first and the second framer chips, a PCM input port which can receive the PCM signals output from the first framer chip, a PCM output port which can send processed PCM signal to the first framer chip, an ADPCM input port which can receive the ADPCM signal output from the second framer chip, an ADPCM output port which can send processed ADPCM signal to the second framer chip and an addresses end which can cause a signal end and a data end to be respectively connected with a CPU processor. The utility model adopts a time multiplexing and hardware parallel processing technique and adopts a low asynchronous working clock to process 31 paths 64K PCM signals, and the utility model can accomplish IMA-ADPCM decoding and encoding.
Description
Technical field
The utility model relates to a kind of ADPCM digital coding transducer, specifically, relates in the telecommunication service at the pcm encoder of E1 link and the transducer between the IMA-ADPCM coding.
Background technology
IMA-ADPCM (Interactive Multimedia Association-Adaptive DifferentialPulse Code Modulation, Interactive Multimedia Association-self adaptation difference pulse code modulation) be a kind of a kind of lossy compression method algorithm at 16 bits (perhaps higher) sound waveform data, it with 16 bits (bit) data of each sampling in the sound stream with 4 bit storage.Because the IMA-ADPCM coding techniques has compression ratio height, less, the better simply characteristics of algorithm of distortion, is comprised in computer software, the telecommunication service so be applied to more and more.Such as the codec functions of in WINDOWS operating system, just directly supporting the IMA-ADPCM of 32Kbps.
Still the A that is based on that adopts in most telecommunication service leads the 64k PCM signal of encoding, and relative IMA-ADPCM coding when the transporting speech code signal can be wasted the line bandwidth of half like this.At present, the problem usual method that solves bandwidth waste is to use special-purpose codec chip, but the problem of Chan Shenging is like this, at first in telecommunication service based on the 2M transmission channel of a standard, G.703 the PCM signal of standard E1 interface has 31 road voice links at most, if use the IMA-ADPCM codec chip of single channel to need 31 at most.Secondly voice signal and data-signal time division multiplexing are transmitted in the E1 link often in a lot of telecommunication services, and certain 64KPCM passage transmits in a period of time probably is voice signal, what transmit in the period at another section is data-signal, and data-signal is can not be compressed.So just make the processing of using special chip to carry out encoding and decoding have significant limitation.
Novel content
The purpose of this utility model is, a kind of ADPCM digital coding transducer is provided, and overcomes to adopt the 64kPCM signal that leads coding based on A, the technical problem of wasting the line bandwidth of half when the transporting speech code signal in the present telecommunication service.
In order to achieve the above object, the technical solution of the utility model is as follows:
A kind of ADPCM digital coding transducer comprises: PCM holds the E1 interface and first framer chip, and the 2M link of 31 road pcm encoders of standard is provided; ADPCM holds the E1 interface and second framer chip, and the 2M link of 31 road IMA-ADPCM coding of standard is provided; The CPU processor; And FPGA (Field Programmable Gate Array field programmable logic array), connect first framer chip, second framer chip by the 2M data/address bus; This FPGA comprises: the clock signal receiving terminal, be connected with first framer chip, second framer chip, and receive the clock signal that first and second framer chips are delivered to FPGA; The header signal receiving terminal is connected with first framer chip, second framer chip, receives the header signal that first and second framer chips are delivered to FPGA; The PCM input port connects first framer chip, receives the PCM signal of first framer chip output; The PCM output port connects first framer chip, and the PCM signal after transmission is handled is to first framer chip; The ADPCM input port connects second framer chip, receives the ADPCM signal of second framer chip output; The ADPCM output port connects second framer chip, and the ADPCM signal after transmission is handled is to second framer chip; The address end connects the CPU processor by the cpu address line; The enable signal end connects the CPU processor by CPU enable signal line; Data terminal connects the CPU processor by cpu data bus.
First framer chip provides the 2M link of 31 road pcm encoders of standard, second framer chip provides the 2M link of 31 road IMA-ADPCM coding of standard, we just can be compressed to the PCM link that need take 31 64K time slots originally in 15.5 64K time slots through the processing of this transducer like this, have 15.5 64K time slots can be used for transmitting other data or other IMA-ADPCM link in addition.CPU is used for FPGA internal RAM (random access memory random asccess memory) district is configured, to determine the corresponding relation of each time slot in two E1 links.FPGA is the nucleus module of transducer, finishes the conversion of encoding between PCM and IMA-ADPCM.This transducer adopts time-sharing multiplex and hardware parallel processing technique, only adopts lower asynchronous working clock (10M-12M), handles the PCM signal of 31 road 64K, realizes IMA-ADPCM digital coding and the G.703 conversion between the PCM digital coding of standard E1 interface.Its major function is to be finished by FPGA, and can control each time slot passage neatly and whether carry out coding-decoding operation.
The header signal that described first and second framer chips are delivered to FPGA is identical.
Described FPGA comprises ADPCM time slot sending module, PCM time slot receiver module, core processing module, ADPCM time slot receiver module and PCM time slot sending module; The header signal receiving terminal connects above-mentioned five modules respectively; The clock signal receiving terminal connects ADPCM time slot sending module, PCM time slot receiver module, ADPCM time slot receiver module and PCM time slot sending module respectively; PCM time slot receiver module connects the PCM input port; Core processing module link address end, enable signal end and data terminal; ADPCM time slot receiver module connects the ADPCM input port; The input of core processing module connects PCM time slot receiver module and ADPCM time slot receiver module respectively, and output connects ADPCM time slot sending module and PCM time slot sending module respectively.By interrupting carrying out exchanges data, can make the processing of core processing module simpler like this between core processing module and other four modules, and can carry out that RAM is multiplexing easily, reduce taking the FPGA resource.
Described ADPCM time slot sending module connects the ADPCM output port by first adder; One input of this adder connects the header signal receiving terminal, and adpcm data to be sent is carried out parallel/serial conversion.
Described PCM time slot sending module connects the PCM output port by second adder; One input of this adder connects the header signal receiving terminal, and PCM data to be sent are carried out parallel/serial conversion.
Described core processing module has clock port, links to each other with work clock.
Described core processing module comprises that A leads inverse transform block, computing module, A and leads conversion module, configuration module and coding/decoding module; Described coding/decoding module connects A respectively and leads inverse transform block, computing module, A and lead conversion module and configuration module.
Description of drawings
Fig. 1 is an ADPCM digital coding commutator principle block diagram of the present utility model;
Fig. 2 is the FPGA internal circuit schematic diagram of ADPCM digital coding transducer of the present utility model;
Fig. 3 is the circuit theory diagrams of the utility model ADPCM digital coding converter core processing module.
Embodiment
For the ease of understanding 26S Proteasome Structure and Function of the present utility model better, be elaborated below in conjunction with Fig. 1 to Fig. 3.
ADPCM digital coding transducer of the present utility model adopts time division multiplexing and hardware parallel processing technique, only adopts lower asynchronous working clock (10M-12M), handles the PCM signal of 31 road 64K, realizes the IMA-ADPCM encoding and decoding.Because main processing module has adopted the FPGA realization, can control each time slot passage flexibly and whether carry out coding-decoding operation.
ADPCM digital coding commutator principle block diagram of the present utility model mainly comprises PCM end E1 interface and framer chip CHIP1, ADPCM end E1 interface and framer chip CHIP2, a FPGA and a CPU as shown in Figure 1.
The header signal receiving terminal FL of FPGA connects the CHIP11 port of CHIP1 and the CHIP21 port of CHIP2 respectively by the 2M data wire, receives the header signal that CHIP1 and CHIP2 deliver to FPGA.The clock signal receiving terminal CLK of FPGA connects the CHIP12 port of CHIP1 and the CHIP22 port of CHIP2 respectively by the 2M data wire, receives the 2M clock signal that CHIP1 and CHIP2 deliver to FPGA.The PCMI port of FPGA receives the PCM signal of CHIP1 output by the CHIP13 port of 2M data wire connection CHIP1.The ADPCMI port of FPGA receives the ADPCM signal of CHIP2 output by the CHIP23 port of 2M data wire connection CHIP2.The PCMO port of FPGA sends the PCM signal to CHIP1 by the CHIP14 port of 2M data wire connection CHIP1.The ADPCMO port of FPGA sends the ADPCM signal to CHIP2 by the CHIP24 port of 2M data wire connection CHIP2.The address end AD of FPGA links to each other with the CPU1 port of CPU by the cpu address line.The enable signal end SI of FPGA links to each other with the CPU2 port by CPU enable signal line.The data terminal DA of FPGA links to each other with the CPU3 port by cpu data bus.
CHIP1 provides the 2M link of 31 road pcm encoders of standard, CHIP2 provides the 2M link of 31 road IMA-ADPCM coding of standard, we just can be compressed to the PCM link that need take 31 64K time slots originally in 15.5 64K time slots through the processing of this transducer like this, have 15.5 64K time slots can be used for transmitting other data or other IMA-ADPCM link in addition.CPU is used for FPGA internal RAM district is configured, to determine the corresponding relation of each time slot in two E1 links.FPGA is the nucleus module of transducer, finishes the conversion of encoding between PCM and IMA-ADPCM.
The algorithm that the IMA-ADPCM of standard is mentioned in the front is the sound waveform data that are used for handling 16bit, and the PCM signal leads that inverse transformation obtains through A is the sound waveform data of 13bit, so just need be to the correct of IMA-ADPCM algorithm, enable to handle the sound waveform data of 13bit, also will guarantee compatibility simultaneously with canonical algorithm.
Because nucleus module in this transducer is FPGA, the function ratio that provides of E1 interface and framer chip CHIP1, CHIP2 and CPU is more single, so here realize being described in detail with regard to the design of FPGA inside.FPGA internal circuit schematic diagram such as Fig. 2.
As shown in Figure 2, FPGA comprises ADPCM time slot sending module 1, PCM time slot receiver module 2, core processing module 3, ADPCM time slot receiver module 4 and PCM time slot sending module 5.
Clock signal receiving terminal CLK connects the clock signal receiving terminal 11 of ADPCM time slot sending module 1, the clock signal receiving terminal 21 of PCM time slot receiver module 2, the clock signal receiving terminal 41 of ADPCM time slot receiver module 4 and the clock signal receiving terminal 51 of PCM time slot sending module 5 respectively, from E1 interface and framer chip, receive the 2M clock signal, be sent among the FPGA.
Header signal receiving terminal FL connects the header signal receiving terminal 11 of ADPCM time slot sending module 1, the header signal receiving terminal 21 of PCM time slot receiver module 2, the header signal receiving terminal 32 of core processing module 3, the header signal receiving terminal 41 of ADPCM time slot receiver module 4 and the header signal receiving terminal 51 of PCM time slot sending module 5 respectively, from E1 interface and framer chip, receive header signal, be sent among the FPGA.The header signal of two E1 interfaces and framer chip is identical.
The input port A11 of adder A1 connects the data output end 14 of ADPCM time slot sending module 1, and another input port A12 connects header signal receiving terminal FL.Pass to port ADPCMO after the stack of adpcm data after adder A1 will handle and header signal, re-send in the E1 link in each time slot, export to E1 interface and framing chip.
The input port A21 of adder A2 connects the data output end 54 of PCM time slot sending module, and another input port A22 connects header signal receiving terminal FL.Pass to port PCMO after the stack of PCM data after adder A2 will handle and header signal, re-send in the E1 link in each time slot, export to E1 interface and framing chip.
The data-out port 38 of core processing module 3 links to each other with the data-in port 13 of ADPCM time slot sending module 1, and data-out port 37 links to each other with the data-in port 53 of PCM time slot sending module 5.
The PCM signal receiving end 23 of PCM time slot receiver module 2 links to each other with port PCMI, and data-out port 24 links to each other with the data-in port 31 of core processing module 3.The ADPCM signal receiving end 43 of ADPCM time slot receiver module 4 links to each other with port ADPCMI, and data-out port 44 links to each other with the data-in port 33 of core processing module 3.Core processing module 3 also has clock port 39, and CLK links to each other with port, and FPGA adopts the 10M clock as work clock.Port 34 links to each other with port AD, and port 35 links to each other with port SI, and port 36 links to each other with port DA.
By interrupting carrying out exchanges data, can make the processing of core processing module 3 simpler like this between core processing module 3 and other four modules, and can carry out that RAM is multiplexing easily, reduce taking the FPGA resource.PCM time slot receiver module 2 is finished from the E1 link and to be received the PCM data in each time slot, and carries out serial/parallelly, send core processing module to handle.PCM time slot sending module 1 is finished PCM data to be sent is carried out parallel/serial conversion, delivers in the E1 link in each time slot, exports to E1 interface and framing chip CHIP1.ADPCM time slot receiver module 4 is finished from the E1 link and is received adpcm data in each time slot, and carries out serial/parallelly, send core processing module 3 to handle.ADPCM time slot sending module 1 is finished adpcm data to be sent is carried out parallel/serial conversion, delivers in the E1 link in each time slot, exports to E1 interface and framing chip CHIP2.
The circuit theory diagrams of core processing module 3 as shown in Figure 3.Consult Fig. 3, core processing module 3 comprises that A leads inverse transform block, coding/decoding module, computing module, A and leads conversion module and TRABLE_ROM module.Data-in port 31 connects A and leads inverse transform block.Header signal receiving terminal 32, data-in port 33, data-out port 38 and clock port 39 are connected coding/decoding module.A leads conversion module and connects data-out port 37.TRABLE_ROM module connectivity port 34,35,36.Coding/decoding module connects A respectively and leads inverse transform block, computing module, A and lead conversion module and configuration module (TRABLE_ROM module).
A leads inverse transform block and finishes the A of PCM data and lead inverse transformation, obtains the crude sampling value SIM_IN of 13bit.Coding/decoding module is used for finishing the encoding and decoding work of ADPCM, and finishes accessing operation to each channel data according to the configuration data in the TRABLE_ROM module.Computing module is finished the addition and subtraction operation of tape symbol computing, for coding/decoding module provides calculate platform.The TRABLE_ROM module realizes a block RAM space in FPGA inside, and can be disposed by CPU, to determine the corresponding relation of each time slot in two E1 links.A leads conversion module and will finish crude sampling value SIM_OUT and carry out being sent to data-out port 37 after A leads conversion.
Though embodiment of the present utility model has illustrated and has been shown and describes, should be appreciated that and know the various modifications that those skilled in the art make the utility model or substitute, do not break away from protection range of the present utility model.
Claims (6)
1. an ADPCM digital coding transducer is characterized in that, comprising:
PCM holds the E1 interface and first framer chip, and the 2M link of 31 road pcm encoders of standard is provided;
IMA-ADPCM holds the E1 interface and second framer chip, and the 2M link of 31 road IMA-ADPCM coding of standard is provided;
The CPU processor; And
FPGA connects first framer chip, second framer chip by the 2M data/address bus; This FPGA comprises:
The clock signal receiving terminal is connected with first framer chip, second framer chip, receives the clock signal that first framer chip and second framer chip are delivered to FPGA;
The header signal receiving terminal is connected with first framer chip, second framer chip, receives the header signal that first framer chip and second framer chip are delivered to FPGA;
The PCM input port connects first framer chip, receives the PCM signal of first framer chip output;
The PCM output port connects first framer chip, and the PCM signal after transmission is handled is to first framer chip;
The ADPCM input port connects second framer chip, receives the ADPCM signal of second framer chip output;
The ADPCM output port connects second framer chip, and the ADPCM signal after transmission is handled is to second framer chip;
The address end connects the CPU processor by the cpu address line;
The enable signal end connects the CPU processor by CPU enable signal line;
Data terminal connects the CPU processor by cpu data bus.
2. ADPCM digital coding transducer as claimed in claim 1, it is characterized in that described field programmable logic array comprises ADPCM time slot sending module, PCM time slot receiver module, core processing module, ADPCM time slot receiver module and PCM time slot sending module;
The header signal receiving terminal connects above-mentioned five modules respectively; The clock signal receiving terminal connects ADPCM time slot sending module, PCM time slot receiver module, ADPCM time slot receiver module and PCM time slot sending module respectively;
PCM time slot receiver module connects the PCM input port; Core processing module link address end, enable signal end and data terminal; ADPCM time slot receiver module connects the ADPCM input port;
The input of core processing module connects PCM time slot receiver module and ADPCM time slot receiver module respectively, and output connects ADPCM time slot sending module and PCM time slot sending module respectively.
3. ADPCM digital coding transducer as claimed in claim 2 is characterized in that, described ADPCM time slot sending module connects the ADPCM output port by first adder; One input of this adder connects the header signal receiving terminal.
4. as claim 2 or 3 described ADPCM digital coding transducers, it is characterized in that described PCM time slot sending module connects the PCM output port by second adder; One input of adder connects the header signal receiving terminal.
5. ADPCM digital coding transducer as claimed in claim 4 is characterized in that described core processing module has clock port, links to each other with work clock.
6. ADPCM digital coding transducer as claimed in claim 5 is characterized in that, described core processing module comprises that A leads inverse transform block, computing module, A and leads conversion module, configuration module and coding/decoding module; Described coding/decoding module connects A respectively and leads inverse transform block, computing module, A and lead conversion module and configuration module.
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2005200408996U CN2807612Y (en) | 2005-04-15 | 2005-04-15 | ADPCM digital code converter |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2005200408996U CN2807612Y (en) | 2005-04-15 | 2005-04-15 | ADPCM digital code converter |
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| CN2807612Y true CN2807612Y (en) | 2006-08-16 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102682772A (en) * | 2012-03-20 | 2012-09-19 | 华为技术有限公司 | Data sending method, data receiving method, data sending equipment and data receiving equipment |
| CN102737140A (en) * | 2011-12-22 | 2012-10-17 | 云南大学 | FPGA (Field Programmable Gata Array)-based IMA-ADPCM (Adaptive Differential Pulse Code Modulation) codec IP core design realization |
| CN103560851A (en) * | 2013-10-28 | 2014-02-05 | 深圳市冠标科技发展有限公司 | Method for wireless audio single-frequency multichannel transmission |
-
2005
- 2005-04-15 CN CNU2005200408996U patent/CN2807612Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102737140A (en) * | 2011-12-22 | 2012-10-17 | 云南大学 | FPGA (Field Programmable Gata Array)-based IMA-ADPCM (Adaptive Differential Pulse Code Modulation) codec IP core design realization |
| CN102682772A (en) * | 2012-03-20 | 2012-09-19 | 华为技术有限公司 | Data sending method, data receiving method, data sending equipment and data receiving equipment |
| CN103560851A (en) * | 2013-10-28 | 2014-02-05 | 深圳市冠标科技发展有限公司 | Method for wireless audio single-frequency multichannel transmission |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20060816 Termination date: 20130415 |