CN1411283A - Full digitize, high resolution, multi interface multi media transmission encipherer and decoder - Google Patents
Full digitize, high resolution, multi interface multi media transmission encipherer and decoder Download PDFInfo
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Abstract
A multimedia transmission coder/decoder of fully digitalized, high resolution and multiple interfaces in which the control circuit is composed of coder and decoder with DSP as the central processor made in American Texas apparatus company, the surrounding equipments of DSP include microprocessor MCU, buffer and outside memory SDRAM; DSP connects with ROM, USB interface controller and 10 Base T/100 Base T interface controller by the buffer, and digital signal processor DSP is connected with E1 interface controller directly by hexagram seam less connection. The said device supports multimedia service integrated transfer of positive andio, video, data service and negative audio, data service etc. and supports USB ,10 Base T/100 Base T, E1/T1 many kinds of interface transmission.
Description
Technical field
The present invention relates to the multimedia transmission coding/decoding device of a kind of total digitalization, high-resolution, many interfaces, exactly, relate to a kind of digitlization that can solve multimedia service, real-time Transmission high-resolution motion image sequence, and the codec that on multiple interfaces such as E1/T1, USB, 10BaseT/100BaseT, transmits multimedia services such as forward audio frequency, video, data and reverse audio frequency, data.Belong to the multimedia telecom equipment technical field.
Background technology
In existing multimedia coding-decoder, can both support vision signal (camera review) and audio signal (full duplex intercommunication telephone voice signal or broadcast speech signal etc.) greatly, but can support multimedia service (forward audio frequency, video, data service, oppositely audio frequency, data service) multimedia coding-decoder of comprehensive transmission is not seldom seen approved product yet on market.Therefore, the realization of multimedia service is at present normally worked together simultaneously by a plurality of separate operation systems (as data operation system, supervisory control system, communication system etc.) and is finished jointly.Operation department will carry out integrated service like this, the transmission that just needs separate system of the many covers of construction and network could realize video, audio frequency, data.This present situation, the maintenance of not only cost height, and system are also quite difficult.Because this multinomial business function of piecing together, interlock is poor in real time, stability is lower, also image and the nonsynchronous phenomenon of sound occur through regular meeting.In addition, the greatest drawback of this mode is that network management and control ratio are difficult, and the initial investment expense is huge.
At present, the transmission bandwidth that existing high resolution multimedia codec needs is mostly at 4Mbit/s to 19Mbit/s, even wideer frequency band; All can not under the condition that is lower than the 2Mbit/s code check,, realize transmitting in real time 720 * 576 high-definition picture with adaptive frame per second.That is to say that present most of multimedia coding-decoders are difficult in the specification requirement that realizes the real-time Transmission high-definition picture under the low bandwidth.Moreover, existing most of multimedia coding-decoder is normally at concrete application and development and design, usually can only support the application of single face, and do not support the transmission (as USB, 10BaseT/100BaseT, E1/T1 etc.) of multiple interfaces, the application of these equipment in multiple Integrated Solution is restricted and influences.
Summary of the invention
The purpose of this invention is to provide and a kind ofly can overcome multimedia transmission coding/decoding device above-mentioned multinomial defective, that realize total digitalization, high-resolution, many interfaces.This device can be supported forward audio frequency, video, data service and the oppositely comprehensive transmission of multimedia services such as audio frequency, data service, and its multi-service inserts the service quality that can guarantee various access service, the image resolution ratio height, transmission can also be supported, the autgmentability and the reliability of system can be guaranteed as USB, 10BaseT/100BaseT, E1/T1 multiple interfaces.
The object of the present invention is achieved like this: a kind of multimedia transmission coding/decoding device of realizing total digitalization, high-resolution, many interfaces, and its control circuit is made up of encoder two parts; It is characterized in that: described encoder all is to adopt digital signal processor DSP as central processing unit, and the ancillary equipment of each digital signal processor DSP comprises microprocessor MCU, buffer and external memory storage SDRAM; This digital signal processor DSP is connected with by buffer: starting ROM, usb interface controller and 10BaseT/100BaseT interface controller, then is directly to adopt six line seamless links between digital signal processor DSP and the E1 interface controller.
Described digital signal processor DSP is the chip that TIX produces, and its model is TMS320C620X, TMS320C621X, TMS320C670X, TMS320C671X series.
The model of described E1 interface controller chip is DS21354/21554, and the receive clock RCLK of this chip, reception data RSER, received frame synchronizing signal RSYNC, tranmitting data register TCLK, transmission data TSER and transmit frame synchronizing signal FSYNC realize seamless link with CLKR, DR, FSR, CLKX, DX and FSX six lines of described digital signal processor DSP chip respectively.
Described encoder section control circuit also includes: the mpeg 2 encoder that is connected with digital signal processor DSP by the sequential logic interface circuit, be connected to the mpeg 2 encoder input respectively, audio A/D transducer as the analogue audio frequency input interface, the video a/d converter of analog video input interface and digital audio/video input interface, the video coding memory storage SDRAM and the external memory storage SDRAM that are connected with mpeg 2 encoder, with the direct-connected Data Input Interface of digital signal processor DSP, reverse data output interface and reverse audio D/A converter, the latter is as reverse audio output interface.
The model of described mpeg 2 encoder chip is: MB86390, the model of audio A/D converter chip is: PCM1800, the model of video a/d converter chip is: SAA7113.
Described sequential logic interface circuit is formed with programmable logic device (CPLD); This sequential logic interface circuit is connected to digital signal processor by described buffer.
Described decoder section control circuit also includes: the MPEG2 decoder that is connected with digital signal processor DSP by the sequential logic interface circuit, be connected to MPEG2 decoder output respectively, audio D/A converter as the analogue audio frequency output interface, the video d/a transducer of analog video output interface and digital audio/video output interface, the video decode memory storage SDRAM and the external memory storage SDRAM that are connected with the MPEG2 decoder, with the direct-connected data output interface of digital signal processor DSP, reverse data input interface and reverse audio D/A converter, the latter is as reverse audio input interface.
The model of described MPEG2 decoder chip is: MB87L2250, the model of audio D/A converter chip is: PCM1723, the model of video d/a converter chip is: SAA7128.
Described sequential logic interface circuit is formed with programmable logic device (CPLD), and this sequential logic interface circuit is to be connected to digital signal processor by described buffer.
Advantage of the present invention is many-sided: at first, this device is that the multiple business of a collection is the system equipment of one, the multimedia service that this device is supported includes: forward audio frequency, video, data service and the oppositely comprehensive transmission of audio frequency, data service, and, its multi-service inserts the service quality that can guarantee every kind of access service, can also guarantee the autgmentability and the reliability of system.Owing to height integration of the present invention, improved the ability of validity, promptness and the fast processing accident of whole system device greatly, these performances also are distinctive marks of modern multimedia system intelligent management.In addition, owing to the present invention does not need to lay other communication links in addition, so significantly reduced expense costs such as procuring equipment, link construction and working service on the whole.
Secondly, the present invention supports multiple interfaces such as USB, 10BaseT/100BaseT, E1/T1, use this device can realize multiple transmission plan easily, for example can be used for system integration schemes such as long distance control system, DVR, video server, help the application of sorts of systems integrator.
Moreover the present invention can be lower than under the transmission conditions of 2Mbit/s the coding of video section, realizes transmitting with the high-resolution of adaptive frame per second and 720 * 576 specification requirement of realtime graphic.So the present invention can realize the Integrated Solution of real-time Transmission high-definition picture quickly and easily under the low bandwidth condition, make the investment of operator on channel save greatly.
In addition, the present invention is at hardware aspect, because adopting DSP is that interface is changed, realized seamless link with the e1 controller chip, hardware circuit is simple, realizes easily reliable operation, for industrialization of the present invention provides good ratio of performance to price advantage, has good popularization and application prospect.
Description of drawings
Fig. 1 is the encoder circuit block diagram among the present invention.
Fig. 2 is the decoder circuit block diagram among the present invention.
Fig. 3 is the electrical schematic diagram of DSP device and peripheral circuit thereof in the encoder control circuit among the present invention.
Fig. 4 is the control circuit electrical schematic diagram of the forward audio/video coding among the present invention.
Fig. 5 is the control circuit electrical schematic diagram of the forward audio/video decoding among the present invention.
Fig. 6 is the logical circuit electrical schematic diagram of the E1 interface controller among the present invention.
Fig. 7 is the logical circuit electrical schematic diagram of the usb interface controller among the present invention.
Fig. 8 is the logical circuit electrical schematic diagram of the network interface controller among the present invention.
Embodiment
The present invention is a kind of multimedia transmission coding/decoding device of realizing total digitalization, high-resolution, many interfaces, and its control circuit is made up of encoder two parts; Wherein encoder all is to adopt digital signal processor DSP (the Digital Signal Processor) chip of TIX's production as central processing unit, its model is TMS320C620X, TMS320C621X, TMS320C670X, TMS320C671X series, and the ancillary equipment of each digital signal processor DSP comprises microprocessor MCU, buffer and external memory storage SDRAM (referring to Fig. 3); This digital signal processor DSP is connected with by buffer: starting the usb interface controller and the 10BaseT/100BaseT interface controller (referring to Fig. 1 and Fig. 2) of ROM, transmitted in both directions, then is directly to adopt six line seamless links (referring to Fig. 6) between digital signal processor DSP and the E1 interface controller.
Below in conjunction with each accompanying drawing, specifically introduce the control circuit structure and the operation principle thereof of encoder among the present invention.
Referring to Fig. 1 and Fig. 4, at first introduce the forward of encoder and the control circuit of reverse multimedia service I/O, encoder of the present invention can be supported the audio-video signal of analog or digital, wherein digital audio-video signal can be from digital audio/video interface directly as the input signal of MPEG2 (Moving Picture Experts Group) encoder 15, simulated audio signal then needs to carry out digital-to-analogue conversion through the simulated audio signal that audio A/D transducer (model is PCM1800) is imported left and right acoustic channels, by its DOUT pin output digital signal, give mpeg 2 encoder 15 (model is MB86390) and encode.It is digital signal that analog video signal can carry out analog-to-digital conversion by S terminal or C terminal input video A/D converter (model is SAA7113), then its video signal sampling clock LLC, horizontal-drive signal RTSO, output field synchronizing signal RTSI, digital video signal VPO7～0 pin is connected to the corresponding video interface of mpeg 2 encoder 15 (model is MB863907) respectively, so that to the encoding digital signals of its output.The audio-video signal of analog or digital is added the data input, has constituted the multimedia service input of forward jointly.Oppositely audio frequency output and reverse data output has constituted reverse multi-service output jointly.
Be input to the SYSCLK pin of audio A/D transducer (model is PCM1800) and the ASCLK pin of encoder 15 audio interface by the external clock source signal, and two clock signals of the audio interface ACLK of encoder 15, ALRCK pin output are connected to BCK, the LRCK pin of PCM1800.These three clock signals are used to refer to the sample rate of PCM1800.
Forward audio frequency and video input signal is behind mpeg 2 encoder 15 codings, output meets TS (Transport Stream)/PS (Program Stream) stream of MPEG2 standard, because the logic of external memory interface EMIF (ExternalMemory Interface) on sequential of the digital signal processor DSP device 10 that its interface sequence and the present invention adopt is inconsistent, so between the two, the present invention adopts a slice programmable logic device (CPLD) (Complex Programmable Logic Device) 16 to realize as the sequential logic interface circuit.Referring to Fig. 4, mpeg 2 encoder 15 (model is MB86390) has with the signal of sequential logic interface circuit 16 interconnection: STCLK-flows clock signal, STEN-stream output useful signal, STDATA7～0-TS/PS flows signal, and TSPSSYNC-TS/PS flows synchronizing signal.Finish mpeg 2 encoder 15 (model is MB86390) and DSP device 10 after the conversion on the sequential logic through CPLD sequential logic interface circuit 16, again data flow is sent into the DSP device.Because DSP is to use asynchronous serial interface to be connected with CPLD, for guarantee encoder 15 (model is MB86390) and DSP on sequential logic synchronously, also will flow clock signal STCLK and be connected to EXT_INT and the TINP pin of DSP, and use interruption or the incident of DSP to realize synchronously.In order to make the encoder 15 can operate as normal, MB86390 also should connect SDRAM and be used for the SDRAM of video decode, and its circuit connects referring to Fig. 4, because be custom circuit, this paper does not give unnecessary details.
Fig. 4 has showed that also the pin that buffer 12 is connected with CPLD16: ED8～0-TS/PS flows input signal, EA21～2-address signal, CE-chip selection signal, AWE-asynchronous write signal, the asynchronous gating signal of AOE-.The effect of microcontroller MCU among Fig. 4 (model is MB90F591) 11 is by the running parameter of serial ports configuration codes device (model is MB86390) 15, passes through I
2The running parameter of C mouth configuration video a/d converter (model is SAA7113).
The following describes the DSP device 10 and the peripheral circuit thereof of encoder among the present invention, referring to Fig. 1, the TS/PS stream behind the forward audio frequency and video input signal coding together enters DSP device 10 through after cushioning with the forward data input.DSP device 10 of the present invention is TMS320C620X, TMS320C621X, TMS320C670X, TMS320C671X series of products that TIX produces.After this DSP device 10 is packed complex data, can select different interface output respectively according to channel transmitted.For example: DSP can send packing data to E1/T1 Interface controller chip 19, by it data is delivered to the E1/T1 channel.In like manner, DSP also can send packing data to usb interface controller chip 17 or 10BaseT/100BaseT interface controller chip 18 through buffer 12, data is delivered on USB channel or the 10BaseT/100BaseT network channel respectively by them and is transmitted.
Simultaneously, the reverse audio signal of coming through corresponding USB, E1,10BaseT/100BaseT channel by decoder 20 and the superpacket of reverse data, after 17,18,19 receptions of corresponding interface controller chip, output to DSP device 10, after unpacking by DSP device 10, output to reverse audio D/A converter and reverse data port respectively, finished reverse multi-service transmission.
Referring to Fig. 3, because the external memory interface EMIF of the DSP device 10 in the encoder control circuit will connect a plurality of outputs: the sequential logic interface circuit 16 that starts rom chip 14, usb interface controller chip 17,10Base controller chip 18 and constitute by CPLD, the former buffer 12 that is provided with links to each other with load after first data to its output cushion again.For the ease of the mutual communication between MCU chip 11 and the DSP device 10, the INT pin of MCU chip 11 is connected with the HPI of DSP device 10 (Host PortInterface) interface.Other pins of HPI (Host Port Interface) interface are received the general purpose I of MCU chip 11/O pin.In order to make DSP device 10 operate as normal, DSP also should connect SDRAM chip 13 and start rom chip 14.The EMIF interface of DSP directly links to each other with SDRAM.The EMIF interface of DSP links to each other with startup rom chip 14 through after the buffer 12 again.In addition, be convenient to artificial debugging in order to make the DSP device, the present invention has added the JTAG mouth in hardware designs.Because above-mentioned various connections are custom circuit, this paper repeats no more.
Here need to prove: the encoder among the present invention is in many interface control circuits, it is on all four that the DSP device is connected with hardware between each interface controller chip, be that control logic circuit on DSP device and E1/T1 Interface, USB interface, the 10BaseT/100BaseT network interface is on all four, so, this paper lumps together the unified explanation of do to many interface control circuits of encoder, describes no longer respectively.
Realize the circuit diagram of six line seamless links referring to dsp chip of the present invention shown in Figure 6 10 (20) and E1/T1 Interface controller 19 (29).Wherein E1 is 32 road PCM standards, and T1 is 24 road PCM standards.Because the receive clock RCLK of E1 interface controller chip 19 (29) (model is DS21354/21554), reception data RSER, received frame synchronizing signal RSYNC, tranmitting data register TCLK, transmission data TSER, transmit frame synchronizing signal FSYNC have the sequential of the multichannel serial line interface MCBSP (Multi-Channel Buffered Serial Port) of buffering to fit like a glove respectively with in the dsp chip 10 (20), can realize six line seamless links.Therefore, above-mentioned six pins are connected with CLKR, DR, FSR, CLKX, DX and the FSX pin of DSP device 10 (20) respectively.The TRING of E1 interface controller 19 (29) (model is DS21354/21554), TTIP pin send data, are sent on the E1 channel after E1 sends transformer.Data from the E1 channel is come are then received by the RRING of E1 interface controller 19 (29), RTIP pin via the E1 receiving transformer.
Referring to Fig. 7, the external memory interface EMIF of the DSP device 10 (20) among the present invention through buffering after, be connected by the output and the usb interface controller chip 17 (27) (model is SL811HS) of buffer 12 (22), and adopt asynchronous sequential logic.The pin that buffer 12 (22) outputs are connected with SL811HS chip 17 (27) has: ED8～0-forwards/reverse superpacket data, EA2-address signal, CE-chip selection signal, the asynchronous read signal of ARE-, AWE-asynchronous write signal.The present invention also is connected to the INTRQ pin of SL811HS chip 17 (27) the EXT_INT pin of DSP device 10 (20), uses the interruption of DSP to manage the USB incident.SL811HS chip 17 (27) is connected to the USB channel by DATA+ and DATA-, carries out the reception and the transmission of data.
Referring to Fig. 8, the external memory interface EMIF of the DSP device 10 (20) among the present invention through buffering after, be connected by the output and the 10BaseT interface controller chip 18 (28) (model is CS8900) of buffer 12 (22), and adopt asynchronous sequential logic.The pin that buffer 12 (22) outputs are connected with CS8900 chip 18 (28) has: ED15～0-forwards/reverse superpacket data, EA21～2-address signal, CE-chip selection signal, the asynchronous read signal of ARE-, AWE-asynchronous write signal.The present invention also is connected to the INTRQ pin of CS8900 chip 18 (28) the EXT_INT pin of DSP device 10 (20), uses the interruption of DSP to manage the 10BaseT incident.The TXD+ of CS8900 chip 18 (28), TXD-pin send data, send transformer via network and are sent on the 10BaseT EtherChannel.Then pass through the network receiving transformer by the RXD+ of CS8900 chip 18 (28), the reception of RXD-pin from the data that the 10BaseT EtherChannel transmits.
Introduce the control circuit that decoder forward multimedia service is exported and reverse traffic is imported among the present invention below, referring to Fig. 2 and Fig. 5, decoder of the present invention is supported the audio-video signal output of analog or digital, it can also can pass through the digital audio-video signal from the 25 decoding outputs of MPEG2 decoder chip respectively audio D/A converter (model is PCM1723) and video d/a transducer (model is PCM1723) and be converted to analogue audio frequency and vision signal output from MPEG2 decoder chip 25 through digital audio/video interface output digital audio-video signal.The audio-video signal output of analog or digital adds data output, has constituted the multimedia service output of forward jointly.Oppositely audio frequency input and reverse data input constituted reverse multi-service input jointly.
Because the TS/PS stream of logical AND MPEG2 decoder chip 25 (model the be MB87L2250) output of the external memory interface EMIF of the digital signal processor DSP device 20 that adopts in the decoder control circuit of the present invention on sequential is inconsistent, so the present invention adopts a slice programmable logic device (CPLD) (Complex Programmable Logic Device) chip 26 to realize as the sequential logic interface circuit between the two.Referring to Fig. 5, need to prove that DSP device 20 is earlier the coherent signal of its output to be delivered to after the buffer 22, send CPLD chip 26 again to.Buffer 22 has with the pin that CPLD chip 26 is connected: ED8～0-TS/PS flows output signal, EA21～2-address signal, CE-chip selection signal, AWE-asynchronous write signal, the asynchronous gating signal of AOE-.The sequential logic interface circuit that is made of CPLD chip 26 is finished the conversion on the sequential logic, the TS/PS stream that DSP device 20 just will meet the MPEG2 standard send and passes to MPEG2 decoder chip 25, MPEG2 decoder chip 25 has with the signal of sequential logic interface circuit 26 interconnection: TS_CLK-flows input clock signal, TS_EN-stream input useful signal, TSDATA7～0-TS/PS flows signal, and TSPSTART-TS/PS flows synchronizing signal.Because DSP device 20 uses asynchronous serial interface to be connected with CPLD chip 26, for guarantee decoder 25 (model is MB87L2250) and DSP device 20 on sequential logic synchronously, also EXT_INT and the TNP pin with DSP is connected to CPLD, uses interruption or the incident of DSP to realize synchronously.In order to make the decoder 25 (model is MB87L2250) can operate as normal, this device also should connect SDRAM and be used for the SDRAM of video decode, and its circuit connects referring to Fig. 5, owing to be custom circuit, this paper does not give unnecessary details.The audio-video signal of the forward TS/PS stream decoded device 25 of signal (model is MB87L2250) decoding back output can directly be exported from digital audio/video interface, also can be converted to analog signal output through audio D/A converter and video d/a transducer again.
Referring to Fig. 5, the AODATA pin output audio signal of MB87L2250 audio interface is to the DIN pin of audio D/A converter (model is PCM1723).The AOCLK of MB87L2250 audio interface, AOBCLK, three pins of AOLRCK are exported clock signal separately respectively, are sent to SCKO, the BCLKIN of audio D/A converter (model is PCM1723), three pins of LRCIN.These three clock signals are used to refer to the sample rate of PCM1723 device.The audio analog signals of the VOUTL of PCM1723, VOUTR pin output left and right acoustic channels.
Digital video signal VO_D7～0 of the video interface of MB87L2250, vertical synchronizing signal VOHSYNC, horizontal-drive signal VOVSYNC, each pin of video signal sampling clock VOPCLK are connected with MP7～0, RCV2, RCV1, the LLC pin of video d/a transducer (model is SAA7128) respectively.Analog video signal can output to the S terminal by Y, the C pin of SAA7128 device, also can output to the C terminal by the CVBS pin of SAA7128.Microcontroller MCU chip 21 among Fig. 5 (model is MB90F591) effect is to pass through I
2The running parameter of C mouth configuration decoder chip 20 is also finished the row configuration to video d/a transducer (model is SAA7128) running parameter.
Referring to Fig. 3, DSP device 20 in the decoder and peripheral circuit thereof be with encoder in situation just the same, because the external memory interface EMIF of this DSP device 20 will connect a plurality of outputs: the sequential logic interface circuit 26 that starts rom chip 24, usb interface controller chip 27,10Base controller chip 28 and constitute by CPLD, the former buffer 22 that is provided with links to each other with load after first data to its output cushion again.For the ease of the mutual communication between MCU chip 21 and the DSP device 20, the INT pin of MCU chip 21 is connected with the HPI of DSP device 20 (Host Port Interface) interface.Other pins of HPI (Host Port Interface) interface are received the general purpose I of MCU chip 21/O pin.In order to make DSP device 20 operate as normal, DSP also should connect SDRAM chip 23 and start rom chip 24.The EMIF interface of DSP directly links to each other with SDRAM.The EMIF interface of DSP links to each other with startup rom chip 24 through after the buffer 22 again.In addition, be convenient to artificial debugging, in hardware designs, added the JTAG mouth in order to make DSP device 20 of the present invention.Because above-mentioned various connections are custom circuit, this paper repeats no more.
The present invention has developed performance prototype and has experimentized, simulates and implement and try out, facts have proved of test, this device can be lower than under the code check condition of 2Mbit/s, realization is with more than 352 * 288 (352 * 288,720 * 288,720 * 576 etc.) resolution transmits the specification requirement of real time kinematics image sequence; Can be implemented in the specification requirement that transmits the motion image sequence of 352 * 288 above resolution in real time on the E1 channel of 2Mbit/s bandwidth; Can support forward multimedia service (audio frequency, video, data service) and reverse audio frequency and data service comprehensively to transmit.In a word, realized goal of the invention.
Claims (9)
1, a kind of multimedia transmission coding/decoding device of realizing total digitalization, high-resolution, many interfaces, its control circuit is made up of encoder two parts; It is characterized in that: described encoder all is to adopt digital signal processor DSP as central processing unit, and the ancillary equipment of each digital signal processor DSP comprises microprocessor MCU, buffer and external memory storage SDRAM; This digital signal processor DSP is connected with by buffer: starting ROM, usb interface controller and 10BaseT/100BaseT interface controller, then is directly to adopt six line seamless links between digital signal processor DSP and the E1 interface controller.
2, multimedia transmission coding/decoding device according to claim 1, it is characterized in that: described digital signal processor DSP is the chip that TIX produces, and its model is TMS320C620X, TMS320C621X, TMS320C670X, TMS320C671X series.
3, multimedia transmission coding/decoding device according to claim 1 and 2, it is characterized in that: the model of described E1 interface controller chip is DS21354/21554, and the receive clock RCLK of this chip, reception data RSER, received frame synchronizing signal RSYNC, tranmitting data register TCLK, transmission data TSER and transmit frame synchronizing signal FSYNC realize seamless link with CLKR, DR, FSR, CLKX, DX and FSX six lines of described digital signal processor DSP chip respectively.
4, multimedia transmission coding/decoding device according to claim 1, it is characterized in that: described encoder section control circuit also includes: the mpeg 2 encoder that is connected with digital signal processor DSP by the sequential logic interface circuit, be connected to respectively the mpeg 2 encoder input, as the audio A/D transducer of analogue audio frequency input interface, the video a/d converter and the digital audio/video input interface of analog video input interface, the video coding memory storage SDRAM and the external memory storage SDRAM that are connected with mpeg 2 encoder; With the direct-connected Data Input Interface of digital signal processor DSP, reverse data output interface and reverse audio D/A converter, the latter is as reverse audio output interface.
5, according to claim 1 or 4 described multimedia transmission coding/decoding devices, it is characterized in that: the model of described mpeg 2 encoder chip is: MB86390, the model of audio A/D converter chip is: PCM1800, the model of video a/d converter chip is: SAA7113.
6, multimedia transmission coding/decoding device according to claim 4, it is characterized in that: described sequential logic interface circuit is formed with programmable logic device (CPLD), and this sequential logic interface circuit is connected to digital signal processor by described buffer.
7, multimedia transmission coding/decoding device according to claim 1, it is characterized in that: described decoder section control circuit also includes: the MPEG2 decoder that is connected with digital signal processor DSP by the sequential logic interface circuit, be connected to respectively MPEG2 decoder output, as the audio D/A converter of analogue audio frequency output interface, the video d/a transducer and the digital audio/video output interface of analog video output interface, the video decode memory storage SDRAM and the external memory storage SDRAM that are connected with the MPEG2 decoder; With the direct-connected data output interface of digital signal processor DSP, reverse data input interface and reverse audio D/A converter, the latter is as reverse audio input interface.
8, according to claim 1 or 7 described multimedia transmission coding/decoding devices, it is characterized in that: the model of described MPEG2 decoder chip is: MB87L2250, the model of audio D/A converter chip is: PCM1723, the model of video d/a converter chip is: SAA7128.
9, multimedia transmission coding/decoding device according to claim 7, it is characterized in that: described sequential logic interface circuit is formed with programmable logic device (CPLD), and this sequential logic interface circuit is to be connected to digital signal processor by described buffer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100389556C (en) * | 2004-03-05 | 2008-05-21 | 华为技术有限公司 | A method for implementing parsing of interface code stream |
| CN101296142B (en) * | 2007-04-29 | 2011-05-11 | 中国科学院声学研究所 | Transmission stream processing equipment and corresponding method for chip processor |
| CN104467898A (en) * | 2013-09-25 | 2015-03-25 | 北京国通创安报警网络技术有限公司 | Portable intelligent terminal and method for conducting data transmission with portable intelligent terminal |
| CN105282600A (en) * | 2014-12-31 | 2016-01-27 | 郭磊 | High-definition low-bit-rate digital video compressor |
| CN115442638A (en) * | 2022-09-15 | 2022-12-06 | 浙江农业商贸职业学院 | Multimedia synchronous live broadcast system |
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- 2002-11-13 CN CN 02148625 patent/CN1411283A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100389556C (en) * | 2004-03-05 | 2008-05-21 | 华为技术有限公司 | A method for implementing parsing of interface code stream |
| CN101296142B (en) * | 2007-04-29 | 2011-05-11 | 中国科学院声学研究所 | Transmission stream processing equipment and corresponding method for chip processor |
| CN104467898A (en) * | 2013-09-25 | 2015-03-25 | 北京国通创安报警网络技术有限公司 | Portable intelligent terminal and method for conducting data transmission with portable intelligent terminal |
| CN105282600A (en) * | 2014-12-31 | 2016-01-27 | 郭磊 | High-definition low-bit-rate digital video compressor |
| CN115442638A (en) * | 2022-09-15 | 2022-12-06 | 浙江农业商贸职业学院 | Multimedia synchronous live broadcast system |
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