CN2519409Y - 具中央引线的半导体封装组件 - Google Patents

具中央引线的半导体封装组件 Download PDF

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CN2519409Y
CN2519409Y CN01274946U CN01274946U CN2519409Y CN 2519409 Y CN2519409 Y CN 2519409Y CN 01274946 U CN01274946 U CN 01274946U CN 01274946 U CN01274946 U CN 01274946U CN 2519409 Y CN2519409 Y CN 2519409Y
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substrate
semiconductor element
elongated slot
semiconductor
duct
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CN01274946U
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林钦福
陈明辉
郑清水
叶乃华
彭镇滨
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Kingpak Technology Inc
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Kingpak Technology Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Wire Bonding (AREA)

Abstract

一种具中央引线的半导体封装组件。为提供一种封装制程简单、成本低、固定效果好的半导体封装组件,提出本实用新型,它包括贯设长槽并于下表面形成复数讯号输出端的基板、长度略小于长槽的长度并设有复数焊垫的半导体元件、复数条导线及封胶体;半导体元件固定于基板的上表面,其上复数个焊垫由基板的长槽露出及令长槽的一端形成孔道;复数条导线系位于基板的长槽内,其两端与焊垫及讯号输出端电连接。

Description

具中央引线的半导体封装组件
技术领域
本实用新型属于半导体封装组件,特别是一种具中央引线的半导体封装组件。
背景技术
如图1所示,习知的一种具中央引线的半导体封装组件包括有基板10、半导体元件12及封胶体14、16。基板10具有透空的长槽18,半导体元件12上的复数个焊垫20系位于基板的长槽18位置,藉由复数条导线22使焊垫20与基板10电连接,封胶体14、16系分别覆盖于半导体元件12及基板10的长槽18,分别藉以保护半导体元件12及复数条导线22。
这种习知的具中央引线的半导体封装组件封胶体14、16的封胶方法,系以点胶或网印方式覆盖于半导体元件12及基板10的长槽18上,因此,其必须以两道程序完成封胶过程,其封装制程上较为繁琐,相对地封装成本较高。
发明内容
本实用新型的目的是提供一种封装制程简单、成本低、固定效果好的具中央引线的半导体封装组件。
本实用新型包括基板、半导体元件、复数条导线及封胶体;基板设有上表面、下表面及由上表面贯穿至下表面的长槽,下表面形成有复数个讯号输出端;半导体元件长度略小于基板上长槽的长度,其上设有复数个焊垫;半导体元件系固定于基板的上表面,令其上复数个焊垫由基板的长槽露出,并令长槽的一端形成孔道;复数条导线系位于基板的长槽内,其两端分别电连接至半导体元件上的焊垫及基板上的复数个讯号输出端;封胶体系分别覆盖于半导体元件及复数条导线;并经长槽一端的孔道呈衔接状。
其中:
长槽具有第一端点及第二端点,孔道系形成于长槽的第二端点。
基板下表面上的讯号输出端形成有金属球。
金属球系为球栅阵列金属球。
由于本实用新型包括贯设长槽并于下表面形成复数讯号输出端的基板、长度略小于长槽的长度并设有复数焊垫的半导体元件、复数条导线及封胶体;半导体元件固定于基板的上表面,其上复数个焊垫由基板的长槽露出及令长槽的一端形成孔道;复数条导线系位于基板的长槽内,其两端与焊垫及讯号输出端电连接;封胶体系分别覆盖于半导体元件及复数条导线;并经长槽一端的孔道呈衔接状。封装时,由基板上表面灌注的封胶体流经长槽形成的孔道往下流入基板的长槽及下表面,以覆盖位于长槽内的复数条导线。以灌胶方式封装半导体元件,可简化制造程序,提高封装效率;并可同时封装数个半导体元件,提高封装效率;不仅封装制程简单,而且成本低、固定效果好,从而达到本发明的目的。
附图说明
图1、为习知的具中央引线的半导体封装组件结构示意剖视图。
图2、为本实用新型结构示意横向剖视图。
图3、为本实用新型结构示意纵向剖视图。
图4、为本实用新型封装灌胶示意图。
图5、为图4中A-A剖视图。
图6、为图4中B-B剖视图。
具体实施方式
如图2、图3所示,本实用新型包括有基板30、半导体元件32、复数条导线34及封胶体36。
基板30设有上表面38、下表面40及由上表面38贯穿至下表面40的长槽42,下表面40形成有复数个讯号输出端44,讯号输出端44形成与其电连接的球栅阵列金属球(ball gride array)50。
半导体元件32上设有复数个焊垫46。
半导体元件32系固定于基板30的上表面38,使得半导体元件32上的复数个焊垫46由基板30的长槽42露出,半导体元件32的长度略小于基板30的长槽42的长度,使得当半导体元件32固定于基板30上时,长槽42的一端形成孔道48。
复数条导线34系位于基板30的长槽42内,其一端电连接至半导体元件32上的焊垫46,另一端电连接至基板30上的复数个讯号输出端44,使半导体元件32与基板30相互电连接。
封胶体36系分别覆盖于半导体元件32及复数条导线34,并经长槽42一端的孔道48使覆盖于半导体元件32及复数条导线34的封胶体36呈衔接状。
如图4、图5、图6所示,本实用新型封装时,提供设有上、下表面38、40及贯穿至上、下表面38、40具有第一、二端54、56三个长槽42的基板30,并于基板30下表面40设有复数讯号输出端44;提供三个设有复数焊垫46的半导体元件32,并令半导体元件32的长度小于基板30上长槽42的长度;将三个半导体元件32固定设置于预设三个长槽42的基板30上表面38,令复数焊垫32由基板30长槽42露出;基板30的上表面38则形成有贯通至基板30的下表面40的孔道48,令前两个孔道48系形成于第二端点56,最后一个孔道48系形成于第一端点54;将复数条导线34置入基板30各长槽42内,其两端分别与半导体元件32上的焊垫46及基板30上的讯号输出端44形成电连接;如图6所示,将封胶体36由长槽42的第一端点54依箭头方向注入基板30的上表面38,此时,封胶体36将顺着箭头方向覆盖住半导体元件32;并当封胶体36流经长槽42的第二端点56的孔道48时,将顺着孔道48往下流入基板30的下表面40,从而将基板30的长槽42封住,用以保护住位于长槽42内的复数条导线34;并令封胶体36流经中间位置及最后位置的半导体元件32,再由孔道48流入基板30的下表面40;当完成该封胶体灌注后,将复数个球栅阵列金属球50形成于基板30的下表面40,并与复数个讯号输端44电连接。
如此,即可同时完成数个半导体元件32的封装,最后再将每一封装完成的半导体元件予以切割成单颗的封装元件,从而,令其在制造上相当的便利。
再者,基板30上前方及中间位置的孔道48系位于半导体元件32的后方,使得当进行封胶体36的灌注时,令封胶体36可先压住半导体元件32,使得封胶体36往基板30的下表面40灌注时,封胶体36的不致将半导体元件32自基板30上撑开,而产生溢胶的情形。而基板30后方的孔道48则可位于半导体元件32的前方,因流经基板30后方的封胶体36的模流压力已减弱,从而不致于将后方的半导体元件32自基板30撑开。
综上所述,本实用新型具有如下的优点:
1、以灌胶方式封装半导体元件32,可简化制造程序,提高封装效率。
2、以灌胶方式封装半导体元件32,可同时封装数个半导体元件32,提高封装效率。

Claims (4)

1、一种具中央引线的半导体封装组件,它包括基板、半导体元件、复数条导线及封胶体;基板设有上表面、下表面及由上表面贯穿至下表面的长槽,下表面形成有复数个讯号输出端;半导体元件上设有复数个焊垫;半导体元件系固定于基板的上表面,并令其上复数个焊垫由基板的长槽露出;复数条导线系位于基板的长槽内,其两端分别电连接至半导体元件上的焊垫及基板上的复数个讯号输出端;封胶体系分别覆盖于半导体元件及复数条导线;其特征在于所述的半导体元件的长度略小于基板上长槽的长度,令长槽的一端形成孔道;覆盖于半导体元件及复数条导线的封胶体经长槽一端的孔道呈衔接状。
2、根据权利要求1所述的具中央引线的半导体封装组件,其特征在于所述的长槽具有第一端点及第二端点,孔道系形成于长槽的第二端点。
3、根据权利要求1所述的具中央引线的半导体封装组件,其特征在于所述的基板下表面上的讯号输出端形成有金属球。
4、根据权利要求3所述的具中央引线的半导体封装组件,其特征在于所述的金属球系为球栅阵列金属球。
CN01274946U 2001-11-27 2001-11-27 具中央引线的半导体封装组件 Expired - Lifetime CN2519409Y (zh)

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