CN221008959U - Novel middle-high voltage shielding grid power MOSFET layout - Google Patents
Novel middle-high voltage shielding grid power MOSFET layout Download PDFInfo
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- CN221008959U CN221008959U CN202322734495.8U CN202322734495U CN221008959U CN 221008959 U CN221008959 U CN 221008959U CN 202322734495 U CN202322734495 U CN 202322734495U CN 221008959 U CN221008959 U CN 221008959U
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- polycrystalline silicon
- contact hole
- out area
- leading
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 60
- 229910052751 metal Inorganic materials 0.000 claims description 35
- 239000002184 metal Substances 0.000 claims description 35
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The embodiment of the application provides a novel middle-high voltage shielding grid power MOSFET layout, and the purpose of optimizing the single-pulse avalanche energy performance of a device is achieved by optimizing a source polycrystalline silicon lead-out area and adding source contact holes between first grooves of the source polycrystalline silicon lead-out area.
Description
Technical Field
The embodiment of the application belongs to the technical field of semiconductors, and particularly relates to a novel middle-high voltage shielding grid power MOSFET layout.
Background
In the design of the shielded gate power MOSFET layout, the source polysilicon electrode, the gate electrode and the source electrode are required to be respectively connected and isolated, but in the prior art, as shown in fig. 1, the source polysilicon lead-out area is only formed by arranging a source contact hole on the source polysilicon, so that the single-pulse avalanche energy (EAS for short) performance is poor.
Disclosure of Invention
In order to solve or alleviate the problems in the prior art. Therefore, a novel middle-high voltage shielding grid power MOSFET layout is provided, which comprises the following steps: a cell region and a terminal ring region;
The cell area comprises a plurality of first grooves, a source polycrystalline silicon leading-out area, a grid leading-out area and a source leading-out area which are arranged at intervals;
A first source electrode contact hole is formed among the first grooves of the source electrode polycrystalline silicon leading-out area, and a first source electrode polycrystalline silicon contact hole is formed in each first groove of the source electrode leading-out area;
A gate contact hole is formed in each first groove of the gate lead-out area;
Second source contact holes are formed among the plurality of first grooves of the source electrode lead-out area;
The first source electrode contact hole and the first source electrode polycrystalline silicon contact hole are filled with metal, and the source electrode polycrystalline silicon electrode is led out through the first metal layer;
the grid electrode contact hole is filled with metal, and the grid electrode is led out through the second metal layer;
the source electrode contact hole is filled with metal, and a source electrode is led out through the third metal layer;
the terminal ring region is in communication with the source polysilicon lead-out region.
As a preferred embodiment of the present application, the first trench of the source polysilicon lead-out area is filled with source polysilicon; and source polycrystalline silicon and gate polycrystalline silicon are filled in each first groove of the gate leading-out area and the source leading-out area from bottom to top, and the source polycrystalline silicon and the gate polycrystalline silicon in the same first groove of the gate leading-out area and the source leading-out area are separated by a dielectric layer.
As a preferred embodiment of the present application, a first source polysilicon contact hole and a gate contact hole are disposed in the same first trench.
As a preferred embodiment of the present application, the terminal ring area includes a plurality of second trenches arranged at intervals, each second trench is provided with a second source polysilicon contact hole, the second source polysilicon contact holes are filled with metal, and the source polysilicon electrodes are led out through the first metal layer; and second source electrode contact holes are formed among the second trenches, metal is filled in the second source electrode contact holes, and source electrode polycrystalline silicon electrodes are led out through the third metal layer.
Compared with the prior art, the embodiment of the application provides a middle-high voltage shielding grid power MOSFET layout, and the application achieves the aim of optimizing the single pulse avalanche Energy (EAS) performance of a device by optimizing the source polycrystalline silicon lead-out area and adding the source contact hole between the first grooves of the source polycrystalline silicon lead-out area.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. Some specific embodiments of the application will be described in detail hereinafter by way of example and not by way of limitation with reference to the accompanying drawings. The same reference numbers in the drawings denote the same or similar parts or portions, and it will be understood by those skilled in the art that the drawings are not necessarily drawn to scale, in which:
Fig. 1 is a schematic diagram of a layout of a middle-high voltage shielded gate power MOSFET in the prior art;
fig. 2 is a schematic structural diagram of a novel middle-high voltage shielding gate power MOSFET layout according to an embodiment of the present application.
Detailed Description
In order to enable those skilled in the art to better understand the present application, the following description will make clear and complete descriptions of the technical solutions according to the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are merely some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
As shown in fig. 2, an embodiment of the present application provides a novel middle-high voltage shielded gate power MOSFET layout, including: a cell region and a terminal ring region;
The cell region comprises a plurality of first grooves 11, a source polycrystalline silicon leading-out region 01, a grid leading-out region 02 and a source leading-out region 03 which are arranged at intervals;
A first source contact hole 08 is arranged among the plurality of first trenches 11 of the source polysilicon lead-out area 01, and a first source polysilicon contact hole 07 is arranged in each first trench 11 of the source lead-out area 03;
Gate contact holes 09 are provided in the first trenches 11 of the gate lead-out region 02;
Second source contact holes 10 are provided between each of the plurality of first trenches 11 in the first trenches 11 of the source extraction region 03;
The first source electrode contact hole 08 and the source electrode polysilicon contact hole 07 are filled with metal, and the source electrode polysilicon electrode is led out through the first metal layer 04;
the gate contact hole 09 is filled with metal, and the gate is led out through the second metal layer 05;
the second source contact hole 10 is filled with metal, and the source is led out through the third metal layer 06, and in the embodiment of the present application, the metal is copper.
The terminal ring region is communicated with the source polycrystalline silicon leading-out region 01.
In the embodiment of the present application, the metal is aluminum, and the first metal layer 04, the second metal layer 05 and the third metal layer 06 are all aluminum.
As a preferred embodiment of the present application, the first trench 11 of the source polysilicon lead-out area 01 is filled with source polysilicon; the first trenches 11 of the gate lead-out region 02 and the source lead-out region 03 are filled with source polysilicon and gate polysilicon from bottom to top, and the source polysilicon and the gate polysilicon in the same first trench 11 of the gate lead-out region 02 and the source lead-out region 03 are separated by a dielectric layer.
As a preferred embodiment of the present application, a first source polysilicon contact hole 07 and a gate contact hole 09 are disposed in the same first trench 11.
As a preferred embodiment of the present application, the terminal ring area includes a plurality of second trenches 12 disposed at intervals, a second source polysilicon contact hole 13 is disposed in the second trench 12, and the second source polysilicon contact hole 13 is filled with metal and leads out source polysilicon electrodes through the first metal layer 04; a second source contact hole 10 is disposed between the second trenches 12, and the second source contact hole 10 is filled with metal, and the source polysilicon electrode is led out through the third metal layer 06.
The embodiment of the application provides a middle-high voltage shielding grid power MOSFET layout, which achieves the aim of optimizing the single pulse avalanche Energy (EAS) performance of a device by optimizing a source polycrystalline silicon lead-out area and adding source contact holes between first grooves of the source polycrystalline silicon lead-out area.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (4)
1. The utility model provides a novel middle-high voltage shielding grid power MOSFET territory which characterized in that includes: a cell region and a terminal ring region;
The cell area comprises a plurality of first grooves, a source polycrystalline silicon leading-out area, a grid leading-out area and a source leading-out area which are arranged at intervals;
A first source electrode contact hole is formed among the first grooves of the source electrode polycrystalline silicon leading-out area, and a first source electrode polycrystalline silicon contact hole is formed in each first groove of the source electrode leading-out area; a gate contact hole is formed in each first groove of the gate lead-out area;
Second source contact holes are formed among the plurality of first grooves of the source electrode lead-out area;
The first source electrode contact hole and the first source electrode polycrystalline silicon contact hole are filled with metal, and the source electrode polycrystalline silicon electrode is led out through the first metal layer;
the grid electrode contact hole is filled with metal, and the grid electrode is led out through the second metal layer;
the source electrode contact hole is filled with metal, and a source electrode is led out through the third metal layer;
the terminal ring region is in communication with the source polysilicon lead-out region.
2. The novel medium-high voltage shielding grid power MOSFET layout as set forth in claim 1, wherein the first trench of the source polysilicon lead-out area is filled with source polysilicon; and source polycrystalline silicon and gate polycrystalline silicon are filled in each first groove of the gate leading-out area and the source leading-out area from bottom to top, and the source polycrystalline silicon and the gate polycrystalline silicon in the same first groove of the gate leading-out area and the source leading-out area are separated by a dielectric layer.
3. The novel medium-high voltage shielded gate power MOSFET layout of claim 1 wherein a first source polysilicon contact hole and a gate contact hole are disposed in the same first trench.
4. The novel medium-high voltage shielding grid power MOSFET layout as set forth in claim 1, wherein the terminal ring region comprises a plurality of second grooves arranged at intervals, each second groove is provided with a second source polycrystalline silicon contact hole, the second source polycrystalline silicon contact holes are filled with metal, and source polycrystalline silicon poles are led out through the first metal layer; a plurality of said first
A second source electrode contact hole is arranged between the two grooves, metal is filled in the second source electrode contact hole,
And the source polycrystalline silicon electrode is led out through the third metal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322734495.8U CN221008959U (en) | 2023-10-11 | 2023-10-11 | Novel middle-high voltage shielding grid power MOSFET layout |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322734495.8U CN221008959U (en) | 2023-10-11 | 2023-10-11 | Novel middle-high voltage shielding grid power MOSFET layout |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221008959U true CN221008959U (en) | 2024-05-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322734495.8U Active CN221008959U (en) | 2023-10-11 | 2023-10-11 | Novel middle-high voltage shielding grid power MOSFET layout |
Country Status (1)
| Country | Link |
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| CN (1) | CN221008959U (en) |
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2023
- 2023-10-11 CN CN202322734495.8U patent/CN221008959U/en active Active
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