CN220934073U - Packaging structure of power semiconductor module - Google Patents
Packaging structure of power semiconductor module Download PDFInfo
- Publication number
- CN220934073U CN220934073U CN202322530175.0U CN202322530175U CN220934073U CN 220934073 U CN220934073 U CN 220934073U CN 202322530175 U CN202322530175 U CN 202322530175U CN 220934073 U CN220934073 U CN 220934073U
- Authority
- CN
- China
- Prior art keywords
- copper foil
- power semiconductor
- bridge arm
- copper
- terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 64
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 18
- 239000000919 ceramic Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000011889 copper foil Substances 0.000 claims description 134
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 132
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 4
- 230000002146 bilateral effect Effects 0.000 claims description 2
- 230000005855 radiation Effects 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 230000010355 oscillation Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 15
- 238000006243 chemical reaction Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 150000003839 salts Chemical class 0.000 description 1
- 239000000741 silica gel Substances 0.000 description 1
- 229910002027 silica gel Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Inverter Devices (AREA)
Abstract
The invention belongs to the technical field of power semiconductor devices, and particularly discloses a packaging structure of a power semiconductor module. The package structure includes: a copper-clad ceramic substrate; a power semiconductor chip, a thermistor and a wiring terminal which are attached to the copper-clad ceramic substrate; and the bonding wire is used for connecting the power semiconductor chip with the metal layer on the copper-clad ceramic substrate. The packaging structure provided by the invention can be compatible with two circuit topologies through reasonable layout of the copper-clad ceramic substrate metal layers, in addition, the commutation circuit is optimized, equalization of the parallel chip commutation circuit is realized, a smaller parasitic inductance value is realized, and turn-off overvoltage and switch oscillation are reduced; the driving loop adopts a Kelvin structure, so that the negative feedback influence of the common-source parasitic inductance on the driving loop is reduced, and the switching speed is improved.
Description
Technical Field
The utility model belongs to the technical field of packaging integration of power semiconductor modules, and particularly relates to a packaging structure of a power semiconductor module.
Background
The power electronic conversion device is widely applied to the fields of electric automobiles, aerospace, new energy power generation and the like, and with the development of technical progress and social demands, the fields put higher requirements on the power electronic conversion device, such as power density improvement and efficiency improvement. The power semiconductor module is a core device of the power electronic conversion device, and the improvement of the performance of the power semiconductor module greatly influences the performance of the device. Compared with the traditional silicon-based power semiconductor device, the wide band gap power semiconductor device has the advantages of higher breakdown voltage, higher switching speed, higher working temperature and the like, can greatly reduce the device loss of the power electronic conversion device, and improves the power density and the efficiency. However, at high switching speeds, wide bandgap power semiconductor devices are more sensitive to parasitic parameters introduced by the package, e.g., parasitic inductance of the main power converter loop can cause overvoltage during device turn-off; the common source inductance reduces the switching speed and interferes with the drive loop; the parasitic parameter asymmetry of the parallel chip causes non-current sharing problems.
The packaging structure of the utility model not only can be compatible with two circuit topologies, but also can effectively reduce parasitic inductance and balance the parasitic inductance difference of parallel chip branches, thereby fully playing the advantages of the power semiconductor chip and improving the performance of the power electronic conversion device. The packaging method provides a reliable processing method for the packaging structure, so that the packaging structure is realized, and the cost is low and the processing quality is reliable.
Disclosure of utility model
In order to solve the above problems, the present utility model provides a packaging structure of a power semiconductor module, which can realize a parallel chip structure with extremely low parasitic inductance of an internal current conversion loop and symmetrical layout, and a packaging method with easy internal connection.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
The utility model provides a packaging structure of power semiconductor module which characterized in that: the front surface of the copper-clad ceramic substrate is provided with an upper copper foil which is provided with an auxiliary source copper foil and a driving grid copper foil which are arranged vertically symmetrically;
The upper bridge arm and the lower bridge arm are provided with the same number and the same type of power semiconductor chips, the source electrodes of the power semiconductor chips of the upper bridge arm and the lower bridge arm are electrically connected with corresponding auxiliary source copper foils through bonding wires, the grid electrodes of the power semiconductor chips of the upper bridge arm and the lower bridge arm are electrically connected with corresponding driving grid copper foils through bonding wires, and the auxiliary source copper foils and the driving grid copper foils are respectively connected with terminals;
the power semiconductor chips of the upper bridge arm and the lower bridge arm are symmetrically arranged;
the terminals on the auxiliary source copper foil in the upper bridge arm and the terminals on the driving gate copper foil are respectively symmetrical with the terminals on the auxiliary source copper foil in the lower bridge arm and the terminals on the driving gate copper foil.
Preferably, the distance between the terminal on the auxiliary source copper foil in the upper bridge arm and the terminal on the driving gate copper foil and the power semiconductor chip in the upper bridge arm is the same as the distance between the terminal on the auxiliary source copper foil in the lower bridge arm and the terminal on the driving gate copper foil and the power semiconductor chip in the lower bridge arm.
Preferably, the packaging structure of the power semiconductor module further comprises a left bridge arm and a right bridge arm, and the upper copper foil is provided with an auxiliary source copper foil and a driving grid copper foil which are arranged in a bilateral symmetry manner;
The power semiconductor chips of the left bridge arm and the right bridge arm are provided with the same number and the same type of power semiconductor chips, the source electrodes of the power semiconductor chips of the left bridge arm and the right bridge arm are electrically connected with the corresponding auxiliary source copper foils through bonding wires, the grid electrodes of the power semiconductor chips of the left bridge arm and the right bridge arm are electrically connected with the corresponding driving grid copper foils through bonding wires, and the auxiliary source copper foils and the driving grid copper foils are respectively connected with terminals;
The power semiconductor chips of the left bridge arm and the right bridge arm are symmetrically arranged;
And the terminals on the auxiliary source copper foil in the left bridge arm and the terminals on the driving grid copper foil are respectively symmetrical with the terminals on the auxiliary source copper foil in the right bridge arm and the terminals on the driving grid copper foil.
Preferably, the distance between the terminal on the auxiliary source copper foil in the left bridge arm and the terminal on the driving gate copper foil and the power semiconductor chip in the left bridge arm is the same as the distance between the terminal on the auxiliary source copper foil in the right bridge arm and the terminal on the driving gate copper foil and the power semiconductor chip in the right bridge arm.
Preferably, in the power semiconductor chips, the source electrode of each power semiconductor chip is individually led out and the bonding wire is electrically connected with an individual signal terminal and forms a Kelvin structure.
Preferably, the copper-clad ceramic substrate is an aluminum nitride copper-clad ceramic substrate, and the back surface of the copper-clad ceramic substrate is provided with a lower copper foil, and the lower copper foil is used for being connected with a radiator so as to improve the heat radiation performance.
Preferably, the peripheral edge of the lower copper foil is etched with uniform and equidistant holes.
Preferably, the upper layer copper foil comprises a plurality of functional copper foils which are partitioned independently, and each functional copper foil is welded with a terminal.
Preferably, the terminal is a pin terminal with a curved buffer structure in the middle.
The beneficial effects of using the utility model are as follows:
In the packaging structure of the power semiconductor module, the symmetrical chip layout mode can ensure the consistency of parasitic parameters of the parallel chip converter circuit and the driving circuit, thereby realizing the consistency of the working states of the parallel chips; the chip driving connection adopts a Kelvin structure, so that the common source inductance can be effectively reduced, and the coupling between a driving loop and a main power loop is reduced; the half-bridge power module realized based on the packaging structure has the advantages that the path length of the main power converter loop is smaller, the parasitic inductance of the converter loop can be effectively reduced, the voltage peak of the high-speed switching process of the power semiconductor chip is reduced, and the damage to devices is avoided; the edge of the copper foil of the copper-clad ceramic substrate is etched with a small hole, which is helpful for releasing thermal stress and prolonging the service life of the module.
Drawings
Fig. 1 is a side view of a copper-clad ceramic substrate in an embodiment of the utility model.
Fig. 2 is a top view of a copper-clad ceramic substrate in an embodiment of the utility model.
Fig. 3 is a bottom view of a copper-clad ceramic substrate in an embodiment of the utility model.
Fig. 4 is a schematic diagram of an internal structure of a first circuit topology module according to an embodiment of the present utility model.
Fig. 5 is a schematic diagram illustrating an internal structure of another view of the first circuit topology module according to the embodiment of the present utility model.
Fig. 6 is a schematic diagram of a terminal of a first circuit topology module according to an embodiment of the utility model.
Fig. 7 is a schematic diagram of an external structure of a first circuit topology module according to an embodiment of the present utility model.
Fig. 8 is a circuit topology diagram of a first circuit topology module according to an embodiment of the present utility model.
Fig. 9 is a schematic diagram of an internal structure of a second circuit topology module according to an embodiment of the present utility model.
Fig. 10 is a schematic diagram of a terminal of a second circuit topology module according to an embodiment of the present utility model.
Fig. 11 is a schematic diagram of an external structure of a second circuit topology module according to an embodiment of the present utility model.
Fig. 12 is a circuit topology diagram of a second circuit topology module according to an embodiment of the present utility model.
Throughout the drawings, the same reference numerals are used to designate the same elements or structures,
Wherein: 1 is a copper-clad ceramic substrate, 2 is a ceramic substrate, 3 is a lower copper foil, 4 is a double hole of the lower copper foil, 5 is DC+ copper foil, 6 is a drain copper foil, 9 is DC-copper foil, and 14 is AC copper foil;
7. 11, 13 and 15 are auxiliary source copper foils;
8. 10, 12 and 16 are all driving grid copper foils;
17 and 18 are NTC resistor copper foil, 19 is source copper foil, 20 is first MOSFET chip, 21 is second MOSFET chip, 22 is third MOSFET chip, 23 is fourth MOSFET chip, 24 is fifth MOSFET chip, 25 is sixth MOSFET chip, 26 is seventh MOSFET chip, 27 is eighth MOSFET chip, 28 is ninth MOSFET chip, 29 is tenth MOSFET chip, 30 is eleventh MOSFET chip, 31 is twelfth MOSFET chip;
20 a-31 a are driving bonding wires;
20 b-31 b are auxiliary source bonding wires;
21 c-31 c are power bonding wires;
32 (32 a-32 f) are DC-connection terminals;
33 (33 a-33 h) are drain connection terminals;
34. 37, 41, 45 are drive gate connection terminals;
35. 38, 40, 44 are auxiliary source connection terminals;
36 (36 a to 36 f) are DC+ connection terminals;
39 (39 a to 39 f) are AC connection terminals;
The NTC resistor connection terminals 42 and 43 are respectively a source connection terminal 46, an NTC resistor 47, a shell 48, a metal spring plate 49 (49 a and 49 b), a glue filling hole 50, a pouring sealant 51 and a needle-type terminal hole 52.
Detailed Description
In order to make the objects, technical solutions and advantages of the present technical solution more apparent, the present technical solution is further described in detail below in conjunction with the specific embodiments. It should be understood that the description is only illustrative and is not intended to limit the scope of the present technical solution.
As shown in fig. 1 to 8, the package structure proposed in this embodiment mainly includes: the power semiconductor chip comprises a copper-clad ceramic substrate 1, power semiconductor chips 20-31 welded on the copper-clad ceramic substrate 1, bonding wires 20 a-31 a, 20 b-31 b and 20 c-31 c for connecting surface electrodes of the power semiconductor chips, pin terminals 32-46 welded on the copper-clad ceramic substrate 1, a thermistor 47 welded on the copper-clad ceramic substrate 1, a shell 48, a metal spring plate 49 and pouring sealant 51.
The copper-clad ceramic substrate 1 has a three-layer structure, wherein both the upper layer and the lower layer are conductor layers, and the middle layer is a ceramic substrate 2. The upper conductor layer is etched to form a plurality of independent conductor layers, and the independent conductor layers, the power chips, the bonding wires, the terminals and the like form a circuit topology. The ceramic substrate 2 of the intermediate layer plays an insulating and heat conducting role. The lower copper foil 3 is generally connected to a heat sink by a thermal interface material to conduct heat. In this embodiment, the conductor layer is high-conductivity oxygen-free copper, hereinafter referred to as copper foil, and the surface of the copper foil can be prevented from oxidation by electroplating. The ceramic substrate of the intermediate layer is generally selected from ceramic materials such as alumina, aluminum nitride, zirconia-doped alumina, and silicon nitride. In this embodiment, in order to improve heat dissipation performance, the ceramic substrate is made of aluminum nitride ceramic having the highest coefficient of thermal conductivity. Holes are etched in the corners of part of the copper foil of the upper layer, a circle of holes 4 are etched in the part of the copper foil of the lower layer, which is a certain distance away from the edge, and the etched holes are helpful for releasing the thermal stress of the edge of the copper foil and improving the reliability.
The outer edges of the upper and lower copper foils are spaced apart from the edge of the ceramic substrate 2 by a certain distance, which is determined according to the pressure-resistant requirement of the module, and in this embodiment, the outermost edges of the upper copper foils are set to 1.9mm from the edge of the ceramic substrate 2, and the outermost edges of the lower copper foils 3 are set to 0.55mm from the edge of the ceramic substrate 2. The upper copper foil is processed to form a circuit pattern, and has the effects of conducting electricity and heat. In the embodiment, the upper copper foil is provided with a solder mask layer, so that the effect of preventing overflow after melting of solder is achieved.
The upper layer copper foil is composed of a DC+ copper foil 5, a drain copper foil 6, a DC-copper foil 9, an AC copper foil 14, auxiliary source copper foils 7, 11, 13, 15, drive gate copper foils 8, 10, 12, 16, NTC resistor copper foils 17, 18 and a source copper foil 19.
The circuit provided by the embodiment is composed of an upper bridge arm, a lower bridge arm, a left bridge arm and a right bridge arm, the four bridge arms can be IGBT, MOSFET, diode and other power semiconductor chips, bonding wires for connecting electrodes on the surface of the power semiconductor chips are made of copper, aluminum, gold and other conductor materials, and in the embodiment, the bonding wires are aluminum bonding wires with low cost and most application.
The drains of the first MOSFET chip 20, the second MOSFET chip 21 and the third MOSFET chip 22 are soldered to the drain copper foil 6, the gates are connected to the gate copper foil 8 by drive bonding wires 20a, 21a, 22a, respectively, the auxiliary sources are connected to the auxiliary source copper foil 7 by auxiliary source bonding wires 20b, 21b, 22b, respectively, and the sources are connected to the source copper foil 19 by power bonding wires 20c, 21c, 22c, respectively. The drain copper foil 6 is connected to an external circuit through the DC-connection terminals 33a to 33h, the gate copper foil 8 is connected to an external circuit through the pin terminal 34, the auxiliary source copper foil 7 is connected to an external circuit through the pin terminal 35, and the source copper foil 19 is connected to an external circuit through the pin terminal 46.
The drains of the fourth MOSFET chip 23, the fifth MOSFET chip 24 and the sixth MOSFET chip 25 are soldered to the AC copper foil 14, the gates are connected to the gate copper foil 16 by drive bonding wires 23a, 24a, 25a, respectively, the auxiliary sources are connected to the auxiliary source copper foil 15 by auxiliary source bonding wires 23b, 24b, 25b, respectively, and the sources are connected to the source copper foil 19 by power bonding wires 23c, 24c, 25c, respectively. The AC copper foil 14 is connected to an external circuit through AC connection terminals 39a to 39f, the gate copper foil 16 is connected to an external circuit through a pin terminal 41, the auxiliary source copper foil 15 is connected to an external circuit through a pin terminal 40, and the source copper foil 19 is connected to an external circuit through a pin terminal 46.
The drains of the seventh MOSFET chip 26, the eighth MOSFET chip 27 and the ninth MOSFET chip 28 are soldered to the dc+ copper foil 5, the gates are connected to the gate copper foil 12 by drive bonding wires 26a, 27a, 28a, respectively, the auxiliary sources are connected to the auxiliary source copper foil 13 by auxiliary source bonding wires 26b, 27b, 28b, respectively, and the sources are connected to the AC copper foil 14 by power bonding wires 26c, 27c, 28c, respectively. The dc+ copper foil 5 is connected to an external circuit through dc+ connection terminals 36a to 36f, the gate copper foil 12 is connected to an external circuit through pin terminals 37, the auxiliary source copper foil 13 is connected to an external circuit through pin terminals 38, and the AC copper foil 14 is connected to an external circuit through AC connection terminals 39a to 39 f.
The tenth MOSFET chip 29, the eleventh MOSFET chip 30 and the twelfth MOSFET chip 31 have their drains soldered to the AC copper foil 14, their gates connected to the gate copper foil 10 by drive bonding wires 29a, 30a, 31a, respectively, their auxiliary sources connected to the auxiliary source copper foil 11 by auxiliary source bonding wires 29b, 30b, 31b, respectively, and their sources connected to the DC-copper foil 9 by power bonding wires 29c, 30c, 31c, respectively. The AC copper foil 14 is connected to an external circuit through AC connection terminals 39a to 39f, the gate copper foil 10 is connected to an external circuit through pin terminals 45, and the auxiliary source copper foil 11 is connected to an external circuit through pin terminals 44. The DC-copper foil 9 is connected to an external circuit through DC-connection terminals 32a to 32 f.
In order to improve the current capacity, the power bonding wires 20 c-31 c are generally formed by connecting a plurality of thick bonding wires in parallel, in this embodiment, each power bonding wire is formed by connecting 8 aluminum bonding wires with the diameter of 15mil in parallel, and in practical application, a plurality of bonding wires can be selected as much as possible according to the area size of the bondable on the chip. In this embodiment, the driving bonding wires 20a to 31a and the auxiliary source bonding wires 20b to 31b are each composed of 1 aluminum bonding wire with a diameter of 5mil, considering that the chip gate size is small.
In order to improve the toughness of the terminal, in this embodiment, a pin terminal with a buffer portion is selected, and an S-shaped bent portion is provided in the middle of the pin terminal, so that the pin terminal has a certain buffer effect under external stress. In addition, in order to improve corrosion resistance of the terminal in a humid, mold, salt mist or other hostile environment, the pin terminal surface gold plating treatment selected in this embodiment may be nickel plating treatment.
Fig. 7 is an external configuration diagram of a first circuit topology module according to the present embodiment. The outer shell 48 consists of a plastic shell, a plurality of pinholes 52 on the upper surface of the plastic shell, metal shrapnel 49a and 49b on two sides and a glue filling hole 50. The bottom of the shell 48 is adhered to the copper-clad ceramic substrate 1, the pin terminals welded on the copper-clad ceramic substrate extend out of a plurality of pin holes 52 on the top of the shell 48, a silica gel 51 for protecting the inner parts of the module from external pollution is arranged in the shell 48, metal elastic sheets 49a and 49b on two sides of the shell 48 are used for connecting a bottom radiator, and a glue filling hole 50 for glue injection is reserved on the top of the shell 48.
Fig. 8 is a circuit topology diagram of a first circuit topology module of the present embodiment; is formed of dc+ connection terminals (36 a to 36 f), DC-connection terminals (32 a to 32 f), AC connection terminals (39 a to 39 f), source connection terminal 46, drive gate connection terminals 34, 37, 41, 45, auxiliary source connection terminals 35, 38, 40, 44, drain connection terminal 33, NTC resistance connection terminals 42 and 43, MOSFET chips 20 to 31, NTC resistance 47, and electrical connection therebetween.
In the first circuit topology module of this embodiment, for the upper and lower bridge arms, the first MOSFET chip 20, the second MOSFET chip 21, the third MOSFET chip 22, the fourth MOSFET chip 23, the fifth MOSFET chip 24, and the sixth MOSFET chip 25 are vertically symmetrical, the driving gate connection terminal 34, the auxiliary source connection terminal 35, the driving gate connection terminal 41, and the auxiliary source connection terminal 40 are vertically symmetrical, and the distances between the auxiliary source connection terminal 35 and the driving gate connection terminal 41 and the first MOSFET chip 20, the second MOSFET chip 21, the third MOSFET chip 22, the driving gate connection terminal 41, and the auxiliary source connection terminal 40 and the fourth MOSFET chip 23, the fifth MOSFET chip 24, and the sixth MOSFET chip 25 are the same, thereby realizing the symmetry of the driving loops of the upper and lower bridge arm parallel chips, and improving the current equalizing characteristics of the parallel chips. The left and right bridge arms are similar and will not be described in detail. Therefore, symmetry of the power converter loop and the driving loop of the parallel chips of the left bridge arm and the right bridge arm is realized, and current sharing characteristic of the parallel chips can be improved.
In the first circuit topology module of this embodiment, the driving signal connection of the 12 MOSFET chips adopts Kelvin structure: the source electrodes of the 2 MOSFET chips are individually led out and connected with the individual signal terminals. The connection mode can effectively reduce the common-source inductance of the converter loop, reduce the coupling between the main power loop and the driving loop of the MOSFET chip, and improve the switching speed, thereby reducing the switching loss.
Fig. 9 to 12 are schematic diagrams of internal structures, schematic diagrams of terminals, schematic diagrams of external structures, and schematic diagrams of circuit topologies in the second circuit topology of the present embodiment, the seventh MOSFET chip 26, the eighth MOSFET chip 27, the ninth MOSFET chip 28, the tenth MOSFET chip 29, the eleventh MOSFET chip 30, and the twelfth MOSFET chip 31 of the left and right bridge arms are replaced with SBD chips, and then the driving gate connection terminals 37 and 45 and the auxiliary source connection terminals 38 and 44 of the left and right bridge arms are removed, so that the vienna power module can be obtained, which also has better current equalizing characteristics, faster switching speed, and smaller switching loss.
The foregoing is merely exemplary of the present utility model, and those skilled in the art can make many variations in the specific embodiments and application scope according to the spirit of the present utility model, as long as the variations do not depart from the spirit of the utility model.
Claims (9)
1. The utility model provides a packaging structure of power semiconductor module which characterized in that: the front surface of the copper-clad ceramic substrate is provided with an upper copper foil which is provided with an auxiliary source copper foil and a driving grid copper foil which are arranged vertically symmetrically;
The upper bridge arm and the lower bridge arm are provided with the same number and the same type of power semiconductor chips, the source electrodes of the power semiconductor chips of the upper bridge arm and the lower bridge arm are electrically connected with corresponding auxiliary source copper foils through bonding wires, the grid electrodes of the power semiconductor chips of the upper bridge arm and the lower bridge arm are electrically connected with corresponding driving grid copper foils through bonding wires, and the auxiliary source copper foils and the driving grid copper foils are respectively connected with terminals;
the power semiconductor chips of the upper bridge arm and the lower bridge arm are symmetrically arranged;
the terminals on the auxiliary source copper foil in the upper bridge arm and the terminals on the driving gate copper foil are respectively symmetrical with the terminals on the auxiliary source copper foil in the lower bridge arm and the terminals on the driving gate copper foil.
2. The package structure of a power semiconductor module according to claim 1, wherein: and the distances between the terminals on the auxiliary source copper foil in the upper bridge arm and the terminals on the driving grid copper foil and the power semiconductor chips in the upper bridge arm are the same as the distances between the terminals on the auxiliary source copper foil in the lower bridge arm and the terminals on the driving grid copper foil and the power semiconductor chips in the lower bridge arm.
3. The package structure of a power semiconductor module according to claim 1, wherein: the packaging structure of the power semiconductor module further comprises a left bridge arm and a right bridge arm, wherein the upper copper foil is provided with an auxiliary source copper foil and a driving grid copper foil which are arranged in a bilateral symmetry manner;
The power semiconductor chips of the left bridge arm and the right bridge arm are provided with the same number and the same type of power semiconductor chips, the source electrodes of the power semiconductor chips of the left bridge arm and the right bridge arm are electrically connected with the corresponding auxiliary source copper foils through bonding wires, the grid electrodes of the power semiconductor chips of the left bridge arm and the right bridge arm are electrically connected with the corresponding driving grid copper foils through bonding wires, and the auxiliary source copper foils and the driving grid copper foils are respectively connected with terminals;
The power semiconductor chips of the left bridge arm and the right bridge arm are symmetrically arranged;
And the terminals on the auxiliary source copper foil in the left bridge arm and the terminals on the driving grid copper foil are respectively symmetrical with the terminals on the auxiliary source copper foil in the right bridge arm and the terminals on the driving grid copper foil.
4. A package structure of a power semiconductor module according to claim 3, wherein: and the distance between the terminal on the auxiliary source copper foil in the left bridge arm and the terminal on the driving grid copper foil and the power semiconductor chip in the left bridge arm is the same as the distance between the terminal on the auxiliary source copper foil in the right bridge arm and the terminal on the driving grid copper foil and the power semiconductor chip in the right bridge arm.
5. The package structure of a power semiconductor module according to any one of claims 1 to 4, wherein: in the power semiconductor chips, a source electrode of each power semiconductor chip is independently led out of a bonding wire to be electrically connected with an independent signal terminal, and a Kelvin structure is formed.
6. The package structure of a power semiconductor module according to claim 1, wherein: the copper-clad ceramic substrate is an aluminum nitride copper-clad ceramic substrate, and the back of the copper-clad ceramic substrate is provided with a lower copper foil which is used for being connected with a radiator so as to improve the heat radiation performance.
7. The package structure of a power semiconductor module according to claim 6, wherein: and the periphery edge of the lower copper foil is etched with uniform and equidistant holes.
8. The package structure of a power semiconductor module according to claim 1, wherein: the upper copper foil comprises a plurality of functional copper foils which are partitioned independently, and each functional copper foil is welded with a terminal.
9. The package structure of a power semiconductor module according to claim 8, wherein: the terminal is a pin terminal with a curved buffer structure in the middle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322530175.0U CN220934073U (en) | 2023-09-15 | 2023-09-15 | Packaging structure of power semiconductor module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322530175.0U CN220934073U (en) | 2023-09-15 | 2023-09-15 | Packaging structure of power semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220934073U true CN220934073U (en) | 2024-05-10 |
Family
ID=90968011
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322530175.0U Active CN220934073U (en) | 2023-09-15 | 2023-09-15 | Packaging structure of power semiconductor module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220934073U (en) |
-
2023
- 2023-09-15 CN CN202322530175.0U patent/CN220934073U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104716128A (en) | Power module, power converter and method for manufacturing power module | |
| KR20160038771A (en) | Semiconductor device | |
| WO2023000823A1 (en) | Novel packaging structure for power semiconductor module | |
| CN111106098B (en) | Power module with low parasitic inductance layout | |
| US20220344310A1 (en) | Semiconductor module | |
| CN111916438B (en) | Silicon carbide Vienna rectifier half-bridge module packaging structure | |
| US20210407875A1 (en) | Semiconductor device | |
| CN109817612B (en) | Encapsulation structure for improving electrothermal performance of welded silicon carbide power module | |
| CN111554645B (en) | Double-sided water-cooling SiC half-bridge module packaging structure integrated with laminated busbar | |
| WO2022059251A1 (en) | Semiconductor device | |
| CN113517244A (en) | Novel packaging structure of power semiconductor module | |
| CN111146164B (en) | Packaging structure of wide-bandgap power module suitable for severe environment | |
| CN115985899A (en) | Packaging structure and packaging method of power semiconductor module | |
| CN110634817B (en) | Packaging structure of hybrid power module composed of IGBT and MOSFET | |
| CN217822755U (en) | Adopt two-sided heat dissipation module's of graphite copper cushion packaging structure and electric automobile | |
| CN114093856A (en) | Multi-chip parallel half-bridge type MOSFET module | |
| CN220934073U (en) | Packaging structure of power semiconductor module | |
| CN216354202U (en) | Power device | |
| CN216213450U (en) | Silicon carbide power module of low return circuit inductance | |
| CN214381606U (en) | Packaging structure of low parasitic parameter power module | |
| CN219497798U (en) | Packaging structure of power semiconductor module | |
| CN210778570U (en) | Power semiconductor module, motor assembly and electric vehicle | |
| CN114664810A (en) | Wide bandgap power semiconductor module based on bypass copper column heat dissipation | |
| CN220172121U (en) | Packaging structure based on SOT-227 packaging module | |
| CN219917162U (en) | Power module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |