CN220755377U - Chip packaging structure and memory - Google Patents

Abstract

The utility model discloses a chip packaging structure, comprising: a substrate; the substrate comprises a WB chip, wherein one surface of the WB chip is provided with a bonding pad, the WB chip is reversely arranged on the substrate, and the bonding pad faces the substrate; the substrate is provided with an electric connection area corresponding to the position of the bonding pad on one surface facing the WB chip, and an electric connection part connected with the bonding pad in a welding way is arranged at the electric connection area. According to the utility model, the electric connection part on the substrate and the bonding pad on the WB chip are connected with each other in a flip-chip bonding mode, and the packaging is completed without adopting a wire bonding mode, so that the signal path length is shortened, the signal quality is improved, the heat dissipation can be effectively carried out, and the power consumption of the chip is reduced.

Description

Chip packaging structure and memory

Technical Field

The present utility model relates to the field of chip packaging technologies, and in particular, to a chip packaging structure and a memory.

Background

In the current information society, high-speed, high-quality and multifunctional products are demanded, and the product appearance is moving toward light, thin, short and small trends. The electronic products generally have semiconductor chips and carriers electrically connected with the semiconductor chips, wherein WB chips are generally packaged by Wire Bonding (WB), however, the signal paths of Wire bonding are long, which results in high power consumption and low heat dissipation efficiency; and wire bonding operations are cumbersome, most high power applications require multiple thick wire bonds, so that the number of connection points is large, and the higher the occurrence of faults.

Disclosure of Invention

The utility model mainly aims to provide a chip packaging structure and aims to solve the problems of complicated steps, high power consumption and low heat dissipation efficiency when a WB chip adopts wire bonding.

In order to achieve the above object, the present utility model provides a chip package structure, comprising:

a substrate;

the substrate comprises a WB chip, wherein one surface of the WB chip is provided with a bonding pad, the WB chip is reversely arranged on the substrate, and the bonding pad faces the substrate;

the substrate is provided with an electric connection area corresponding to the position of the bonding pad on one surface facing the WB chip, and an electric connection part connected with the bonding pad in a welding way is arranged at the electric connection area.

In some embodiments, the bonding pads are provided in plurality, and the electrical connection regions are correspondingly provided in plurality, and the plurality of bonding pads are arranged on one side of the WB chip along a straight line direction.

In some embodiments, further comprising:

and the glue layer is arranged on the substrate and is adhered and connected with the WB chip.

In some embodiments, the glue layer is uniform in height with the electrical connection.

In some embodiments, further comprising:

and the main control chip is positioned on the WB chip and is bonded with the substrate through a lead.

In some embodiments, further comprising:

and the shell is covered on the substrate to encapsulate the WB chip and the main control chip.

The utility model further provides a memory, which comprises a main board and the chip packaging structure recorded in the embodiment, wherein the chip packaging structure is arranged on the main board.

According to the utility model, the WB chip is flip-chip welded on the substrate, so that the electric connection part on the substrate and the bonding pad on the WB chip are connected with each other, and the packaging is completed without adopting a wire bonding mode, so that the packaging step of the WB chip is simplified, the signal path length is shortened, the signal quality is improved, the heat dissipation can be effectively carried out, and the chip power consumption is reduced.

Drawings

FIG. 1 is a top view of an embodiment of a chip package structure according to the present utility model;

FIG. 2 is a front view of another embodiment of a chip package structure according to the present utility model;

FIG. 3 is a right side view of a further embodiment of a chip package structure according to the present utility model;

fig. 4 is a top view of a WB chip according to another embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made more clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.

Due to the different connection modes, when the chips leave the factory, there is a corresponding distinction, for example, the Bonding pads 110 of the WB (Wire Bonding) chip 100 are distributed at the edge positions of the WB chip 100, and are generally packaged by adopting a Wire Bonding mode, which cannot meet the packaging requirements of different sizes, so that the WB chip 100 has very limited application scenarios.

The present utility model provides a chip package structure, as shown in fig. 1 to 4, comprising:

a substrate 200;

the WB chip 100, one surface of the WB chip 100 is provided with a bonding pad 110, the WB chip 100 is flip-chip placed on the substrate 200, and the bonding pad 110 faces the substrate 200;

wherein, the surface of the substrate 200 facing the WB chip 100 is provided with an electrical connection area corresponding to the position of the pad 110, and the electrical connection area is provided with an electrical connection portion welded to the pad 110.

The substrate 200 is classified into various types according to reinforcing materials of the board: paper base, glass fiber cloth base, composite base, laminated multilayer board base and special material base. Preferably, the present utility model employs BT plates (Bismaleimide Triazine, bismaleimide modified triazine resin) in fiberglass cloth base, which have very high glass transition temperature (Tg), excellent dielectric properties, low thermal expansion and good mechanical characteristics, and are more suitable for encapsulation.

In order to connect the substrate 200 to the bonding pads 110 on the WB chip 100, an electrical connection area is provided in a region of the substrate 200 opposite to the bonding pads 110, that is, the substrate 200 is windowed to expose metal lines in the substrate 200, so that the WB chip 100 and the substrate 200 are connected. It should be noted that not all pads 110 on WB chip 100 need to be connected to substrate 200, and for some meaningless pads 110, no electrical connection area needs to be provided on substrate 200.

An electrical connection portion is provided on the electrical connection region of the substrate 200 so that the WB chip 100 performs signal transmission through the electrical connection portion. Specifically, the electrical connection portion is formed of a material capable of conducting electricity, and by way of example, the material of the electrical connection portion may be a metallic material or a combination thereof, and may include gold, silver, copper, lead, tin, etc., as well as alloys of various components. For example, the electrical connection includes a metal line on the substrate 200 and a solder bump 210 disposed on the metal line. The material of the solder bump 210 can be divided into three types: the high temperature solder (95% Pb-5% Sn and 97% Pb-3% Sn, etc.), the medium temperature solder (96.5% Sn-3.0% Ag-0.5% Cu,99% Sn-0.3% Ag-0.7% Cu and 96.5% Sn-3.5% Ag, etc.) having a melting point exceeding 250 ℃ and the low temperature solder (37% Pb-63% Sn eutectic, 42% Sn-58% Bi eutectic, 48% Sn-52% in, etc.) having a melting point lower than 200 ℃ may be selected according to practical situations.

It should be noted that, the WB chip 100 is a normal chip in a general sense, and the bonding pad 110 of the WB chip 100 is connected to the substrate 200 by a gold wire, that is, wire bonding, and since the side of the WB chip 100 on which the bonding pad 110 is disposed faces away from the substrate 200, a certain space is required to accommodate the gold wire. In the embodiment, the face, provided with the bonding pad 110, of the WB chip 100 faces the substrate 200 in a flip-chip manner, so that the connection distance between the bonding pad 110 and the substrate 200 is shorter, the signal transmission delay is reduced, the adaptation frequency of the transmission signal is greatly improved, signals in a wider range can be transmitted, heat dissipation can be effectively performed, and the power consumption of the WB chip 100 is reduced.

As shown in fig. 4, in some embodiments, the pads 110 are provided in plurality and the electrical connection regions are correspondingly provided in plurality, and the plurality of pads 110 are arranged on one side of the WB chip 100 in a straight direction. The WB chip 100 is a chip on which a package is generally completed using wire bonding, and a plurality of pads 110 are arranged, and positions of the pads 110 are set at one side of the WB chip 100 to facilitate connection with electrical connections.

As shown in fig. 2, in some embodiments, the chip package structure further includes:

the glue layer 300 is disposed on the substrate 200 and is adhered to the WB chip 100.

Specifically, when the WB chip 100 is fixed on the substrate 200, the adhesive layer 300 plays a role of adhesion and support, preventing the WB chip 100 from being damaged due to unstable connection between the WB chip 100 and the substrate 200. It is understood that the glue layer 300 is merely meant to be a substance that serves as a paste support and that any material that serves the same purpose is intended to be within the scope of the present utility model. Such as an epoxy resin. The epoxy resin has high bonding strength, good tensile strength and strong adhesive force, and is more suitable for being used as a material for supporting and bonding the WB chip 100. Alternatively, epoxy thermosetting films, which are generally composed of various materials such as epoxy resins, organosilicon compounds, etc., can also be used, and have high heat resistance, adhesive strength and reliability.

As shown in fig. 2, in some embodiments, the glue layer 300 is consistent with the height of the electrical connection. Specifically, a proper amount of UV glue or other glue is applied to the position of the substrate 200 corresponding to the WB chip 100, so that when the WB chip 100 is connected to the substrate 200, the height of the last formed glue layer 300 is kept consistent with the height of the electrical connection portion, and at this time, the glue layer 300 plays a main supporting role on the WB chip 100, so as to prevent the electrical connection portion from being damaged, resulting in unstable connection. Preferably, the underfill is used to fill the solder joints, to better protect the solder joints, to reduce package stress damage, to improve the mechanical strength of the solder joints, and to improve the service life of the package.

As shown in fig. 1 to 3, in some embodiments, the chip package structure further includes:

the main control chip 400, the main control chip 400 is located on the WB chip 100 and is wire-bonded with the substrate 200.

In this embodiment, the WB chip 100 is generally used as a memory chip, and the main control chip 400 is required to control the read/write operation of the memory, wherein the main control chip 400 is bonded to the WB chip 100. Due to the rapid development of digitization, different types of devices require different kinds of data storage chips, thereby better achieving respective performance and capacity requirements. By determining the memory capacity of the WB chip 100 and the required parameters such as read-write speed, power consumption, interface, etc., a suitable main control chip 400 is selected to ensure that the chip has correct performance and compatibility.

In some embodiments, the chip package structure further comprises:

the housing is covered on the substrate 200 to encapsulate the WB chip 100 and the main control chip 400.

The shell for packaging the WB chip 100 and the main control chip 400 plays roles of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, is also a bridge for communicating the WB chip 100 with an external circuit, contacts on the chip are connected to pins of the shell by wires, and the pins are connected with other devices by wires on a printed board to complete signal transmission.

According to the chip packaging structure provided by the utility model, the electric connection part on the substrate 200 and the bonding pad 110 on the WB chip 100 are connected with each other in a flip-chip bonding mode, and packaging is completed without adopting a wire bonding mode, so that the signal path length is shortened, the signal quality is improved, the power consumption is reduced, and heat dissipation can be effectively performed.

The utility model also provides a memory, which comprises a main board and the chip packaging structure recorded in the embodiment, wherein the chip packaging structure is arranged on the main board. The specific structure of the chip packaging structure refers to the above embodiments, and since the memory adopts all the technical solutions of all the embodiments, at least all the technical effects brought by the technical solutions of the embodiments are provided, and will not be described in detail herein.

The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.

Claims (7)

1. A chip package structure, comprising:

a substrate;

the substrate comprises a WB chip, wherein one surface of the WB chip is provided with a bonding pad, the WB chip is reversely arranged on the substrate, and the bonding pad faces the substrate;

the substrate is provided with an electric connection area corresponding to the position of the bonding pad on one surface facing the WB chip, and an electric connection part connected with the bonding pad in a welding way is arranged at the electric connection area.

2. The chip package structure of claim 1, wherein the semiconductor package structure comprises a plurality of semiconductor chips,

the bonding pads are arranged in a plurality, the electric connection areas are correspondingly arranged in a plurality, and the bonding pads are arranged on one side of the WB chip along the straight line direction.

3. The chip package structure according to claim 1, further comprising:

and the glue layer is arranged on the substrate and is adhered and connected with the WB chip.

4. The chip package structure of claim 3, wherein the glue layer is uniform in height with the electrical connection.

5. The chip package structure according to claim 1, further comprising:

and the main control chip is positioned on the WB chip and is bonded with the substrate through a lead.

6. The chip package structure of claim 5, further comprising:

and the shell is covered on the substrate to encapsulate the WB chip and the main control chip.

7. A memory comprising a motherboard and the chip package structure of any one of claims 1-6, the chip package structure disposed on the motherboard.