CN219799662U - Mechanism for avalanche and conventional parallel test of Mosfet device - Google Patents
Mechanism for avalanche and conventional parallel test of Mosfet device Download PDFInfo
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- CN219799662U CN219799662U CN202321105824.6U CN202321105824U CN219799662U CN 219799662 U CN219799662 U CN 219799662U CN 202321105824 U CN202321105824 U CN 202321105824U CN 219799662 U CN219799662 U CN 219799662U
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- 238000012360 testing method Methods 0.000 title claims abstract description 145
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
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- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 9
- 238000001514 detection method Methods 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 2
- 108091006149 Electron carriers Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
The utility model discloses a mechanism for avalanche and conventional parallel testing of a Mosfet device, which relates to electronic device detection equipment and aims to solve the problems that the detection of a conventional field effect transistor is carried out in a single-tube single-test mode, and the detection efficiency is low, and the technical scheme is as follows: the integrated test box is connected with the semiconductor test board through a Cable line; the semiconductor test board is provided with a plurality of test bits which are arranged side by side, and the test bits are connected with the integrated test box through Cable lines to form a test loop. According to the utility model, a plurality of test bits are arranged side by side, and the test bits and the integrated test box form a test loop through the Cable line, so that a single operator can perform multi-station efficient operation through the plurality of test bits during manual detection, the test unit can connect the communicated test bits, the step-by-step test of components is satisfied, and the avalanche and conventional parallel test efficiency of the components is improved.
Description
Technical Field
The utility model relates to electronic device detection equipment, in particular to a mechanism for avalanche and conventional parallel testing of a Mosfet device.
Background
Silicon ICs can be classified into MOS-type and bipolar junction transistors, both of which can use either free electron carriers or holes as carriers. The Chinese character of MOSFET is called metal-oxide semiconductor field effect transistor, because the grid of the field effect transistor is isolated by the insulating layer, the field effect transistor is called an insulated gate field effect transistor.
The field effect transistor has a source electrode (S), a gate electrode (G), and a drain electrode (D), and the conductivity between the drain electrode and the source electrode is changed by applying a voltage to the gate electrode to control the current.
There is therefore a need to propose a new solution to this problem.
Disclosure of Invention
Aiming at the defects existing in the prior art, the utility model aims to provide a mechanism for avalanche and conventional parallel test of a Mosfet device.
The technical aim of the utility model is realized by the following technical scheme: the mechanism for avalanche and conventional parallel test of the Mosfet device comprises a semiconductor test board and an integrated test box, wherein the integrated test box is connected with the semiconductor test board through a Cable wire;
the semiconductor test board is provided with a plurality of test bits which are arranged side by side, the test bits are connected with the integrated test box through Cable lines to form a test loop, and the test bits are used for being connected with components to be tested in a plug-in mode.
The utility model is further provided with: and the integrated test box is provided with a plurality of test units communicated with the test position to form a test loop.
The utility model is further provided with: the integrated test box comprises a plug-and-play base, plug-and-play positions with the same number as the test positions are arranged on the plug-and-play base, and the plug-and-play positions are used for plug-and-play connection with each test unit.
The utility model is further provided with: the test unit comprises a shielding box and a test module arranged in the shielding box, wherein an instant socket is arranged at the bottom end of the shielding box, and an instant socket penetrating through the instant socket and being spliced with the test module is arranged on the instant socket base.
The utility model is further provided with: the test module is provided with a test indicator lamp and a test serial port, and the shielding box is provided with a through hole corresponding to the test indicator lamp and a through slot for accommodating the test serial port to pass through.
The utility model is further provided with: the semiconductor test board is provided with a serial port electrically connected with the test bit, and an avalanche inductor and a grid resistor are electrically connected between the serial port and the test bit.
The utility model is further provided with: the test site is provided with a base, the base is provided with pin bit slots corresponding to the source electrode, the grid electrode and the drain electrode respectively, and clamping structures used for clamping the source electrode, the grid electrode and the drain electrode are arranged in the pin bit slots respectively.
The utility model is further provided with: the clamping structure comprises a plurality of symmetrically arranged metal contact pieces, an elastic piece connected with the metal contact pieces is arranged in the base, and the elastic piece is used for providing acting forces for mutually abutting the symmetrically arranged metal contact pieces.
In summary, the utility model has the following beneficial effects:
through setting up a plurality of test bits that set up side by side to the test bit constitutes test circuit through Cable line and integrated test box, realizes when artifical the detection, and single operating personnel carries out the high-efficient operation of multistation is realized to a plurality of test bits of accessible, and the setting up of test unit can realize connecting the test bit of looks UNICOM, satisfies and tests step by step the components and parts, has improved the efficiency of components and parts avalanche and conventional parallel test.
Drawings
FIG. 1 is a schematic diagram of an integrated test cartridge according to the present utility model;
FIG. 2 is a schematic diagram of a semiconductor test board according to the present utility model;
FIG. 3 is an exploded view of the integrated test cartridge of the present utility model;
fig. 4 is an enlarged view at a in fig. 2.
In the figure: 1. a semiconductor test board; 2. an integrated test box; 21. a test unit; 22. a plug-and-play base; 221. plug-and-play; 211. a shielding box; 222. plug-and-play interfaces; 212. testing a serial port; 213. a through hole; 11. a base; 12. pin slots; 13. a metal contact.
Detailed Description
The present utility model will be described in detail below with reference to the accompanying drawings and examples.
The utility model provides a mechanism of Mosfet device avalanche and conventional parallel test, as shown in fig. 1 and 2, including semiconductor test board 1 and integrated test box 2, integrated test box 2 passes through Cable line connection with semiconductor test board 1, through the electrical property and the data connection of integrated test box 2 with semiconductor test board 1, realize can carrying out the test to the MOS components and parts that load on semiconductor test board 1, and set up a plurality of test bits of setting side by side on the semiconductor test board 1, the test bit passes through Cable line connection and constitutes test circuit with integrated test box 2, the test bit is used for being connected with the components and parts that await measuring plug-in type, specifically, in this embodiment, semiconductor test board 1 is based on the PCB board, when pegging graft to the test bit through three pins of the MOS components and parts of field effect transistor for example, can carry out batch detection to the components and parts.
As shown in fig. 1 and fig. 3, the integrated test box 2 includes a plug-and-play base 22 and test units 21 detachably mounted on the plug-and-play base 22, the plug-and-play base 22 is provided with plug-and-play positions 221 with the same number of test positions, the test units 21 are mounted on the plug-and-play base 22 through the plug-and-play positions 221, and a power supply module and a central processing unit matched with the plug-and-play base 22 can coordinate and supply a plurality of test units 21 for power supply and data storage and transmission, and each test unit 21 is communicated with each test position to form a test loop, so that a plurality of parallel test loops are formed, and independent test of a plurality of field effect transistors is realized.
The test unit 21 includes a shielding box 211 and a test module built in the shielding box 211, the test module is provided with a test indicator lamp and a test serial port 212, the shielding box 211 is provided with a through hole 213 corresponding to the test indicator lamp and a through slot for accommodating the test serial port 212 to pass through, the bottom end of the shielding box 211 is provided with an instant socket, the instant socket is provided with an instant socket 222 penetrating the instant socket and being spliced with the test module, in the embodiment, the shielding box 211 is made of all-metal material, and particularly adopts aluminum material to form an integrated structure, so that the effect of shielding electromagnetic signals can be achieved to a certain extent, and the side, facing each other, of the shielding box 211 is provided with a radiating hole, the bottom end of the shielding box 211 is provided with a rectangular instant socket, and the instant socket is matched with the instant socket 222 at the bottom end of the test module, so that the test module is quickly connected with the instant socket and the instant socket 222, and the test unit 21 is convenient to replace according to the specific performance of the field effect tube by people.
As shown in fig. 2, the semiconductor test board 1 is provided with a serial port electrically connected with a test site, an avalanche inductor and a gate resistor are electrically connected between the serial port and the test site, a base 11 is provided on the test site, pin slots 12 corresponding to a source electrode, a gate electrode and a drain electrode are provided on the base 11, clamping structures for clamping the source electrode, the gate electrode and the drain electrode are provided in the pin slots 12, when pins of the source electrode, the gate electrode and the drain electrode are inserted into the pin slots 12 on the base 11 through the clamping structures, connection stability of the source electrode, the gate electrode and the drain electrode can be further improved through the clamping forces, so that the detection precision is improved.
The above description is only a preferred embodiment of the present utility model, and the protection scope of the present utility model is not limited to the above examples, and all technical solutions belonging to the concept of the present utility model belong to the protection scope of the present utility model. It should be noted that modifications and adaptations to the present utility model may occur to one skilled in the art without departing from the principles of the present utility model and are intended to be within the scope of the present utility model.
Claims (8)
1. A mechanism for avalanche and conventional parallel test of a Mosfet device is characterized in that: the integrated test box (2) is connected with the semiconductor test board (1) through Cable wires;
the semiconductor test board (1) is provided with a plurality of test bits which are arranged side by side, the test bits are connected with the integrated test box (2) through Cable lines to form a test loop, and the test bits are used for plug-in connection with components to be tested.
2. The mechanism for avalanche and conventional parallel testing of Mosfet devices according to claim 1, wherein: and the integrated test box (2) is provided with a plurality of test units (21) communicated with the test positions to form a test loop.
3. The mechanism for avalanche and conventional parallel testing of Mosfet devices according to claim 2, wherein: the integrated test box (2) comprises a plug-and-play base (22), plug-and-play positions (221) with the same number as the test positions are arranged on the plug-and-play base (22), and the plug-and-play positions (221) are used for being connected with all the test units (21) in a plug-and-pull mode.
4. A Mosfet device avalanche and conventional parallel testing mechanism according to claim 3, wherein: the test unit (21) comprises a shielding box (211) and a test module which is arranged in the shielding box (211), an instant socket is arranged at the bottom end of the shielding box (211), and an instant socket penetrating through the instant socket and being spliced with the test module is arranged on the instant socket base (22).
5. The mechanism for avalanche and conventional parallel testing of Mosfet devices according to claim 4, wherein: the test module is provided with a test indicator lamp and a test serial port (212), and the shielding box (211) is provided with a through hole (213) corresponding to the test indicator lamp and a through slot for accommodating the test serial port (212) to pass through.
6. The mechanism for avalanche and conventional parallel testing of Mosfet devices according to claim 1, wherein: the semiconductor test board (1) is provided with a serial port electrically connected with the test bit, and an avalanche inductor and a grid resistor are electrically connected between the serial port and the test bit.
7. The mechanism for avalanche and conventional parallel testing of Mosfet devices according to claim 6, wherein: the test site is provided with a base (11), the base (11) is provided with pin bit slots (12) corresponding to the source electrode, the grid electrode and the drain electrode respectively, and clamping structures used for clamping the source electrode, the grid electrode and the drain electrode are arranged in the pin bit slots (12) respectively.
8. The mechanism for avalanche and conventional parallel testing of Mosfet devices according to claim 7, wherein: the clamping structure comprises a plurality of symmetrically arranged metal contact pieces (13), an elastic piece connected with the metal contact pieces (13) is arranged in the base (11), and the elastic piece is used for providing acting forces for mutually abutting the symmetrically arranged metal contact pieces (13).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321105824.6U CN219799662U (en) | 2023-05-08 | 2023-05-08 | Mechanism for avalanche and conventional parallel test of Mosfet device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321105824.6U CN219799662U (en) | 2023-05-08 | 2023-05-08 | Mechanism for avalanche and conventional parallel test of Mosfet device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219799662U true CN219799662U (en) | 2023-10-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321105824.6U Active CN219799662U (en) | 2023-05-08 | 2023-05-08 | Mechanism for avalanche and conventional parallel test of Mosfet device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219799662U (en) |
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2023
- 2023-05-08 CN CN202321105824.6U patent/CN219799662U/en active Active
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