CN219287802U

CN219287802U - Structure beneficial to heat dissipation of FPC patch

Info

Publication number: CN219287802U
Application number: CN202223281143.3U
Authority: CN
Inventors: 吴子钧; 江小勇; 沈强; 蔡新志
Original assignee: Zhuhai Kainuo Microelectronics Co ltd
Current assignee: Zhuhai Kainuo Microelectronics Co ltd
Priority date: 2022-12-06
Filing date: 2022-12-06
Publication date: 2023-06-30
Anticipated expiration: 2032-12-06

Abstract

A structure beneficial to FPC patch heat dissipation comprises a first circuit layer, a second circuit layer, a first PI layer, a solder mask layer and a resin adhesive layer in a patch structure corresponding to an IC area; the first circuit layer and the second circuit layer are copper-money-shaped hollowed-out copper layers; the first PI layer is provided with a via hole, and the first circuit layer and the second circuit layer are connected in a conducting way through the via hole; the lower bottom surface of the solder mask layer is attached to the first circuit layer, and the upper top surface of the resin adhesive layer is attached to the second circuit layer; the copper coin-shaped hollowed-out copper layer is adopted, and the square grids and the hexagonal grids are connected with each other, so that dense hollowed-out arrangement is formed, and electromagnetic signal interference is reduced; compared with a copper layer with a large plane, the hollowed-out copper layer greatly reduces heat accumulation; meanwhile, the copper coin-shaped hollowed-out copper layer can form a concave-convex occlusion structure with other structural layers, so that the occlusion degree between the layers is improved, and the solder mask layer is prevented from falling off due to heating.

Description

Structure beneficial to heat dissipation of FPC patch

Technical Field

The utility model relates to the field of FPC (flexible printed circuit), in particular to a structure beneficial to heat dissipation of an FPC patch.

Background

In the technology of FPC paster, in the FPC paster structure of the device area such as IC, devices such as IC often produce a large amount of heat because of calculation of data and electric current circulation, and in order not to influence electromagnetic interference, the ground network in FPC paster adopts the solid copper layer of large-plane, the solid copper layer is through the long-time heat absorption leading to harsh reprocessing and service environment, to the solder resist oil ribbon of FPC paster serious challenge, there is the problem that the solder resist layer foams and drops; the square grid copper layer is adopted, the hollowed-out area is large, and the problem of electromagnetic interference exists.

Disclosure of Invention

In order to overcome the defects of the prior art, the utility model provides a structure beneficial to heat dissipation of an FPC patch, and aims to solve the problems of bubbling and falling off of a solder mask and electromagnetic interference and realize the purposes of preventing the bubbling and falling off of the solder mask and reducing the electromagnetic interference.

In order to solve the problems, the technical scheme adopted by the utility model is as follows:

a structure beneficial to FPC patch heat dissipation comprises a first circuit layer, a second circuit layer, a first PI layer, a solder mask layer and a resin adhesive layer in a patch structure corresponding to an IC area; the first circuit layer and the second circuit layer are copper-money-shaped hollowed-out copper layers; the first PI layer is provided with a via hole, and the first circuit layer and the second circuit layer are connected in a conducting way through the via hole; the lower bottom surface of the solder mask layer is attached to the first circuit layer, and the upper top surface of the resin adhesive layer is attached to the second circuit layer.

The patch structure further comprises a second PI layer, and the upper top surface of the second PI layer is attached to the resin adhesive layer.

Further, in the first circuit layer and the second circuit layer, the copper coin-shaped hollowed-out copper layer adopts a square grid and four hexagonal grids in combination, and the hexagonal grids are attached to four sides of the square grid.

And a concave-convex engagement structure is formed between the solder mask layer and the first circuit layer and between the resin adhesive layer and the second circuit layer.

Further, the solder mask layer is provided with a reserved hole, and the welding disc is connected with the first circuit layer through the reserved hole.

Further, the bond pad is also connected to a ground pin terminal of the IC device.

Further, the square grid and the hexagonal grid have grid line frames ranging from 0.1mm to 0.2mm.

Further, the first circuit layer and the second circuit layer are connected with the circuit grounding end.

Compared with the prior art, the utility model has the beneficial effects that: the copper coin-shaped hollowed-out copper layer is adopted, and the square grids and the hexagonal grids are connected with each other, so that dense hollowed-out arrangement is formed, and electromagnetic signal interference is reduced; compared with a copper layer with a large plane, the hollowed-out copper layer greatly reduces heat accumulation; meanwhile, the copper coin-shaped hollowed-out copper layer can form a concave-convex occlusion structure with other structural layers, so that the occlusion degree between the layers is improved, and the solder mask layer is prevented from falling off due to heating.

The utility model is described in further detail below with reference to the drawings and the detailed description.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a schematic structural diagram of a structure for facilitating heat dissipation of an FPC patch according to an embodiment of the present utility model;

fig. 2 is a schematic structural diagram of a copper coin-shaped hollowed-out copper layer according to an embodiment of the utility model.

Detailed Description

Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be practiced or carried out in other embodiments and details in the present description may be varied or modified from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.

In a patch structure corresponding to an IC area, as shown in fig. 1, the structure comprises a solder mask layer 1, a first circuit layer 2, a first PI layer 3, a second circuit layer 4, a resin adhesive layer 5 and a second PI layer 6 from top to bottom in sequence; wherein the first circuit layer 2 and the second circuit layer 4 are connected with the IC device.

The lower bottom surface of the solder mask layer 1 is attached to the first circuit layer 2, the first circuit layer 2 is connected with the second circuit layer 4 through the first PI layer 3, the upper top surface of the resin adhesive layer 5 is attached to the second circuit layer 4, and the upper top surface of the second PI layer 6 is attached to the resin adhesive layer 5.

The first circuit layer 2 and the second circuit layer 4 are copper-coin-shaped hollowed-out copper layers; the first PI layer 3 is provided with a via hole 30, and the first circuit layer 2 and the second circuit layer 4 are connected to each other through the via hole 30.

Further, as shown in fig. 2, in the first circuit layer 2 and the second circuit layer 4, the copper-coin-shaped hollowed copper layer adopts a combination of square grids and four hexagonal grids, the hexagonal grids are attached to four sides of the square grids, the hexagonal grids comprise four inner angles of 135 degrees and two inner angles of 45 degrees, and the inner angles of the square grids attached to the hexagonal grids are 135 degrees; adopt copper coin form fretwork copper layer, compare in square grid's setting, square grid and hexagonal grid are mutually combined, have more closely-packed structure, when guaranteeing that first circuit layer 2 and second circuit layer 4 reducible electromagnetic signal interference, kept the heat dissipation of first circuit layer 2 and second circuit layer 4.

Further, the square grid and the hexagonal grid have grid frames ranging from 0.1mm to 0.2mm, and the smaller-range grid frames are adopted, so that heat dissipation of the first circuit layer 2 and the second circuit layer 4 is increased.

The solder mask layer 1 is provided with a reserved hole 10, the welding disk is connected with the first circuit layer 2 through the reserved hole 10, and the other end of the welding disk is connected with the grounding pin end of the IC device; further, the ground pin end of the IC device is connected to the first circuit layer 2 through the via hole 10, and the first circuit layer 2 and the second circuit layer 4 are connected to each other through the via hole 30, the first circuit layer 2 and the second circuit layer 4 are grounded copper layers, the first circuit layer 2 and the second circuit layer 4 are connected to the ground end, and the ground pin end of the IC device is connected to the ground end.

A concave-convex engagement structure is formed between the solder mask layer 1 and the first circuit layer 2 and between the resin adhesive layer 5 and the second circuit layer 4; after a large-area solid copper is set to be a copper-coin-shaped grid copper layer, the plane state is adjusted to be a three-dimensional state, the solder mask layer 1 is flatly paved and covered on the first circuit layer 2 and is mutually attached and connected with the first circuit layer 2 to form a concave-convex occlusion structure, and the occlusion force of the solder mask layer 1 and the first circuit layer 2 is improved; likewise, when the upper top surface of the resin adhesive layer 5 is attached to the second circuit layer 4, a concave-convex engagement structure is formed with the second circuit layer 4, so that the engagement force between the resin adhesive layer 5 and the second circuit layer 4 is improved; after the first circuit layer 2 and the second circuit layer 4 are designed by adopting copper-coin-shaped grids, a concave-convex meshing structure is formed between the first circuit layer 2 and the second circuit layer and the solder mask layer 1 and the resin adhesive layer 5 correspondingly, so that meshing degree among the layers is greatly improved, and dropping of the solder mask layer 1 is effectively reduced.

In the utility model, a copper-coin-shaped hollowed-out copper layer is adopted, square grids and hexagonal grids are connected with each other, so that dense hollowed-out arrangement is formed, and electromagnetic signal interference is reduced; compared with a copper layer design of large-area tiling, the area of sixty percent to eighty percent of copper layer is reduced, and heat accumulation is greatly reduced; meanwhile, a concave-convex engagement structure is formed between the solder mask layer and the first circuit layer and between the resin adhesive layer and the second circuit layer, so that the engagement degree between the layers is improved, and the solder mask layer is prevented from falling off due to heating.

The above embodiments are only preferred embodiments of the present utility model, and the scope of the present utility model is not limited thereto, but any insubstantial changes and substitutions made by those skilled in the art on the basis of the present utility model are intended to be within the scope of the present utility model as claimed.

Claims

1. A structure beneficial to FPC patch heat dissipation is characterized in that in a patch structure corresponding to an IC area, the structure comprises a first circuit layer, a second circuit layer, a first PI layer, a solder mask layer and a resin adhesive layer; the first circuit layer and the second circuit layer are copper-coin-shaped hollowed-out copper layers; the first PI layer is provided with a via hole, and the first circuit layer and the second circuit layer are connected in a conducting way through the via hole; the lower bottom surface of the solder mask layer is attached to the first circuit layer, and the upper top surface of the resin adhesive layer is attached to the second circuit layer.

2. The structure of claim 1, further comprising a second PI layer, wherein an upper top surface of the second PI layer is attached to the resin adhesive layer.

3. The structure of claim 1, wherein the copper-money-shaped hollowed-out copper layer in the first circuit layer and the second circuit layer is a combination of a square grid and four hexagonal grids, and the hexagonal grids are attached to four sides of the square grid.

4. A structure for facilitating heat dissipation of an FPC patch according to claim 3, wherein a concave-convex engagement structure is formed between said solder resist layer and said first wiring layer, and between said resin adhesive layer and said second wiring layer.

5. A structure for facilitating heat dissipation of an FPC patch according to claim 3, wherein the solder mask layer is provided with a hole, and the solder pad is connected to the first circuit layer through the hole.

6. The structure of claim 5, wherein the bonding pad is further connected to a ground pin of the IC device.

7. A structure for facilitating heat dissipation of FPC patch according to claim 3, wherein the square grid and the hexagonal grid have grid line frames ranging from 0.1mm to 0.2mm.

8. The structure of claim 4, wherein the first circuit layer and the second circuit layer are connected to a circuit ground.