CN219205144U - Chip packaging structure - Google Patents

Abstract

The utility model discloses a chip packaging structure, which comprises a packaging substrate, a bare chip and a plastic sealing layer, wherein the bare chip comprises a device substrate, a device functional area and a first bonding pad which are arranged above the device substrate, a surrounding layer surrounding the device functional area is arranged between the device functional area and the first bonding pad, a sealing layer is arranged on the surrounding layer, a cavity is formed among the sealing layer, the surrounding layer and the device substrate, the device functional area is arranged in the cavity, the first bonding pad is arranged outside the cavity, the device substrate is attached to the packaging substrate, a second bonding pad is arranged on the packaging substrate, the second bonding pad is connected with the first bonding pad through a lead, and the plastic sealing layer is arranged on the packaging substrate and covers the bare chip, the surrounding layer, the sealing layer, the second bonding pad and the lead. The first bonding pad is connected with the second bonding pad on the packaging substrate in a wire bonding mode, so that the problems of virtual bonding and no residual gold existing in GGI flip-chip ultrasonic bonding are avoided, and the packaging reliability is effectively improved.

Description

Chip packaging structure

Technical Field

The present disclosure relates to chip packaging, and particularly to a chip packaging structure.

Background

Chip scale packaging (Wafer Level Chip Scale Packaging, WLCSP for short), i.e., wafer level chip packaging, is different from conventional chip packaging, and this latest technology is that packaging and testing are performed on a whole wafer, then individual chip particles are cut, and then packaged into modules; WLCSP is not only an important technology to achieve high density, high performance packages and sips, but will also play a key role in device embedded PCB technology.

Referring to fig. 1, a surface acoustic wave filter is generally packaged by a Chip Size Package (CSP) at present, but the heat of the filter package structure formed by the chip size package is transferred only through a solder joint with a small area, most of the heat is concentrated in a middle device functional area and is difficult to transfer out, and reliability instability is easily caused by GGI flip-chip bonding problem.

Disclosure of Invention

The utility model aims to overcome the defects in the prior art and provides a chip packaging structure.

In order to achieve the above object, the technical scheme of the present utility model is as follows:

the utility model provides a chip packaging structure, includes package substrate, wave filter chip and plastic envelope, the bare chip includes device substrate and device functional region and the first pad of top, be equipped with between device functional region and the first pad and encircle the enclose of device functional region keeps off the layer, enclose and be equipped with the closing cap on the layer, the closing cap enclose keep off the layer with form the cavity between the device substrate, the device functional region is located in the cavity, first pad is located outside the cavity, the device substrate paste dress in on the package substrate, be equipped with the second pad on the package substrate, the second pad with connect through the lead wire between the first pad, the plastic envelope is located package substrate is last and cladding bare chip, enclose keep off the layer, closing cap, second pad and lead wire.

Preferably, the bare chip is a surface acoustic wave filter chip.

Preferably, the projections of the capping layer and the first bonding pad on the device substrate do not overlap each other.

Preferably, the side edge of the cover layer is flush with the side edge of the enclosure layer away from the cavity.

Preferably, an adhesive layer is arranged between the device substrate and the packaging substrate, and the second bonding pad is arranged on the periphery of the adhesive layer.

Preferably, the adhesive layer is high-heat-conductivity silver colloid.

Preferably, the thickness of the surrounding barrier layer is in the range of 10-50 μm; the thickness of the capping layer ranges from 10 to 50 μm.

Preferably, the packaging substrate is also provided with a radio frequency switch, a duplexer and/or a power amplifier; the radio frequency switch, the duplexer and/or the power amplifier are/is attached to the packaging substrate and are covered by the plastic layer.

Preferably, the enclosing layer and the cover layer are photosensitive organic dry films.

Preferably, the device substrate is a substrate formed of piezoelectric single crystals or polycrystal such as lithium tantalate, lithium niobate, or crystal, or a substrate formed by bonding lithium tantalate, lithium niobate, or crystal with sapphire, silicon, alumina, spinel, crystal, or glass; the packaging substrate is a PCB.

Compared with the prior art, the utility model has the beneficial effects that:

(1) According to the chip packaging structure provided by the utility model, the device substrate is attached to the packaging substrate through the adhesive layer, and the adhesive layer adopts the high-heat-conductivity silver adhesive, so that heat generated during operation of the device functional area can be effectively conducted out, and the heat dissipation effect is improved.

(2) The chip packaging structure provided by the utility model has the advantages that the surrounding barrier layer is arranged between the device functional area and the first bonding pad, the sealing cover layer is covered on the surrounding barrier layer to form the cavity, and the first bonding pad is connected with the second bonding pad on the packaging substrate in a wire bonding mode, so that the problems of virtual bonding and no residual gold existing in GGI flip-chip ultrasonic bonding are avoided, and the packaging reliability is effectively improved.

(3) The chip packaging structure provided by the utility model can realize wafer level packaging, can reduce the thickness and the volume of the packaging structure by reducing the thickness of the device substrate, the wire bonding height and the thicknesses of the enclosure layer and the sealing layer, and is packaged on the packaging substrate together with radio frequency devices such as a radio frequency switch, a power amplifier, a duplexer and the like, thereby realizing high integration.

Drawings

FIG. 1 is a schematic diagram of a prior art chip package structure;

FIG. 2 is a schematic diagram of a chip package structure according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a DiFEM module according to an embodiment of the present application;

FIGS. 4-12 are process flow diagrams illustrating a method for fabricating a chip package structure according to an embodiment of the present application;

reference numerals: 1. packaging a substrate; 11. a second bonding pad; 2. a bare chip; 21. a device substrate; 22. a device functional region; 23. a first bonding pad; 24. a barrier layer; 25. a capping layer; 3. a plastic sealing layer; 4. a lead wire; 5. an adhesive layer; 6. a radio frequency switch.

Detailed Description

The utility model is further explained below with reference to the drawings and specific embodiments. The drawings of the present utility model are merely schematic to facilitate understanding of the present utility model, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.

Referring to fig. 2, an embodiment of the present application proposes a chip package structure, including a package substrate 1, a bare chip 2 and a plastic layer 3, where the bare chip 2 includes a device substrate 21 and a device functional area 22 and a first bonding pad 23 above the device substrate, and in one embodiment, the bare chip 2 is a surface acoustic wave filter chip, and the device substrate 21 is a substrate formed by piezoelectric single crystals or polycrystal such as lithium tantalate, lithium niobate or crystal, or a substrate formed by bonding lithium tantalate, lithium niobate or crystal with sapphire, silicon, alumina, spinel, crystal or glass; forming a device functional region 22 and a first pad 23 around the device functional region 22 on a device substrate 21, the device functional region 21 including an interdigital transducer and a reflector; the interdigital transducer comprises two interdigital electrodes which are arranged in an interposed way, wherein each interdigital electrode is respectively provided with an outgoing line which is opposite to the interposed direction, and the outgoing lines are electrically connected with the first bonding pads through conductive patterns. A barrier layer 24 surrounding the device functional region 22 is provided between the device functional region 22 and the first pad 23. The enclosure layer 24 is provided with a relief at the lead-out position, i.e. the enclosure layer 24 is disconnected at the lead-out position. Or the enclosure layer 24 may cover a portion of the lead-out wires or conductive patterns to form an enclosure. Preferably, the barrier 24 is a photosensitive organic dry film, and a pattern surrounding the device functional region 22 can be produced by photolithography and development. The enclosure layer 24 is provided with a sealing layer 25, the sealing layer 25 is covered above the enclosure layer 24, and forms a cavity together with the enclosure layer 24 and the device substrate 21, and preferably, the sealing layer 25 is a photosensitive organic dry film. The device functional area 22 is arranged in a cavity, and the cavity has a certain height so as to protect interdigital electrodes in the device functional area 22 from being damaged to realize surface acoustic wave transmission, and the first bonding pad 23 is arranged outside the cavity, so that subsequent welding is facilitated. The device substrate 21 with the cavity formed above the device functional region 22 is cut to obtain a modularized filter chip, which can be further packaged. The device substrate 21 is mounted on the package substrate 1, the package substrate 1 is provided with a second bonding pad 11, the second bonding pad 11 is connected with the first bonding pad 23 through a lead 4, and preferably, the package substrate 1 is a PCB board, the PCB board is provided with a plurality of second bonding pads 11 and conductive lines, and the second bonding pads 11 are connected with the first bonding pad 23 in a lead bonding manner. Therefore, the electric characteristic connection of the filter chip can be realized by adopting the traditional welding mode of wire bonding, the problems of virtual welding combination, no residual gold and the like existing in GGI flip-chip ultrasonic welding can be solved, and the reliability performance of chip packaging is effectively improved. The plastic layer 3 is disposed on the package substrate 1 and encapsulates the bare chip 2, the enclosure layer 24, the capping layer 25, the second bonding pad 11 and the leads 4. Specifically, the packaging substrate 1 can be subjected to plastic packaging by adopting a plastic packaging material to form a plastic packaging layer 3 which coats the bare chip 2, the enclosure layer 24, the cover sealing layer 25, the second bonding pad 11 and the lead 4, so that the reliability of the packaging structure is further improved.

In a specific embodiment, the projections of the capping layer 25 and the first pad 23 on the device substrate 21 do not overlap each other. Preferably, the sides of the cover layer 25 are flush with the sides of the enclosure layer 24 remote from the cavity. There is no capping layer 25 over the first pad 23, thus leaving enough operating space for wire bonding between the first pad 23 and the second pad 11 to avoid the presence of the capping layer 25 over the first pad 23 affecting the wire bonding process between it and the second pad 11.

In a specific embodiment, an adhesive layer 5 is disposed between the device substrate 21 and the package substrate 1, the adhesive layer 5 is high thermal conductive silver paste, the filter chip is attached to the package substrate 1 through the adhesive layer 5, and the high thermal conductive silver paste is used to attach the device substrate 21 to the package substrate 1, so that the heat dissipation area can be further increased, and the heat generated by the device functional area 22 in the working process of the filter chip is dissipated through the device substrate 21 and the package substrate 1. The second pad 11 is provided at the outer periphery of the adhesive layer 5 and is connected with the first pad 23 through the lead 4.

In a specific embodiment, the thickness of the device substrate 21 is in the range of 100-300 μm, and preferably, the thickness of the device substrate 21 is 150 μm; the thickness of the capping layer 25 ranges from 10 to 50 μm; the thickness of the barrier layer 24 ranges from 10 to 50 μm. By reducing the thickness of the device substrate 21, the height of the leads 4 on the device substrate 21, and the thicknesses of the barrier layer 24 and the capping layer 25, the size of the package structure is minimized, and the effect of chip-size packaging performance can be achieved.

Specifically, referring to fig. 3, the package substrate 1 is further provided with a radio frequency switch 6, a duplexer and/or a power amplifier, and the radio frequency switch 6, the duplexer and/or the power amplifier are attached to the package substrate 1 and are covered by the plastic layer 3. The rf switch 6 and the filter chip are integrated on the package substrate 1 to form a DiFEM module, and the multimode-multiband PA (power amplifier), the rf switch 6, the filter chip and the duplexer are integrated on the package substrate 1 to form a PAMiD module. Taking the DiFEM module as an example in fig. 3, on one hand, the filter chip may be attached to the package substrate 1 through the adhesive layer 5 and wire bonding may be performed to connect the first pad 23 and the second pad 11, on the other hand, the radio frequency switch 6 may be attached to the package substrate 1, and then the filter chip and the radio frequency switch 6 may be plastic-packaged together to form the DiFEM module.

Referring to fig. 2 and fig. 4-12, the embodiment of the present application further provides a method for manufacturing a chip package structure, which specifically includes the following steps:

(1) Referring to fig. 4, a bare chip 2 is provided, the bare chip 2 being a surface acoustic wave filter, the bare chip 2 including a device substrate 21, a device functional region 22 and a first pad 23, the device substrate 21 having a thickness in the range of 100-300 μm, the device functional region 22 and the first pad 23 being provided on the device substrate 21, the first pad 23 being provided at the periphery of the device functional region 22.

(2) Referring to fig. 5 and 6, a photosensitive organic dry film is attached on a device substrate 21 by vacuum lamination, and patterned by photolithography and development to form a barrier layer 24 having a thickness of 10-50 μm, the barrier layer 24 being disposed between a device functional region 22 and a first pad 23.

(3) Referring to fig. 7, a capping layer 25 having a thickness of 10-50 μm is capped on the barrier layer 24, a cavity is formed between the barrier layer 24, the capping layer 25 and the device substrate 21, the device functional region 22 is disposed in the cavity, and the first bonding pad 23 is disposed outside the cavity, facilitating subsequent soldering.

(4) Referring to fig. 8, a laser grooving process is used to remove the cover layer 25 outside the cavity and the enclosure layer 24, and the side edge of the cover layer 25 is flush with the side edge of the enclosure layer 24 away from the cavity, so as to expose the first bonding pad 23.

(5) Referring to fig. 9, dicing is performed along dicing streets between two adjacent filter chips on the device substrate 21, resulting in packaged individual filter chips.

(6) Referring to fig. 10 and 11, an adhesive layer 5 is coated on a package substrate 1, a device substrate 21 is attached to the adhesive layer 5, a plurality of individual filter chips are attached to the package substrate 1 through the adhesive layer 5, and a wire bonding process is used to bond a first pad 23 with a second pad 11 on the package substrate 1. The bonding layer 5 can be high heat conduction silver colloid, and can effectively improve the heat dissipation effect.

(7) Referring to fig. 12 and 2, a molding compound is used to perform plastic packaging on a packaging substrate 1 to form a molding layer 3 that encapsulates a bare chip 2, a surrounding layer 24, a capping layer 25, a lead 4 and a second bonding pad 11, and the molding layer is cut along a cutting path between two adjacent chip packaging structures on the packaging substrate 1 to obtain a single chip packaging structure, and each chip packaging structure is tested to obtain a qualified chip packaging structure.

According to the chip packaging structure provided by the embodiment of the application, the surrounding barrier layer 24 is arranged between the device functional area 22 of the bare chip 2 and the first bonding pad 23, the first bonding pad 23 is exposed, the bare chip 2 is attached to the packaging substrate 1 through the bonding layer 5, the bonding layer 5 is made of high-heat-conductivity silver colloid, the radiating effect of the filter chip can be effectively improved, the first bonding pad 23 and the second bonding pad 11 on the packaging substrate 1 are welded through a traditional wire bonding process, the problems of virtual welding combination and no gold residue existing in GGI flip-chip ultrasonic welding can be effectively solved, the reliability of the electric characteristic connection of the filter chip is effectively improved, in addition, the thickness and the volume of the packaging structure can be further reduced by further reducing the welding height of the device substrate 21 and the lead 4 and the thickness of the surrounding barrier layer 24 and the sealing cover layer 25, and the high integration with radio frequency devices such as a radio frequency switch 6, a power amplifier and a duplexer can be further integrated together, and high integration is realized.

The above embodiments are only for further illustrating the technical solution of the present utility model, but the present utility model is not limited to the embodiments, and any simple modification, equivalent variation and modification made to the above embodiments according to the technical substance of the present utility model falls within the protection scope of the technical solution of the present utility model.

Claims (10)

1. A chip packaging structure, characterized in that: the packaging structure comprises a packaging substrate, a bare chip and a plastic sealing layer, wherein the bare chip comprises a device substrate, a device functional area and a first bonding pad, wherein the device functional area is arranged above the device substrate, a surrounding layer surrounding the device functional area is arranged between the device functional area and the first bonding pad, a sealing layer is arranged on the surrounding layer, a cavity is formed between the surrounding layer and the device substrate, the device functional area is arranged in the cavity, the first bonding pad is arranged outside the cavity, the device substrate is attached to the packaging substrate, a second bonding pad is arranged on the packaging substrate, the second bonding pad is connected with the first bonding pad through a lead, and the plastic sealing layer is arranged on the packaging substrate and covers the bare chip, the surrounding layer, the sealing layer, the second bonding pad and the lead.

2. The chip package structure according to claim 1, wherein: the bare chip is a surface acoustic wave filter chip.

3. The chip package structure according to claim 1, wherein: the projections of the capping layer and the first bonding pad on the device substrate are not overlapped with each other.

4. The chip package structure according to claim 1, wherein: the side of the sealing layer is flush with the side of the enclosure layer, which is far away from the cavity.

5. The chip package structure according to claim 1, wherein: an adhesive layer is arranged between the device substrate and the packaging substrate, and the second bonding pad is arranged on the periphery of the adhesive layer.

6. The chip package structure according to claim 5, wherein: the bonding layer is high-heat-conductivity silver colloid.

7. The chip package structure according to claim 1, wherein: the thickness range of the surrounding barrier layer is 10-50 mu m; the thickness of the capping layer ranges from 10 to 50 μm.

8. The chip package structure according to claim 1, wherein: the packaging substrate is also provided with a radio frequency switch, a duplexer and/or a power amplifier; the radio frequency switch, the duplexer and/or the power amplifier are/is attached to the packaging substrate and are covered by the plastic layer.

9. The chip package structure according to claim 1, wherein: the enclosing layer and the cover layer are photosensitive organic dry films.

10. The chip package structure according to claim 1, wherein: the device substrate is a substrate formed by piezoelectric single crystals or polycrystal made of lithium tantalate, lithium niobate or crystal, or a substrate formed by bonding lithium tantalate, lithium niobate or crystal with sapphire, silicon, alumina, spinel, crystal or glass; the packaging substrate is a PCB.

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