CN111510099A

CN111510099A - Film bulk acoustic wave filter and wafer level packaging method thereof

Info

Publication number: CN111510099A
Application number: CN202010331091.2A
Authority: CN
Inventors: 魏德义; 盛荆浩; 江舟
Original assignee: Hangzhou Jianwenlu Technology Co Ltd
Current assignee: Hangzhou Jianwenlu Technology Co Ltd
Priority date: 2020-04-24
Filing date: 2020-04-24
Publication date: 2020-08-07

Abstract

The invention discloses a film bulk acoustic wave filter and a wafer level packaging method thereof, wherein a cover plate is bonded and fixed on the upper surface of a chip substrate to package and protect a resonator, an air cavity is arranged below a resonant film, and a gap is arranged between the cover plate and the resonator to ensure the normal work of the resonator.

Description

Film bulk acoustic wave filter and wafer level packaging method thereof

Technical Field

The invention relates to the technical field of semiconductor devices, in particular to a film bulk acoustic wave filter and a wafer level packaging method thereof.

Background

With the development of thin film and micro-nano manufacturing technology, electronic devices are rapidly developed in the direction of miniaturization, high-density multiplexing, high frequency and low power consumption. A Film Bulk Acoustic Resonator (FBAR) developed in recent years uses an advanced resonance technology, which converts electric energy into an acoustic wave by an inverse piezoelectric effect of a piezoelectric film to form resonance, and the resonance technology can be used for manufacturing advanced components such as a film frequency shaping device.

Unlike previous filters, FBAR filters are fabricated by MEMS technology using a silicon substrate. The functions of image elimination, parasitic filtering, channel selection and the like are realized in the wireless transceiver, the characteristics of high Q value, easiness in miniaturization and the like are realized, and the wireless transceiver is widely applied to the field of wireless communication. In order to ensure the reliability of the FBAR device, it needs to have good heat dissipation performance, and the package structure of the conventional FBAR device has poor heat dissipation performance. Due to the limitation of processes, equipment and the like, the bonding precision of the packaged wafer and the device wafer is poor, so that the chip needs larger redundant size to ensure the yield.

Disclosure of Invention

In view of the above, the present application provides a thin film bulk acoustic filter and a wafer level packaging method thereof, and the scheme is as follows:

a thin film bulk acoustic wave filter, the filter comprising:

the chip comprises a chip substrate, a first electrode and a second electrode, wherein an air cavity is formed on the upper surface of the chip substrate;

a resonator device covering the air cavity;

the redistribution interconnection structure is arranged on the lower surface of the chip substrate and is used for electrically connecting the layout lead and the ball-planting pad;

the through hole interconnection structure penetrates through the upper surface and the lower surface of the chip substrate, is used for electrically connecting the resonance device and the redistribution interconnection structure, and is used for conducting heat of the resonance device to the redistribution interconnection structure so as to be dissipated to the outside of the filter;

and the cover plate is fixed opposite to the upper surface of the chip substrate, covers the resonance device and has a gap with the resonance device.

Preferably, in the above filter, the resonator device includes a resonator film located above the air cavity, the upper surface of the resonator film has a top electrode, the lower surface of the resonator film has a bottom electrode, the top electrode and the bottom electrode are electrically connected to a bonding pad located on the upper surface of the chip substrate through an electrode lead, and the bonding pad completely covers the through hole interconnection structure.

Preferably, in the above filter, the cover plate is fixed to the upper surface of the chip substrate by bonding with a bonding pad;

the bonding block comprises a first metal block arranged on the upper surface of the chip substrate and a second metal block arranged on the surface of the cover plate, and the first metal block and the second metal block are welded to form the bonding block.

Preferably, in the above filter, the cover plate is fixed to the surface of the chip substrate by bonding with a bonding pad;

wherein the bonding block is a resin bonding material; the cover plate also has a groove on a side surface facing the resonator device.

Preferably, in the above filter, the cover plate is fixed to the surface of the chip substrate by a bonding block;

the bonding blocks have a spacing of 5-20 μm from the side edges of the filter.

Preferably, in the above filter, the via interconnection structure includes a via and a metal filling material located in the via, and the lower surface of the chip substrate is thinned to expose the via and the metal filling material located in the via;

and forming the redistribution interconnection structure electrically contacted with the through hole interconnection structure on the lower surface of the chip substrate after thinning treatment.

Preferably, in the above filter, a surface of the cover plate facing the chip substrate further includes an electromagnetic shielding layer.

Preferably, in the above filter, the electromagnetic shielding layer includes: the cover plate comprises a titanium layer covering the surface of the cover plate and a copper layer, a silver layer, a nickel layer or a nickel-iron layer covering the titanium layer.

The invention also provides a wafer level packaging method of the film bulk acoustic wave filter, which comprises the following steps:

providing a device wafer; the device wafer comprises a plurality of chip areas, and cutting channels are arranged among the chip areas;

forming an air cavity on the upper surface of the chip area, and covering the resonant device of the air cavity;

fixing a packaging wafer on the upper surface of the device wafer, wherein the packaging wafer covers all the chip areas and has a gap with the resonant device;

dividing the device wafer and the packaging wafer based on the cutting channels to form a plurality of single film bulk acoustic resonators;

the lower surface of the chip area is provided with a redistribution interconnection structure for electrically connecting a layout lead and a ball-mounting pad; the chip region is provided with a through hole interconnection structure which is used for electrically connecting the resonance device with the rearrangement interconnection structure and conducting heat of the resonance device to the rearrangement interconnection structure so as to be dissipated to the outside of the filter.

Preferably, in the wafer-level packaging method, the resonator device includes a resonator film located above the air cavity, the upper surface of the resonator film has a top electrode, the lower surface of the resonator film has a bottom electrode, the top electrode and the bottom electrode are electrically connected to a bonding pad located on the upper surface of the chip region through an electrode lead, and the bonding pad completely covers the through hole interconnection structure.

Preferably, in the wafer level packaging method, the method for fixing the packaged wafer includes:

forming a first metal block on the upper surface of the device wafer, and forming a second metal block on the surface of the packaging wafer;

and welding the first metal block and the second metal block to form a bonding block so as to bond and fix the packaging wafer and the device wafer.

and bonding and fixing the device wafer and the packaging wafer through a resin block, wherein the surface of one side of the packaging wafer, which faces the resonance device, is also provided with a groove.

Preferably, in the wafer level packaging method, the packaged wafer is fixed on the upper surface of the chip region by a bonding block;

Preferably, in the wafer level packaging method, the method for manufacturing the through hole interconnection structure includes:

before the packaging wafer is fixed, blind holes are manufactured on the upper surface of the chip area, the depth of each blind hole is smaller than the thickness of the device wafer and larger than the thinned thickness of the device wafer, and the thickness range is between 40 and 200 microns;

forming the metal filling material in the blind hole;

and after the packaging wafer is fixed, thinning the lower surface of the device wafer to expose the blind holes and the metal filling material.

Preferably, in the wafer level packaging method, before fixing the packaged wafer, the method further includes:

and forming an electromagnetic shielding layer on the surface of one side, facing the device wafer, of the packaging wafer.

Preferably, in the wafer level packaging method, the method for manufacturing the electromagnetic shielding layer includes:

and forming a titanium layer and a copper layer, a silver layer, a nickel layer or a nickel-iron layer covering the titanium layer on the surface of the packaging wafer.

According to the thin film bulk acoustic wave filter and the wafer level packaging method thereof, the cover plate is bonded and fixed on the upper surface of the chip substrate to package and protect the resonator, the air cavity is arranged below the resonator, and the gap is reserved between the cover plate and the resonator to ensure the normal work of the resonator.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

The structure, proportion, size and the like shown in the drawings are only used for matching with the content disclosed in the specification, so that the person skilled in the art can understand and read the description, and the description is not used for limiting the limit condition of the implementation of the invention, so the method has no technical essence, and any structural modification, proportion relation change or size adjustment still falls within the scope of the technical content disclosed by the invention without affecting the effect and the achievable purpose of the invention.

FIG. 1 is a schematic view of a structure of an SMR-BAW (solid State Assembly type bulk Acoustic wave resonator) in the related art;

FIG. 2 is a schematic structural diagram of an FBAR in the related art;

fig. 3 is a schematic diagram of a filter package structure in the related art;

FIG. 4 is a diagram illustrating another filter package structure in the related art;

FIG. 5 is a diagram illustrating another filter package structure in the related art;

FIG. 6 is a diagram illustrating another filter package structure in the related art;

FIG. 7 is a diagram illustrating another filter package structure in the related art;

FIG. 8 is a diagram illustrating another filter package structure in the related art;

fig. 9 is a schematic structural diagram of a thin film bulk acoustic wave filter according to an embodiment of the present invention;

fig. 10 is a schematic structural diagram of another film bulk acoustic wave filter according to an embodiment of the present invention;

fig. 11 is a schematic structural diagram of another thin film bulk acoustic wave filter according to an embodiment of the present invention;

fig. 12-24 are process flow diagrams of a wafer level packaging method according to an embodiment of the invention.

Detailed Description

The embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 1, fig. 1 is a schematic structural view of an SMR-BAW (solid-state bulk acoustic wave resonator) in the related art, which includes a Si substrate 01, and an acoustic reflector 02 and a piezoelectric film 03 sequentially disposed on the Si substrate 01, wherein an upper surface and a lower surface of the piezoelectric film 03 are respectively provided with an electrode layer 04. The device structure shown in fig. 1 has good heat dissipation performance, heat generated by the operation of the piezoelectric film 03 can be directly conducted to the Si substrate 01 from top to bottom through heat conduction, the heat is dissipated to the external gas environment through the lower surface of the Si substrate 01, the temperature difference between the operating state and the non-operating state is generally 20 ℃, but the operating frequency is low.

Referring to fig. 2, fig. 2 is a schematic structural diagram of an FBAR in the related art, which includes a Si substrate 11, an air cavity 12 is formed on an upper surface of the Si substrate 11, a piezoelectric film 13 covers a surface of the air cavity 12, and a layer of electrode layer 14 is respectively disposed on an upper surface and a lower surface of the piezoelectric film 13. Compared with the mode shown in fig. 1, the resonance device with the structure shown in fig. 2 can reach a higher working frequency range, but because most of the area below the piezoelectric film 13 is the air cavity 12, and the heat conduction effect of the gas in the air cavity 12 is poor, when the resonance device works, heat is mainly conducted to the Si substrate 11 through the piezoelectric film 13 and the edges of the upper electrode layer 14 and the lower electrode layer 14, the heat dissipation rate is poor, the temperature difference between the working state and the non-working state is generally 70 ℃, and due to poor heat dissipation, the performance attenuation of the resonance device is fast, the long-term use reliability is poor, and the actual effective working life is reduced.

At present, FBAR technology has been developed more and more mature, and is widely applied in the field of wireless communication technology. As shown in fig. 2, due to the characteristics of the thin film structure, the requirement for the device package structure is high, and it is necessary to ensure that the device in the package structure is in the cavity, which results in a complicated packaging process, low reliability, and inconvenience for the miniaturized design of the package size. Therefore, a novel film bulk acoustic wave filter and a wafer level packaging method thereof are provided to simplify the packaging process, reduce the packaging complexity, reduce the packaging size, improve the heat dissipation performance and improve the heat dissipation efficiency to the greatest extent, which is a problem to be solved urgently in the FBAR technical field. The film bulk acoustic wave filter comprises at least one film bulk acoustic resonator.

As shown in fig. 3, fig. 3 is a schematic diagram of a filter package structure in the related art, in which a resonant device is fabricated on a device wafer 21, and a package upper cover 22 is fixed on the surface of the device wafer 21 through a polymer frame 23. A CuNi metal interconnection layer 24 is formed on the upper surface of the package upper cover plate 22, and the CuNi metal interconnection layer 24 extends to the upper surface of the device wafer 21 and is connected with an electrode lead of the resonator device. A ball-planting base (UBM)25 is formed on the surface of the CuNi metal interconnection layer 24 on the package upper cover plate 22, and a solder micro-bump 26 is formed on the ball-planting base 25, wherein the solder micro-bump 26 is eutectic SnAgCu solder.

In the manner shown in fig. 3, although the wafer is insensitive to the injection pressure and can bear a larger injection pressure, the layout of the electrical connection routing of the two wafers is complicated, and the packaging difficulty and the process controllability are increased; the upper packaging cover plate 22 needs to be subjected to photoetching and etching processes before bonding, and the upper packaging cover plate 22 is thin in thickness and difficult in process; meanwhile, for circuit interconnection, the size of the package upper cover plate 22 is small, and the solder micro-bumps 26 are manufactured above the package upper cover plate 22 to form a step-type structure, so that the product thickness is large; in addition, two identical single crystal wafers are required to ensure the Radio Frequency (RF) performance after the electrical interconnection traces are arranged, so the package upper cover plate 22 needs to be a single crystal wafer, resulting in higher cost, because the top package upper cover plate 22 generally only plays a role in package protection, and the additional RF performance is required, which greatly increases the cost. The product structure can not effectively solve the problem of heat dissipation of the resonance device area.

As shown in fig. 4, fig. 4 is a schematic view of another filter package structure in the related art, the mode shown in fig. 4 is a saw filter wafer bonding package structure, a master wafer 31 and a wafer 32 are bonded and fixed by a metal 36 and electrically interconnected by TSVs (deep through silicon vias) 33, and a solder micro bump 37 is provided on an upper surface of the wafer 32. Both wafers have saw filter structures, the master wafer 31 has saw filter cells 34, and the wafer 32 has saw filter cells 35, both packaged.

In the mode shown in fig. 4, the injection mold is insensitive to injection pressure and can bear larger injection pressure. However, the through hole penetrating through the wafer 32 needs to be directly formed on the wafer 32 by the TSV technology, and the wafer 32 as the cover plate is thin, which has great process difficulty and high cost, and the wafer 32 is thin in thickness during processing, easy to crack, and poor in reliability. This approach also requires two identical monocrystalline wafers to ensure Radio Frequency (RF) performance after the electrical interconnect traces are laid out, resulting in higher cost.

As shown in fig. 5, fig. 5 is a schematic diagram of another filter package structure in the related art, in the method shown in fig. 5, for bonding and packaging a bulk acoustic wave filter wafer, after a main wafer 41 is manufactured, it is bonded to a sub-wafer 42, and the two wafers are electrically connected by forming TSVs directly on the back surface of the sub-wafer 42, which penetrate through the sub-wafer 42, so as to complete the package. The TSVs form an interconnect structure on the top surface of the wafer 42 through the redistribution layer 43.

In the mode shown in fig. 5, the injection mold is insensitive to injection pressure and can bear larger injection pressure. However, the through holes penetrating through the sub-wafer 42 need to be directly formed on the sub-wafer 42 by the TSV technology, and the sub-wafer 42 serving as the cover plate is thin, difficult to control etching and processes, and high in cost. And two identical high impedance single crystal wafers are required to ensure Radio Frequency (RF) performance after electrical interconnect traces are laid out, resulting in higher cost. Although the peripheral area of the resonant film can conduct heat to the lower surface of the main wafer 41 during operation, and has a certain heat dissipation effect, the heat dissipation effect is poor.

As shown in fig. 6, fig. 6 is a schematic view of a filter package structure in another related art, in the manner shown in fig. 6, a device wafer 51 and a package wafer 52 are fixed by metal bonding or adhesive bonding through an adhesive layer, after dicing, the device wafer 51 is divided into a plurality of single filter chips, and the package wafer 52 is divided into a plurality of cover plates. And each filter chip is correspondingly bonded with a cover plate to form a packaging structure. One package structure is shown in fig. 6. The package wafer 52 has a groove, and is fixed to the FBAR structure 53 on the surface of the device wafer 51 through the sealing frame, the surface of the device wafer 51 has an electrode 54 led out of the sealing frame, and the surface of the electrode 54 has a bonding PAD. The bonding PAD PAD can be connected with an external circuit through routing or manufacturing a solder micro-bump.

In the manner shown in fig. 6, the package wafer 52 requires a recess formed by photolithography and etching processes, which adds processing steps. And a certain distance needs to be reserved between the package wafer 52 and the bonding PAD, which results in a large size after packaging and is inconvenient for product miniaturization design. In addition, the FBAR structure 53 cannot be effectively cooled due to poor heat dissipation.

As shown in fig. 7, fig. 7 is a schematic diagram of another filter package structure in the related art, where the manner shown in fig. 7 is similar to the manner shown in fig. 5, the lower surface of the package wafer 62 has a groove and a first eutectic bonding metal layer, and has TSVs penetrating through the upper and lower surfaces thereof, and the TSVs have metal fillings 64 therein, and an end of the TSV facing away from the device wafer 61 is connected with the ball-mounting base UBM through an interconnection layer. The upper surface of the device wafer 61 is provided with a second eutectic bonding metal layer, and the second eutectic bonding metal layer and the first eutectic bonding metal layer are bonded and fixed to form bonding blocks 63 around each packaging structure. The device wafer 61 also has an FBAR structure 65 on its upper surface and an electrode 66 connected to it, the electrode 66 being in electrical contact with the bond pads 63. After the two wafers are bonded and fixed, the upper surface of the packaging wafer 62 is thinned, and the metal filling 64 is exposed so as to be convenient for connecting the interconnection layer and the ball-mounting base UBM and leading out the electrode 66.

In the method shown in fig. 7, the heat generated by the FBAR structure 65 during operation cannot be conducted to the lower surface of the device wafer 61 well, and the heat cannot be conducted effectively. Similarly, before bonding and fixing, the package wafer 62 needs to be subjected to photolithography and etching, and the package wafer 62 has a small thickness, a large process difficulty, and low bonding alignment accuracy. Moreover, the thickness of the package wafer 62 is thin, which makes the TSV process difficult.

As shown in fig. 8, fig. 8 is a schematic diagram of a filter package structure of another related art, in the mode shown in fig. 8, an interdigital transducer IDT of a filter structure on the lower surface of a device wafer 71 is sealed and protected by a thin film protection layer 72, and a cavity is formed between the thin film protection layer 72 and the filter structure. And then, a through hole penetrating through the thin film protection layer 72 is directly formed through the TSV technology and is electrically connected with a bonding pad on the lower surface of the device wafer 71, and a solder ball 73 is formed on the lower surface of the thin film protection layer 72 at a position corresponding to the through hole, so that packaging is completed.

In the embodiment shown in fig. 8, the thin film protective layer 72 is generally formed by a resin material, and when integrated into a circuit module, the thin film protective layer is sensitive to an injection pressure, cannot withstand a large injection pressure, and has a reliability risk, so that a package with high reliability cannot be provided due to the characteristics of the resin material. And poor heat dissipation, further resulting in poor reliability.

As can be seen from the above description, there are some problems in the package structures of the related art. In order to solve the problems, the embodiment of the invention provides a film bulk acoustic wave filter and a wafer level packaging method thereof, if metal bonding packaging is used, the heat dissipation efficiency of a product can be greatly improved, the working performance and long-term reliability of the product can be ensured, and simultaneously, high-reliability wafer level packaging is realized; if the resin bonding package is used, the heat dissipation efficiency can be greatly improved.

The technical scheme of the invention can be generally applied to wafer-level packaging of FBAR, particularly to the use in the fields of high frequency and wide frequency band such as 5G and the like, and can greatly improve the heat dissipation performance under the condition of high heat dissipation requirement, so that the product can be applied to wider terminal equipment, such as the technical fields of industry, automobiles and the like.

The invention is also applicable to devices with similar cavity structures and cavity requirements, including but not limited to BAW, SAW and other devices used for acoustic wave filters, infrared sensing devices, ultrasonic sensors and other MEMS devices.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a thin film bulk acoustic wave filter according to an embodiment of the present invention, where the thin film bulk acoustic wave filter includes a chip substrate 81, an air cavity 811 is formed on an upper surface of the chip substrate 81, a resonant device covers the air cavity 811, a redistribution interconnect (RD L) 812 disposed on a lower surface of the chip substrate 81 and used for electrically connecting a layout lead and a ball pad, a via interconnect 100 penetrating the chip substrate 81, where the via interconnect 100 is used for electrically connecting the resonant device and the redistribution interconnect 812 and conducting heat of the resonant film 815 to the redistribution interconnect 812 to be dissipated to the outside of the filter, and a cover plate 82 fixed to the upper surface of the chip substrate 81, where the cover plate 82 covers the resonant device and has a gap 84 with the resonant device, and the cut gap is a distance between a bonding region and a cut channel to prevent cracking or damage of a bonding site caused by edge or diffraction during cutting and further cause a problem of package failure.

Wherein the resonance device includes: and the resonant film 815 is positioned on the air cavity 811, the upper surface of the resonant film 815 is provided with a top electrode, the lower surface of the resonant film 815 is provided with a bottom electrode, the top electrode and the bottom electrode are electrically connected with a bonding pad positioned on the upper surface of the chip substrate through electrode leads, and the bonding pad completely covers the through hole interconnection structure 100. The bottom electrodes, electrode leads, and piezoelectric pads may be fabricated simultaneously from a metal layer 816 on the upper surface of the chip substrate 81.

When the resonator in the filter operates, the generated heat can be conducted to the redistribution interconnection structure 812 on the lower surface of the chip substrate 81 through the through hole interconnection structure 100, and then dissipated to the external environment on the lower surface of the chip substrate 81, so that the speed of conducting the upper surface of the chip substrate 81 to the lower surface of the chip substrate is increased, and the heat dissipation rate is increased.

The piezoelectric bonding pad is disposed to completely cover the through-hole interconnection structure 100, so that the metal layer 816 has the largest thermal contact area with the through-hole interconnection structure 100, and the heat dissipation efficiency is improved. Both the top and bottom electrodes are connected to corresponding piezoelectric pads through electrode leads on the upper surface of the chip substrate 81 to lead to the redistribution interconnect 812 on the lower surface of the chip substrate 81.

In the manner shown in fig. 9, the cover plate 82 is bonded and fixed to the upper surface of the chip substrate 81 by a bonding block 83; the bonding block 83 includes a first metal block disposed on the upper surface of the chip substrate 81 and a second metal block disposed on the surface of the cover plate 82, and the first metal block and the second metal block are bonded to form the bonding block 83.

As shown in fig. 9, the cover plate 82 is fixed on the surface of the chip substrate 81 by a bonding block 83; the bond blocks 83 have a 5-20 μm spacing 84 from the side edges of the filter. By arranging the space 84, the problem of chip breakage or wafer breakage caused by cutting when a wafer is cut to form a single filter chip can be avoided.

Through-hole interconnect structure 100 includes through-hole 813 and is located metal filling material 814 in through-hole 813, through-hole 813 is less than for the degree of depth chip substrate 81 place device wafer thickness, is forming during the wave filter, chip substrate 81's lower surface passes through the attenuate processing to expose through-hole 813 and be located in the through-hole 813 metal filling material 814. The redistribution interconnection structure 812 electrically contacting with the through-hole interconnection structure 100 is formed on the lower surface of the chip substrate 81 after thinning processing.

As shown in fig. 10, fig. 10 is a schematic structural diagram of another thin film bulk acoustic wave filter according to an embodiment of the present invention, and in the manner shown in fig. 10, on the basis of the manner shown in fig. 9, an electromagnetic shielding layer is further disposed on a surface of the cover plate 82 facing the chip substrate 81. Optionally, the electromagnetic shielding layer includes a titanium layer 821 covering the surface of the cover plate 82 and a conductor layer 822 covering the titanium layer 821, and the conductor layer 822 may be a copper layer, a silver layer, a nickel layer, or a nickel-iron layer.

In the embodiment of the present invention, the chip substrate 81 is made of a device wafer, the cover plate 82 is made of a package wafer, the surfaces of the two wafers form a set structure, and after bonding and fixing, a single package protected filter chip is formed after cutting. Before the two wafers are bonded and fixed, a through hole 813 is formed on the device wafer through a TSV technology. The electrodes on the chip substrate 81 may be led out to the lower surface thereof through the TSV process. If the two wafers are fixed through metal bonding, the two wafers can be directly bonded and fixed on the device wafer after the metal deposition of a single layer or a composite layer is carried out on the surface of the packaging wafer, and the packaging wafer does not need photoetching or etching.

The method for fixing the packaging wafer comprises the following steps: and fixing the device wafer and the packaging wafer through resin block bonding, wherein the side surface of the cover plate 82 facing the resonant film 815 is also provided with a groove. As shown in fig. 11, fig. 11 is a schematic structural diagram of another thin film bulk acoustic wave filter according to an embodiment of the present invention, and the manner shown in fig. 11 is different from that shown in fig. 9 in that a bonding block 83 is a resin block bonding material or other organic bonding material, and a side surface of the cover plate 82 facing the resonator device further has a groove 85. Because the bonding fixing thickness of the resin material is relatively thin, the distance between the lower surface of the cover plate 82 and the resonance device cannot meet the working requirement of the resonance device, and therefore the groove 85 needs to be arranged in the region of the lower surface of the cover plate 82 opposite to the resonance thin device.

Since the resin is an insulating material, the bonding block 83 can be formed on the bonding wire, and can be overlapped with the through hole interconnection structure 100, so that the product size can be reduced, and the circuit and the package wafer are not electrically connected, and the radio frequency characteristic is not affected. This approach also requires that the bonding block 83 be spaced from the edge of the product by 5 μm to 20 μm to prevent chipping or wafer breakage problems caused by dicing.

Based on the above filter, another embodiment of the present invention further provides a wafer level packaging method for a thin film bulk acoustic filter, where the wafer level packaging method is shown in fig. 12 to 24, and fig. 12 to 24 are process flow diagrams of a wafer level packaging method provided in an embodiment of the present invention, and the method includes:

step S11: as shown in fig. 12, a device wafer 801 is provided.

The device wafer 801 includes a plurality of chip regions with dicing channels therebetween. After the subsequent division process is completed, the chip region serves as a chip substrate 81 of a single film bulk acoustic wave filter. Only one chip substrate 81 is shown in fig. 12, and the dicing channels are not shown.

Step S12: as shown in fig. 13 to 16, an air cavity 811 and a resonator device covering the air cavity are formed on the upper surface of the chip substrate 81. On the chip substrate 81, there are a blind via 813 ', a metal layer 814', an air cavity 811 and a resonator device in sequence, as mentioned above, the resonator device includes a resonator film 815 covering the air cavity 811 and its electrodes, electrode leads and bonding pads, and in some packaging bonding methods, a bonding block or a bonding frame is also fabricated.

Wherein, the lower surface of the chip substrate 81 has a redistribution interconnect structure 812 (formed after the package wafer 802 is bonded subsequently) for electrically connecting the layout leads and the ball-mounted pads; the chip substrate 81 has a through-hole interconnection structure 100 for electrically connecting the resonator device and the redistribution interconnection structure 812, and for conducting heat of the resonator device to the redistribution interconnection structure 812 to be dissipated to the outside of the filter.

In step S12, the method for manufacturing the via interconnection structure 100 includes: before manufacturing a resonant device, forming a blind hole 813 'on the upper surface of the chip substrate 81, wherein the depth of the blind hole 813' is smaller than the thickness of the device wafer 801 and larger than the thinned thickness of the device wafer 801; forming the metal filling material 814 in the blind hole 813'; after the package wafer 802 is fixed, the lower surface of the device wafer 801 is thinned to expose the blind holes 813 'and the metal filling material 814, and the through holes 813 are formed based on the blind holes 813'. Therefore, the TSV punching depth can be reduced, the device wafer 801 and the packaging wafer 802 can be further thinned based on the structure with larger thickness after the two wafers are bonded and fixed, and the thickness of the filter is greatly reduced.

Specifically, in step S12, the device wafer 801 is cleaned, and then the upper surface thereof is subjected to glue coating, exposure, and development to form the patterned photoresist mask layer 91, where the photoresist mask layer 91 has an opening.

Then, as shown in fig. 13, through TSV etching, blind holes 813 'are formed in the device wafer 801 at positions corresponding to the openings defined by the photoresist mask layer 91, and the depth of the blind holes 813' is smaller than the thickness of the device wafer 801. The depth of the blind hole 813' depends on the thickness of the lower surface of the device wafer 801 to be thinned later, and is usually greater than the thickness of the thinned chip substrate 801, and the process can remove part of the lower end of the metal filling material 814, ensure that the metal filling material 814 is fully exposed, and ensure that the lower ends of the metal filling materials 814 are flush (the coplanarity meets the requirement).

As shown in fig. 14, the photoresist mask layer 91 is removed, an isolation oxide layer is formed to cover the top surface of the device wafer 801 and the sidewalls and bottom of the blind via 813 ', a barrier layer and a seed layer are formed to cover the isolation oxide layer, and a plating metal layer (such as copper) 814' is formed on the surface of the seed layer, and the blind via 813 'is filled with the metal layer 814' as a metal filling material 814. The barrier layer serves to block diffusion of its surface metal atoms into the device wafer 801 and also serves to improve adhesion of the surface metal layer 814'. The seed layer is used for filling the conductive layer and the initial layer during metal plating, and the seed layer and the plated metal layer are laminated into a whole after the plating. The seed layer is the same material as the electroplated metal layer 814', and may be copper, for example.

As shown in fig. 15, the metal layer 814 ' (including the seed layer), the barrier layer and the isolation oxide layer on the upper surface of the device wafer 801 are removed, and the metal layer 814 ' in the blind via hole 813 ' is remained, thereby forming the metal filling material 814. In this process, the three-layer structure may be simultaneously removed by a grinding process (CMP). The metal layer 814', the seed barrier layer and the isolation oxide layer may be removed sequentially by three times of etching, and the etching may be dry etching, wet etching or a combination thereof.

Finally, as shown in fig. 16, a resonant device structure is fabricated, an air cavity 811 is formed on the upper surface of the chip substrate 81, and a resonant device is fabricated on the air cavity 811, including a resonant film 815 and top and bottom electrodes on the upper and lower surfaces thereof, an electrode lead-out line, and a piezoelectric pad. The bottom electrodes, the electrode leads, and the piezoelectric pads may be formed by a metal layer 816 on the upper surface of the chip substrate 81. The method is described by taking an example of metal bonding between two wafers, and a first metal block 817 is formed on a predetermined bonding region on the upper surface of the chip substrate 81, for example, the first metal block 817 may be disposed on a copper layer at the bonding region and a tin layer disposed on the surface of the copper layer. The piezoelectric pads completely cover the through-hole interconnection structure 100 to improve heat dissipation efficiency.

Step S13: as shown in fig. 17-21, a package wafer 802 is fixed on the upper surface of the device wafer 801, and the package wafer 802 covers all the chip substrates 81 and has a gap with the resonant devices.

The method is described by taking an example of metal bonding fixing of two wafers, and the method for fixing the package wafer 802 includes: forming the first metal block 817 on the upper surface of the device wafer 801, and forming the second metal block 92 on the surface of the package wafer 802, where the second metal block 92 includes a copper layer 921 on the surface of the package wafer 802 and a tin layer 922 covering the copper layer 921; the first metal block 817 and the second metal block 92 are welded to form a bonding block 83, so as to bond and fix the package wafer 802 and the device wafer 801.

Specifically, in step S13, as shown in fig. 17, a pattern of bonding regions is first formed on the surface of the package wafer 802 corresponding to each chip substrate 81, a patterned copper layer 921 of 5 μm to 20 μm is formed by electroplating, and a tin layer 922 of 1 μm to 5 μm is electroplated on the copper layer 921, thereby forming the second metal block 92. In another way, before the second metal blocks 92 are formed, a titanium layer 821 may be formed on the surface of the package wafer 802 to increase the adhesion stability of the copper layer 921.

Then, as shown in fig. 18, the metal blocks in the two wafers are bonded, eutectic bonding and fixing are performed under certain temperature and pressure conditions, and a sealing frame (i.e., a bonding block 83) is formed at the periphery of the chip substrate 81 and the corresponding cover plate 82. After bonding and fixing, the lower surface of the device wafer 801 is thinned to expose the metal filling material 814. After the two wafers are bonded and fixed, the distance between the edge of the sealing frame and the preset cutting edge is 5-20 μm, namely, the distance between the bonding block 83 and the edge of the filter chip is 5-20 μm, so that the single chip or the wafer is prevented from being cracked when the wafer is cut based on the cutting channel.

Finally, as shown in fig. 19, after thinning the device wafer 801, the device wafer is turned upside down to make its lower surface face upward, and bonding pads are formed on the lower surface of the device wafer 801 for wire bonding or for forming a redistribution layer RD L and a ball-mounting base UBM for ball-mounting or solder micro-bump formation to form a redistribution interconnect structure 812, and finally, the package wafer 802 is thinned again.

In another embodiment, before fixing the package wafer 802, the method further includes: an electromagnetic shielding layer is formed on the surface of the package wafer 802 facing the device wafer 801. The manufacturing method of the electromagnetic shielding layer comprises the following steps: a titanium layer 821 and a conductor layer 822 are sequentially formed on the surface of the package wafer 802, and the conductor layer 822 may be a copper layer, a silver layer, a nickel layer, or a nickel-iron layer. As shown in fig. 20 and 21, first, as shown in fig. 20, before the second metal block 92 is formed, the conductor layer 822 is formed, and in order to improve the adhesion stability of the conductor layer 822, the titanium layer 821 is formed on the surface of the package wafer 802 before the conductor layer 822 is formed, and the conductor layer 822 is formed on the surface of the titanium layer 821. A second metal block 92 comprising a 5-20 μm layer of copper 921 and a 1-5 μm layer of tin 922 is then formed on the surface of the conductor layer 822 based on the bonding region pattern. The tin layer 922 in the second metal block 92 is optional. Then, as shown in fig. 21, the device wafer 801 and the package wafer 802 are bonded and fixed, the chip substrates 81 in the device wafer 801 and the cover plates 82 in the package wafer 802 are bonded and fixed in a one-to-one correspondence manner, after the bonding and fixing, the device wafer 801 is inverted through the thinning process in the same manner as in the above process, so that the lower surface of the device wafer is upward to form a redistribution interconnection structure 812, and finally, the package wafer 802 is thinned. This way, a high-efficiency heat-dissipating filter package structure with an electromagnetic shielding function as shown in fig. 10 can be manufactured.

Step S14: and dividing the device wafer 801 and the packaging wafer 802 based on the cutting channels to form a plurality of single devices such as the film bulk acoustic filter and the like, including at least one resonant device.

The individual thin-film bulk acoustic wave filter comprises a chip substrate 81 and a cover plate 82 which is fixed in a correspondingly bonded manner. The device wafer 801 is singulated to form a plurality of individual chip substrates 81. The package wafer 802 is singulated to form a plurality of individual cover plates 82. The chip substrates 81 and the cover plates 82 are bonded and fixed in a one-to-one correspondence.

In the filter package structure according to the embodiment of the present invention, the redistribution interconnect structure 812 is fabricated on the lower surface of the chip substrate 81, and is connected to the piezoelectric bonding pad through the through hole interconnect structure 100 to implement circuit interconnection, and finally, the electrode is led out to the lower surface of the chip substrate 81. While the redistribution interconnection structure 812 is directly formed on the surface of the chip substrate 81, the good thermal conductivity of the metal conductor can be utilized to improve the heat dissipation efficiency.

In the above embodiments, the package wafer 802 does not need to be processed by photolithography and etching, which is illustrated by metal bonding, and thus the cost is low. Before the two wafers are bonded and fixed, a TSV process is performed on the surface of the device wafer 801 to form a through hole 813, the problem caused by poor bonding and fixing alignment accuracy can be solved, an electrode is led out of the device wafer 801, and the bonding alignment is replaced by photoetching alignment (a resonant device electrode lead and a pressure welding PAD PAD are aligned to cover the TSV). Because the photoetching alignment precision is far higher than the bonding alignment, and the precision after the alignment cannot be further reduced in the subsequent process (such as position offset in the bonding process), the radio frequency performance and the reliability of the device can be improved, the process difficulty is greatly reduced, and the packaging size of the filter chip is reduced.

In the embodiment of the invention, the TSV process is performed before bonding and fixing, and the through hole interconnection structure 100 is formed in the set region of the device wafer 801 to realize direct heat conduction, so that the heat dissipation effect is better compared with the related technology. The thermal conduction path is formed at the same time as the via interconnect structure 100 is processed. In the final formed filter package structure, the solder bumps in one or more of the redistribution interconnect structures 812 are not connected to electrodes, i.e., are not connected to electrical signal paths, and are only used for supporting and dissipating heat, such as the solder bump 93 in the middle of fig. 22, and the other end of the corresponding through-hole interconnect structure 100 to which the solder bump 93 is connected is not connected to the electrode leads and the bonding pads. Moreover, the through hole interconnection structure 100 corresponding to the solder bump 93 can directly contact with the bonding block 83, and since the through hole interconnection structure 100 corresponding to the solder bump 93 is not connected with an electrical signal channel, and the through hole interconnection structure 100 corresponding to the solder bump 93 is arranged to contact with the bonding block 83, the influence of the device wafer 801 on the radio frequency characteristics is not caused. If metal bonding is employed, the through-hole interconnection structures 100 electrically connected to the metal layer 816 and the metal bonding blocks 83 are disposed in a staggered manner, and they do not contact each other, and if resin bonding is employed, all the through-hole interconnection structures 100 can contact the bonding blocks 83.

Since the redistribution interconnection structure is not required to be fabricated on the package wafer 802, the package wafer 802 is not in electrical contact with the rf device, and therefore a high-impedance single crystal wafer is not required, which greatly reduces the cost. And moreover, a resin material is adopted for bonding and packaging in the subsequent process, a high-impedance monocrystalline wafer is not required, and the cost can be greatly reduced.

When the high-heat-dissipation-efficiency filter is manufactured, the electromagnetic shielding layer can be manufactured on the packaging wafer 802, so that the filter with the electromagnetic shielding structure and function is obtained, and the filter can be used in 5G equipment, so that signal noise is greatly reduced, and the signal transmission effect is improved.

As described above, when the redistribution layer 812 is formed on the lower surface of the device wafer 801, the ball mount UBM may be adjusted in position by the redistribution layer, as shown in fig. 23, after bonding and fixing the two wafers, the device wafer 801 is turned upside down so that the lower surface faces upward, and the redistribution layer (RD L) 94 and the ball mount UBM are formed on the lower surface thereof, or as shown in fig. 24, the copper bump 95 is formed on the lower surface thereof as a solder micro bump.

The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other.

It should be noted that in the description of the present invention, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A thin film bulk acoustic wave filter, the filter comprising:

a resonator device covering the air cavity;

a through-hole interconnection structure penetrating through the chip substrate, the through-hole interconnection structure being used for electrically connecting the resonance device and the redistribution interconnection structure and conducting heat of the resonance device to the redistribution interconnection structure so as to be dissipated to the outside of the filter;

and the cover plate is fixed opposite to the upper surface of the chip substrate, covers the resonance device and has a gap with the device.

2. The filter of claim 1, wherein the resonator device comprises a resonator film over the air cavity, the resonator film having a top electrode on an upper surface thereof and a bottom electrode on a lower surface thereof, the top and bottom electrodes being electrically connected by electrode leads to bond pads on an upper surface of the chip substrate, the bond pads completely covering the via interconnection.

3. The filter of claim 1, wherein the cover plate is fixed to the upper surface of the chip substrate by a bond pad bond;

the bonding block comprises a first metal block arranged on the upper surface of the chip substrate and a second metal block arranged on the surface of the cover plate, and the first metal block and the second metal block are bonded to form the bonding block.

4. The filter of claim 1, wherein the cover plate is fixed to the surface of the chip substrate by a bond pad bond;

5. The filter of claim 1, wherein the cover plate is fixed to the surface of the chip substrate by a bonding block;

6. The filter of claim 1, wherein the via interconnection structure comprises a via and a metal filling material located in the via, and the lower surface of the chip substrate is thinned to expose the via and the metal filling material located in the via;

7. The filter of claim 1, wherein the surface of the cover plate facing the chip substrate is further provided with an electromagnetic shielding layer.

8. The filter of claim 7, wherein the electromagnetic shielding layer comprises: the cover plate comprises a titanium layer covering the surface of the cover plate and a copper layer, a silver layer, a nickel layer or a nickel-iron layer covering the titanium layer.

9. A wafer level packaging method of a film bulk acoustic wave filter is characterized by comprising the following steps:

dividing the device wafer and the packaging wafer based on the cutting channels to form a plurality of single film bulk acoustic wave filters;

10. The wafer level packaging method of claim 9, wherein the resonant device comprises a resonant film located above the air cavity, the resonant film has a top electrode on an upper surface thereof and a bottom electrode on a lower surface thereof, the top electrode and the bottom electrode are electrically connected with a bonding pad located on an upper surface of the chip region through an electrode lead, and the bonding pad completely covers the through hole interconnection structure.

11. The wafer level packaging method of claim 9, wherein the method of securing the packaged wafer comprises:

12. The wafer level packaging method of claim 9, wherein the method of securing the packaged wafer comprises:

13. The wafer level packaging method as claimed in claim 9, wherein the packaging wafer is fixed on the upper surface of the chip region by a bonding block;

14. The wafer level packaging method of claim 9, wherein the method for manufacturing the through hole interconnection structure comprises:

before a resonant device is manufactured, a blind hole is manufactured on the upper surface of the chip area, and the depth of the blind hole is smaller than the thickness of the device wafer and larger than the thinned thickness of the device wafer;

forming a metal filling material in the blind hole;

15. The wafer level packaging method of claim 9, further comprising, before securing the packaged wafer:

16. The wafer-level packaging method according to claim 15, wherein the electromagnetic shielding layer is manufactured by a method comprising: