CN216120296U - Fan-out type packaging structure and radio frequency module - Google Patents
Fan-out type packaging structure and radio frequency module Download PDFInfo
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- CN216120296U CN216120296U CN202122470876.0U CN202122470876U CN216120296U CN 216120296 U CN216120296 U CN 216120296U CN 202122470876 U CN202122470876 U CN 202122470876U CN 216120296 U CN216120296 U CN 216120296U
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Abstract
The embodiment of the utility model discloses a fan-out type packaging structure and a radio frequency module, wherein the fan-out type packaging structure comprises a first wafer, a second wafer and a rewiring layer, the rewiring layer comprises a first insulating layer arranged on the first surface of the first wafer and a second insulating layer arranged on the first surface of the second wafer, the first surface of the first wafer is bonded through the wafer and is combined with the second surface of the second wafer into a whole in a fan-out mode, and a sealed cavity is formed between the first wafer and the second wafer through the first insulating layer; the first wafer is electrically connected through a through hole penetrating through the first insulating layer, the second wafer and the second insulating layer. According to the technical scheme provided by the embodiment of the utility model, the first wafer and the second wafer are bonded together in a fan-out mode to form the fan-out type three-dimensional wafer, so that the size flexibility of the wafer is higher, the wafer bonding method can adapt to the bonding of the wafers with different sizes, the integration level of wafer packaging is greatly improved, and the utilization rate of the wafer is improved.
Description
Technical Field
The embodiment of the utility model relates to the technical field of semiconductors, in particular to a fan-out type packaging structure and a radio frequency module.
Background
With the rapid development of chip technology, people have higher and higher requirements on the integration level of chips and smaller requirements on the size of chips.
The rf module includes a filter, a Silicon On Insulator (SOI) chip (e.g., an antenna switch, a low noise amplifier, etc.). At present, the packaging aiming at the chip is mostly 2D wafer level packaging in the market, the radio frequency module corresponding to the packaging occupies a larger space, and the requirements of high integration level and miniaturization can not be met.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a fan-out type packaging structure and a radio frequency module, and aims to realize a small-size and high-integration packaging structure.
In a first aspect, an embodiment of the present invention provides a fan-out package structure, including: the wafer structure comprises a first wafer, a second wafer and a rewiring layer, wherein the first wafer and the second wafer respectively comprise a first surface and a second surface which are arranged oppositely;
the redistribution layer comprises a first insulating layer arranged on the first surface of the first wafer and a second insulating layer arranged on the first surface of the second wafer, the first surface of the first wafer is combined with the second surface of the second wafer into a whole in a fan-out mode, and a sealed cavity is formed between the first wafer and the second wafer through the first insulating layer;
the first wafer is electrically connected through a through hole penetrating through the first insulating layer, the second wafer and the second insulating layer.
Optionally, a first pad is disposed on the first wafer, a second pad is disposed on the second wafer, the first insulating layer includes at least one first through hole exposing the first pad, the second insulating layer includes at least one second through hole exposing the second pad and at least one third through hole exposing the second wafer, and the first through hole and the third through hole penetrate through the second wafer to form a fourth through hole;
and conductive materials are filled in the fourth through hole and the second through hole, and the first welding pad is electrically connected with the second welding pad through metal routing.
Optionally, the redistribution layer further includes a third insulating layer disposed on a side of the second insulating layer away from the second wafer, and the third insulating layer covers the metal trace.
Optionally, a metal bump is further included;
the metal bumps are arranged on one side, far away from the second insulating layer, of the third insulating layer and are connected with the metal wiring through the conductive posts.
Optionally, the first insulating layer covers the first pad, and the second insulating layer covers the second pad.
Optionally, the wafer structure further comprises a plastic package structure, and the plastic package structure is wrapped on the second surface and the side surface of the first wafer.
Optionally, the plastic package structure includes a top surface and a bottom surface that are arranged oppositely, the bottom surface of the plastic package structure contacts with the second surface of the first wafer, the top surface of the plastic package structure is flush with the surface of the first insulating layer away from one side of the first wafer, and contacts with the second surface of the second wafer.
Optionally, the first wafer comprises an acoustic surface filter wafer.
Optionally, the substrate material of the first wafer comprises lithium tantalate or lithium niobate, and the substrate material of the second wafer comprises silicon.
In a second aspect, an embodiment of the present invention further provides a radio frequency module, where the radio frequency module includes the fan-out package structure provided in any embodiment of the present invention.
The embodiment of the utility model provides a fan-out type packaging structure and a radio frequency module, wherein the fan-out type packaging structure comprises a first wafer, a second wafer and a rewiring layer, wherein the first wafer and the second wafer respectively comprise a first surface and a second surface which are oppositely arranged; the rewiring layer comprises a first insulating layer arranged on the first surface of the first wafer and a second insulating layer arranged on the first surface of the second wafer, the first surface of the first wafer is bonded through the wafer and is combined with the second surface of the second wafer into a whole in a fan-out mode, and a sealed cavity is formed between the first wafer and the second wafer through the first insulating layer; the first wafer is electrically connected through a through hole penetrating through the first insulating layer, the second wafer and the second insulating layer. Compared with the prior art, the technical scheme provided by the embodiment of the utility model bonds the first wafer and the second wafer together in a fan-out mode to form the fan-out type three-dimensional wafer, so that the size flexibility of the wafer is higher, the wafer bonding method can adapt to the bonding of the wafers with different sizes, the integration level of wafer packaging is greatly improved, the occupied area of the wafer packaging can be reduced, and the utilization rate of the wafer is improved.
Drawings
Fig. 1 is a schematic structural diagram of a fan-out package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another fan-out package structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another fan-out package structure according to an embodiment of the present invention;
FIG. 4 is a top view of another fan-out package structure according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another fan-out package structure according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another fan-out package structure according to an embodiment of the present invention;
fig. 7-17 are schematic structural diagrams corresponding to a manufacturing process of a fan-out package structure according to an embodiment of the utility model.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, most of the packages of chips constituting the conventional rf module are 2D wafer level packages. The component chips of the rf module typically include a filter, which may be a saw filter, and an SOI chip. The working principle of the acoustic surface filter is that sound waves are transmitted on the surface of a chip, so that the packaging form of the acoustic surface filter requires that the surface of an interdigital transducer of the acoustic surface filter must ensure enough cavities, otherwise, signal transmission is influenced. In the prior art, a sealed cavity is usually formed on an interdigital transducer of a filter chip, and then the sealed cavity is sequentially attached to a radio frequency module substrate to form a 2D packaging structure.
In view of the above problems, embodiments of the present invention provide a fan-out package structure, which performs chip packaging by directly bonding a wafer to a wafer, so as to achieve high integration and small size of a chip. Fig. 1 is a schematic structural diagram of a fan-out package structure according to an embodiment of the present invention, and referring to fig. 1, the fan-out package structure according to the embodiment of the present invention includes a first wafer 10, a second wafer 20, and a redistribution layer 30, where the first wafer 10 and the second wafer 20 both include a first surface and a second surface that are disposed opposite to each other;
the redistribution layer 30 includes a first insulating layer 31 disposed on the first surface of the first wafer 10 and a second insulating layer 32 disposed on the first surface of the second wafer 20, the first surface of the first wafer 10 is integrated with the second surface of the second wafer 20 in a fan-out manner, and a sealed cavity is formed between the first wafer 10 and the second wafer 20 through the first insulating layer 31;
the first wafer 10 is electrically connected through a via hole penetrating through the first insulating layer 31, the second wafer 20 and the second insulating layer 32.
Specifically, the first wafer 10 may be a filter wafer, the second wafer 20 may be an SOI wafer, and the first wafer 10 is directly bonded with the second wafer 20 in a fanout manner to form a larger-sized three-dimensional wafer. In this embodiment, the fan-out package structure further includes a redistribution layer 30, and the redistribution layer 30 is provided with a plurality of through holes penetrating through the second wafer 20, and the through holes are used for realizing circuit connection between the first wafer 10 and the second wafer 20 through a redistribution process.
The first surface of the first wafer 10 may be a front surface, and the second surface of the first wafer 10 may be a back surface; the first surface of the second wafer 20 is a front surface, and the second surface of the second wafer 20 is a back surface. The redistribution layer 30 includes a first insulating layer 31 disposed on the first surface of the first wafer 10 and a second insulating layer 32 disposed on the first surface of the second wafer 20. The first wafer 10 is bonded by bonding the first surface of the first wafer 10 and the second surface of the second wafer 20 together, i.e. bonding the first wafer 10 in a fan-out manner on the back side of the second wafer 20. In this embodiment, the first wafer 10 and the second wafer 20 may be bonded together by mounting, for example, by using a bonding adhesive. The redistribution layer 30 further includes a through hole that does not penetrate the second wafer 20, so that a sealed cavity is formed between the first surface of the first wafer 10 and the second surface of the second wafer 20 through the through hole on the first insulation 31 that does not penetrate the second wafer 20, thereby ensuring that the acoustic wave propagates without interference. It should be noted that the through hole penetrating the second wafer 20 mentioned in the embodiments of the present invention means that the through hole exposes the second wafer 20, and the through hole formed by the second wafer 20 is not etched.
The fan-out type packaging structure provided by the embodiment of the utility model comprises a first wafer, a second wafer and a rewiring layer, wherein the first wafer and the second wafer respectively comprise a first surface and a second surface which are arranged oppositely; the rewiring layer comprises a first insulating layer arranged on the first surface of the first wafer and a second insulating layer arranged on the first surface of the second wafer, the first surface of the first wafer is bonded through the wafer and is combined with the second surface of the second wafer into a whole in a fan-out mode, and a sealed cavity is formed between the first wafer and the second wafer through the first insulating layer; the first wafer is electrically connected through a through hole penetrating through the first insulating layer, the second wafer and the second insulating layer. Compared with the prior art, the technical scheme provided by the embodiment of the utility model bonds the first wafer and the second wafer together in a fan-out mode to form the fan-out type three-dimensional wafer, so that the size flexibility of the wafer is higher, the wafer bonding method can adapt to the bonding of the wafers with different sizes, the integration level of wafer packaging is greatly improved, the occupied area of the wafer packaging can be reduced, and the utilization rate of the wafer is improved.
In the present embodiment, the first wafer 10 includes a sonography filter wafer, the substrate material of which includes lithium tantalate or lithium niobate, and the substrate material of the second wafer 20 includes silicon. The first wafer 10 of the small-sized lithium tantalate or lithium niobate substrate and the second wafer 20 of the silicon substrate are reconstructed into the three-dimensional wafer with larger size in a fan-out mode, so that the small-sized limitation of the first wafer 10 taking the lithium tantalate or lithium niobate as the substrate is broken, the production efficiency of the wafer is greatly improved, and the production cost is favorably reduced.
Optionally, fig. 2 is a schematic structural diagram of another fan-out package structure according to an embodiment of the present invention, and referring to fig. 2, based on the above technical solution, a first pad 101 is disposed on a first wafer 10, a second pad 201 is disposed on a second wafer 20, a first insulating layer 31 includes at least one first through hole 311 exposing the first pad 101, a second insulating layer 32 includes at least one second through hole 321 exposing the second pad 201 and at least one third through hole 322 exposing the second wafer 20, the first through hole 311 and the third through hole 322 penetrate the second wafer 20 to form a fourth through hole 33, the fourth through hole 33 and the second through hole 321 are filled with a conductive material, and the first pad 101 and the second pad 201 are electrically connected through a metal trace 40.
Specifically, the first through hole 311 on the first insulating layer 31 and the third through hole 322 on the second insulating layer 32 penetrate the second wafer 20 and form the fourth through hole 33 as a whole. The first bonding pads 101 are located on the first surface of the first wafer 10, and the second bonding pads 201 are located on the first surface of the second wafer 20. The first pad 101 and the second pad 201 are electrically connected through the fourth via 33, wherein the fourth via 33 is filled with a conductive material. In this embodiment, the conductive material may fill the fourth through hole 33, or may be coated along the inner wall of the fourth through hole 33, and a protective layer (e.g., green oil) is disposed on the outer layer of the conductive material. A metal trace 40 is disposed above the second insulating layer 32, and the metal trace 40 is disposed along the surface of the second insulating layer 32 and connected to the conductive material in the fourth via hole 33 and the second via hole 321 to electrically connect the first pad 101 and the second pad 201, thereby implementing circuit connection between the first wafer 10 and the second wafer 20.
Optionally, fig. 3 is a schematic structural diagram of another fan-out package structure according to an embodiment of the present invention, and referring to fig. 3, on the basis of the above technical solution, the redistribution layer 30 further includes a third insulating layer 34 disposed on a side of the second insulating layer 32 away from the second wafer 20, and the third insulating layer 34 covers the metal trace 40. The third insulating layer 34 mainly plays a role in protecting the metal trace 40 from being corroded by the external environment.
Alternatively, fig. 4 is a top view of another fan-out package structure provided by the embodiment of the utility model, fig. 3 is a cross-sectional view of the fan-out package structure shown in fig. 4 along a cutting line AA', and referring to fig. 3 and fig. 4, the fan-out package structure further includes a metal bump 50; the metal bump 50 is disposed on a side of the third insulating layer 34 away from the second insulating layer 32, and is connected to the metal trace 40 through the conductive pillar 60. The third insulating layer 34 is provided with an opening, and a conductive pillar 60 is formed in the opening for leading out the metal trace 40. The metal bump 50 is disposed on the conductive pillar 60 and exposed on the third insulating layer 34 for electrical connection with other devices.
Optionally, fig. 5 is a schematic structural diagram of another fan-out package structure provided by an embodiment of the utility model, and referring to fig. 5, on the basis of the above technical solution, along the thickness direction of the wafer, the surface of the first pad 101 is higher than the first surface of the first wafer 10, and the second pad 201 is also higher than the first surface of the second wafer 20, so as to facilitate soldering. The first insulating layer 31 covers the first pad 101, and the second insulating layer 32 covers the second pad 201, so that the contact area between the first insulating layer 31 and the first pad 101 is increased, and the contact area between the second insulating layer 32 and the second pad 201 is increased, which is beneficial to improving the adhesion between the first insulating layer 31 and the first wafer 10, and the adhesion between the second insulating layer 32 and the second wafer 20, thereby being beneficial to improving the bonding reliability between the first wafer 10 and the second wafer 20.
Optionally, fig. 6 is a schematic structural diagram of another fan-out package structure according to an embodiment of the present invention, and referring to fig. 6, based on the above technical solution, the fan-out package structure further includes a plastic package structure 70, and the plastic package structure 70 is wrapped on the second surface and the side surface of the first wafer 10.
Specifically, the plastic package structure 70 includes a top surface and a bottom surface that are oppositely disposed, the bottom surface of the plastic package structure 70 is in contact with the second surface of the first wafer 10, and the top surface of the plastic package structure 70 is flush with the surface of the first insulating layer 31 on the side away from the first wafer 10 and is in contact with the second surface of the second wafer 20. The top surface of the plastic package structure 70 is open and flush with the surface of the first insulating layer 31 on the side away from the first wafer 10, that is, the top surface abuts against the second surface of the second wafer 20, and the ground surface of the plastic package structure 70 abuts against the second surface of the first wafer 10. In other words, the plastic package structure 70 wraps the second surface and the side surface of the first wafer 10, and in combination with the first insulating layer 31, the plastic package structure 70 can completely wrap the first wafer 10, so as to provide protection for the first wafer 10.
Optionally, fig. 7 to 17 are schematic structural diagrams corresponding to a manufacturing process of a fan-out package structure provided in an embodiment of the present invention, and based on the above technical solutions, referring to fig. 7 to 17, a specific manufacturing process of the fan-out package structure provided in the embodiment of the present invention is as follows:
as shown in fig. 7-10, a first wafer 10 is provided, in which the first wafer 10 is an acoustic surface filter wafer, and a first surface of the first wafer 10 is provided with a first pad 101. A first insulating layer 31 is formed on the first surface of the first wafer 10, and the first insulating layer 31 covers the first surface of the first wafer 10. Then, a photoresist layer 80 is coated on the first insulating layer 31, exposure and development are performed under the illumination condition to form a mask pattern, the first insulating layer 31 is etched according to the mask pattern to form a first through hole 311, and the photoresist layer 80 is etched away. Then, a dicing process is performed on the first wafer 10 to form a single first wafer 10.
As shown in fig. 11-13, a second wafer 20 is provided, the second wafer 10 is an SOI (e.g., integrated inductor capacitor, antenna switch, low noise amplifier, etc.) wafer, and a first surface of the second wafer 20 is provided with a second bonding pad 201. And bonding a first carrier 41 on the first surface of the second wafer 20, grinding and thinning the second surface of the second wafer 20, and etching a through hole penetrating through the second wafer 20 by using a Through Silicon Via (TSV) process. And coating a layer of bonding glue on the second surface of the second wafer 20, and attaching the cut first wafer 10 to the second surface of the second wafer 20, thereby completing bonding of the first wafer 10 and the second wafer 20. The first through holes 311 correspond to the through holes on the second wafer 20, and the first wafer 10 is attached to the second surface of the second wafer 20 in a fan-out manner. In this embodiment, the substrate of the first wafer 10 is lithium tantalate or lithium niobate, and due to the particularity of the material, the wafer is likely to warp during the bonding process. Therefore, the first carrier 41 is bonded to the first surface of the second wafer 20 before bonding, so as to provide a supporting protection function. The first carrier 41 is a temporary bonding carrier, and is used to prevent the wafer from curling during the manufacturing process and reduce the risk of wafer breakage.
As shown in fig. 14, after the bonding of the first wafer 10 and the second wafer 20 is completed, a plastic package structure 70 is formed on the second surface and the side surface of the first wafer 10 by using a plastic package process, so that the first wafer 10 and the second wafer 20 form a fan-out three-dimensional reconstruction wafer.
As shown in fig. 15-17, the first carrier 41 on the first surface of the second wafer 20 is debonded, and the second carrier 42 is bonded on the plastic package surface of the reconstituted wafer, so as to reduce the warpage of the wafer during the manufacturing process and ensure the smooth proceeding of the subsequent manufacturing process.
Afterwards, a second insulating layer 32 is deposited on the first surface of the second wafer 20, and a third via hole 322 is etched at a position of the second insulating layer 32 corresponding to the first via hole 311, and a second via hole 321 is etched at a position corresponding to the second pad 201. Wherein the first insulating layer 31 and the second insulating layer 32 together form the rewiring layer 30. The first via hole 311 on the first insulating layer 31 and the third via hole 322 on the second insulating layer 32 penetrate the second wafer 20 and form a fourth via hole 33 as a whole. The first bonding pads 101 are located on the first surface of the first wafer 10, and the second bonding pads 201 are located on the first surface of the second wafer 20. The first pad 101 and the second pad 201 are electrically connected through the fourth via 33, wherein the fourth via 33 is filled with a conductive material. In this embodiment, the conductive material may fill the fourth through hole 33, or may be coated along the inner wall of the fourth through hole 33, and a protective layer (e.g., green oil) is disposed on the outer layer of the conductive material. A re-routing process is adopted to form a metal trace 40 above the second insulating layer 32, the metal trace 40 is arranged along the surface of the second insulating layer 32 and is connected with the conductive materials in the fourth through hole 33 and the second through hole 321, so that the electrical connection between the first bonding pad 101 and the second bonding pad 201 is realized, and the circuit connection between the first wafer 10 and the second wafer 20 is realized.
After the metal trace 40 is formed, the third insulating layer 34 is formed on the metal trace 40, and the third insulating layer 34 mainly plays a role in protection and prevents the metal trace 40 from being corroded by the external environment. Then, the bump process is continued on the third insulating layer 34 to form the metal bump 50, the metal bump 50 is disposed on one side of the third insulating layer 34 away from the second insulating layer 32 and is connected to the metal trace 40 through the conductive pillar 60, and the conductive pillar 60 is used to lead out the metal trace 40. In this embodiment, the conductive pillar 60 and the metal bump 50 may be made of the same material.
Finally, the second carrier 42 is de-bonded to complete the fan-out package structure.
According to the technical scheme provided by the embodiment of the utility model, the first wafer and the second wafer are bonded together in a fan-out mode to form the fan-out type three-dimensional wafer, so that the size flexibility of the wafer is higher, the wafer bonding method can adapt to the bonding of the wafers with different sizes, the integration level of wafer packaging is greatly improved, the occupied area of wafer packaging can be reduced, and the utilization rate of the wafer is improved. In addition, the first wafer 10 and the second wafer 20 of the silicon substrate are reconstructed into a three-dimensional wafer with a larger size in a fan-out manner, so that the limitation of small-size wafers is broken, the production efficiency of the wafers is greatly improved, and the production cost is favorably reduced. In the manufacturing process, a plurality of temporary bonding support plates are adopted to provide support protection for the reconstructed wafer, so that the warping of the wafer can be effectively improved, and the risk of cracking is reduced.
Optionally, an embodiment of the present invention further provides a radio frequency module, including the fan-out package structure provided in any embodiment of the present invention, so that the radio frequency module provided in the embodiment of the present invention also has the beneficial effects described in any embodiment above, and details are not described herein again.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A fan-out package structure, comprising: the wafer structure comprises a first wafer, a second wafer and a rewiring layer, wherein the first wafer and the second wafer respectively comprise a first surface and a second surface which are arranged oppositely;
the redistribution layer comprises a first insulating layer arranged on the first surface of the first wafer and a second insulating layer arranged on the first surface of the second wafer, the first surface of the first wafer is combined with the second surface of the second wafer into a whole in a fan-out mode, and a sealed cavity is formed between the first wafer and the second wafer through the first insulating layer;
the first wafer is electrically connected through a through hole penetrating through the first insulating layer, the second wafer and the second insulating layer.
2. The fan-out package structure of claim 1, wherein the first wafer has a first pad disposed thereon, the second wafer has a second pad disposed thereon, the first insulating layer includes at least one first via exposing the first pad, the second insulating layer includes at least one second via exposing the second pad and at least one third via exposing the second wafer, the first and third vias form a fourth via through the second wafer;
and conductive materials are filled in the fourth through hole and the second through hole, and the first welding pad is electrically connected with the second welding pad through metal routing.
3. The fan-out package structure of claim 2, wherein the redistribution layer further comprises a third insulating layer disposed on a side of the second insulating layer away from the second wafer, the third insulating layer covering the metal trace.
4. The fan-out package structure of claim 3, further comprising metal bumps;
the metal bumps are arranged on one side, far away from the second insulating layer, of the third insulating layer and are connected with the metal wiring through the conductive posts.
5. The fan-out package structure of claim 2, wherein the first insulating layer covers the first pad and the second insulating layer covers the second pad.
6. The fan-out package structure of claim 1, further comprising a plastic encapsulated structure encapsulating the second surface and the side surface of the first wafer.
7. The fan-out package structure of claim 6, wherein the plastic package structure comprises a top surface and a bottom surface that are opposite to each other, the bottom surface of the plastic package structure is in contact with the second surface of the first wafer, and the top surface of the plastic package structure is flush with the surface of the first insulating layer on the side away from the first wafer and is in contact with the second surface of the second wafer.
8. The fan-out package structure of claim 1, wherein the first wafer comprises an acoustic surface filter wafer.
9. The fan-out package structure of claim 1, wherein the substrate material of the first wafer comprises lithium tantalate or lithium niobate, and the substrate material of the second wafer comprises silicon.
10. A radio frequency module comprising the fan-out package structure of any one of claims 1-9.
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