CN112967940A - Wafer-level packaging method and structure of thin-film resonator - Google Patents

Wafer-level packaging method and structure of thin-film resonator Download PDF

Info

Publication number
CN112967940A
CN112967940A CN202110145337.1A CN202110145337A CN112967940A CN 112967940 A CN112967940 A CN 112967940A CN 202110145337 A CN202110145337 A CN 202110145337A CN 112967940 A CN112967940 A CN 112967940A
Authority
CN
China
Prior art keywords
wafer
layer
thin film
film resonator
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110145337.1A
Other languages
Chinese (zh)
Other versions
CN112967940B (en
Inventor
钱盈
唐兆云
赖志国
杨清华
王家友
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Huntersun Electronics Co Ltd
Original Assignee
Suzhou Huntersun Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Huntersun Electronics Co Ltd filed Critical Suzhou Huntersun Electronics Co Ltd
Priority to CN202110145337.1A priority Critical patent/CN112967940B/en
Publication of CN112967940A publication Critical patent/CN112967940A/en
Application granted granted Critical
Publication of CN112967940B publication Critical patent/CN112967940B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02331Multilayer structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02373Layout of the redistribution layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0237Disposition of the redistribution layers
    • H01L2224/02381Side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/111Manufacture and pre-treatment of the bump connector preform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13005Structure
    • H01L2224/13008Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

The invention discloses a wafer level packaging method and a structure of a thin film resonator. The method comprises the following steps: preparing a first wafer, wherein the first wafer is provided with a first surface and a second surface opposite to the first surface, the first surface of the first wafer is provided with at least one thin film resonator unit and at least two bonding pads, and the bonding pads are electrically connected with electrodes of the thin film resonator unit; preparing a second wafer, wherein the second wafer is provided with a third surface and a fourth surface opposite to the third surface; placing the first surface of the first wafer on the third surface side of the second wafer; forming a groove in the second wafer, wherein the groove exposes part or all of the bonding pad; forming a wiring layer on the bottom surface and the side wall of the groove, wherein the wiring layer is electrically connected with the bonding pad; and cutting the second wafer and the first wafer along the groove. The technical scheme provided by the embodiment improves the packaging efficiency of the packaging method of the thin film resonator.

Description

Wafer-level packaging method and structure of thin-film resonator
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a wafer level packaging method and structure of a thin film resonator.
Background
A Film Bulk Acoustic Resonator (FBAR) has excellent characteristics such as a small size, a high resonance frequency, a high quality factor, and a large power capacity, and plays an important role in the field of communications.
In the prior art, a packaging method of a thin film resonator is to form a packaging structure including an independent supporting structure and an independent thin film resonator unit on a circuit board substrate to obtain a packaging structure of the thin film resonator. When a large amount of package structures of the thin film resonators need to be produced, the package efficiency of the package method using the thin film resonators is too low.
Disclosure of Invention
In view of this, embodiments of the present invention provide a wafer level packaging method and structure for a thin film resonator, so as to improve the packaging efficiency of the packaging method for the thin film resonator.
The embodiment of the invention provides a wafer-level packaging method of a thin film resonator, which comprises the following steps: preparing a first wafer, wherein the first wafer is provided with a first surface and a second surface opposite to the first surface, the first surface of the first wafer is provided with at least one thin film resonator unit and at least two bonding pads, and the bonding pads are electrically connected with electrodes of the thin film resonator unit;
preparing a second wafer having a third surface and a fourth surface opposite to the third surface;
placing the first surface of the first wafer on a third surface side of the second wafer;
forming a groove in the second wafer, wherein the groove exposes part or all of the bonding pad;
forming a wiring layer on the bottom surface and the side wall of the groove, wherein the wiring layer is electrically connected with the bonding pad;
and cutting the second wafer and the first wafer along the groove.
Optionally, the wiring layer extends to a fourth surface of the second wafer; the method further includes, before dicing the second wafer and the first wafer along the trench:
forming at least two conductive connection structures on the fourth surface of the second wafer, wherein the conductive connection structures are electrically connected with the wiring layer;
forming a first protective layer on the fourth surface side of the second wafer, wherein the first protective layer exposes the surface of the conductive connection structure on the side away from the second wafer and is flush with the surface of the conductive connection structure on the side away from the second wafer;
and forming a heavy wiring layer on the surface of the first protective layer on the side far away from the second wafer.
Optionally, preparing the second wafer comprises:
providing a second wafer;
forming at least one seal ring structure at a third surface of the second wafer;
correspondingly, placing the first surface of the first wafer on the third surface side of the second wafer comprises:
placing the first surface of the first wafer on a third surface side of a second wafer including the seal ring structure, wherein the seal ring structure surrounds the thin-film resonator unit, and a portion of the bonding pad covers the seal ring structure.
Optionally, the forming a redistribution layer on the surface of the first protection layer on the side away from the second wafer includes:
and forming a redistribution layer comprising an inductance structure on the surface of one side, away from the second wafer, of the first protection layer.
Optionally, after forming a redistribution layer on a surface of the first protection layer on a side away from the second wafer, the method further includes:
and forming an insulating layer on the surface of the redistribution layer on the side far away from the second wafer, wherein the insulating layer comprises at least one opening structure, and the opening structure exposes part of the redistribution layer.
Optionally, the forming a first protection layer on the fourth surface side of the second wafer includes:
forming a protective material layer on the fourth surface side of the second wafer, wherein the protective material layer covers the conductive connection structure;
and carrying out planarization treatment on the protective material layer to form the first protective layer.
Optionally, before forming the trench in the second wafer, the method further includes:
and thinning the fourth surface of the second wafer.
Optionally, before cutting the second wafer and the first wafer along the trench, the method further includes:
forming a second protective layer on the second surface of the first wafer;
forming a supporting layer on one side, far away from the first wafer, of the second protective layer;
the method further includes, after dicing the second wafer and the first wafer along the trench:
and removing the supporting layer.
Optionally, before forming the second protective layer on the second surface of the first wafer, the method further includes:
and thinning the second surface of the first wafer.
Optionally, placing the first surface of the first wafer on the third surface side of the second wafer comprises:
placing the first surface of the first wafer on the third surface side of the second wafer by a bonding process.
The embodiment of the invention also provides a wafer level packaging structure of the thin film resonator, which comprises the following components: the wafer comprises a first wafer and a second wafer, wherein the first wafer is provided with a first surface and a second surface opposite to the first surface, the first surface of the first wafer is provided with a thin film resonator unit and at least two bonding pads, and the bonding pads are electrically connected with electrodes of the thin film resonator unit;
a second wafer having a third surface and a fourth surface opposite the third surface, the first surface of the first wafer being located on a third surface side of the second wafer;
the second wafer is provided with a groove and a wiring layer, and the groove exposes part or all of the bonding pad; the wiring layer is located on the bottom surface and the side wall of the groove, and the wiring layer is electrically connected with the bonding pad.
Optionally, the device further comprises at least two conductive connection structures, a first protection layer and a redistribution layer;
the conductive connection structure is located on the fourth surface of the second wafer, the wiring layer extends to the fourth surface of the second wafer, and the conductive connection structure is electrically connected with the wiring layer;
the first protection layer is located on a fourth surface of the second wafer, wherein the first protection layer exposes the surface of the conductive connection structure on the side far away from the second wafer and is flush with the surface of the conductive connection structure on the side far away from the second wafer;
the rewiring layer is located on the surface of one side, away from the second wafer, of the first protection layer.
Optionally, the thin film resonator unit further includes a seal ring structure located on the third surface of the second wafer and surrounding the thin film resonator unit, and a portion of the pad covers the seal ring structure.
Optionally, the redistribution layer includes an inductance structure.
Optionally, the wafer further includes an insulating layer, the insulating layer is located on a surface of the redistribution layer on a side away from the second wafer, and the insulating layer includes at least one opening structure, and a portion of the redistribution layer is exposed by the opening structure.
Optionally, the wafer further comprises a second protective layer, and the second protective layer is located on the second surface of the first wafer.
In this embodiment, a plurality of thin film resonator package structures are prepared through a first wafer and a second wafer, which is called as a thin film resonator wafer-level package method, so that the package efficiency of the thin film resonator package method is improved. According to the wafer-level packaging structure of the thin film resonator prepared by the method, the bonding pad is equivalent to an electric signal leading-out end of the thin film resonator unit, the wiring layers on the bottom surface and the side wall of the groove are electrically connected with the bonding pad to lead out the electric signal of the thin film resonator unit, so that the electric signal is electrically connected with an external circuit, a circuit board substrate is not needed to be used for realizing the electric connection with the external circuit, the production cost is saved, and the process flow is simplified. In addition, the formation of the trench in the second wafer can be completed by selecting a separate dry etching process and a separate wet etching process, or combining the dry etching process and the wet etching process, and the preparation of the trench is completed without using a Through Silicon Via (TSV) technology with higher process difficulty, so that the process difficulty is reduced.
Drawings
Fig. 1 is a wafer level packaging method of a thin film resonator according to an embodiment of the present invention;
fig. 2-7 are structural diagrams corresponding to steps of a wafer level packaging method for a thin film resonator according to an embodiment of the present invention;
fig. 8-19 are structural diagrams corresponding to steps of another wafer-level packaging method for a thin film resonator according to an embodiment of the present invention;
FIG. 20 is a flowchart illustrating another wafer level packaging method for a thin film resonator according to an embodiment of the present invention;
FIG. 21 is a schematic flow chart included in step 120 of FIG. 1;
FIG. 22 is a schematic flow chart included in step 1602 of FIG. 20;
fig. 23 is a flowchart illustrating a wafer level packaging method for a thin film resonator according to another embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the above background art, when the related art thin film resonator packaging method requires the production of a large number of thin film resonator packaging structures, the packaging efficiency of the thin film resonator packaging method is too low. For this reason, when a large number of package structures of the thin film resonator are required to be produced, the wafer including the support structure is further required to be cut to obtain the independent support structure, the wafer including the thin film resonator unit is cut to obtain the independent thin film resonator unit, and then the independent support structure and the independent thin film resonator unit are packaged and then formed on the circuit board substrate to form the package structure of the independent thin film resonator, so that the package efficiency of the package method using the thin film resonator is too low.
In view of the above technical problems, an embodiment of the present invention provides the following technical solutions:
fig. 1 is a wafer level packaging method of a thin film resonator according to an embodiment of the present invention. Fig. 2 to fig. 7 are structural diagrams corresponding to steps of a wafer-level packaging method for a thin film resonator according to an embodiment of the present invention. Referring to fig. 1, the wafer level packaging method of the thin film resonator includes the following steps:
step 110, preparing a first wafer, where the first wafer has a first surface and a second surface opposite to the first surface, the first surface of the first wafer is provided with at least one thin film resonator unit and at least two bonding pads, and the bonding pads are electrically connected to electrodes of the thin film resonator unit.
Referring to fig. 2, a first wafer 100 is prepared, the first wafer 100 having a first surface 100A and a second surface 100B opposite to the first surface 100A, the first surface 100A of the first wafer 100 being provided with at least one thin-film resonator unit 101 and at least two pads 102, the pads 102 being electrically connected to electrodes of the thin-film resonator unit 101. The thickness of the pad 102 is less than 1 micron. The pad 102 may be made of gold, which is a metal having good conductivity. However, the material selection of the bonding pad 102 is not limited thereto in the embodiment of the present invention.
Specifically, the thin-film resonator unit 101 includes a first electrode, a piezoelectric thin-film layer, and a second electrode, which are stacked, where the first electrode is electrically connected to the corresponding pad 102, and the second electrode is electrically connected to the corresponding pad 102. The piezoelectric thin film layer in the thin film resonator unit 101 is configured to deform according to a received sound signal, microscopically represents a vibration of a phonon, macroscopically forms a sound wave reflected back and forth between the first electrode and the second electrode, the sound wave is a bulk sound wave inside the piezoelectric thin film layer, and two opposite surfaces of the piezoelectric thin film layer have opposite charges, so that a potential difference is formed between the first electrode and the second electrode, and the potential difference is used as a corresponding electrical signal. The stronger the sound signal, the larger the voltage value corresponding to the electric signal. The pad 102 corresponds to an electrical signal terminal of the thin-film resonator unit 101 to achieve electrical connection with an external circuit.
Specifically, the first wafer 100 is used to support the thin film resonator unit 101, and in order to reduce the energy loss of the bulk acoustic wave in the thin film resonator unit 101, the air gap 103 for avoiding the energy loss of the acoustic wave is exemplarily shown in the present embodiment, so that the energy loss of the thin film resonator unit 101 is reduced, and the quality factor is improved. Specifically, a bragg reflection layer may be disposed between the first wafer 100 and the thin-film resonator unit 101 to reduce energy loss of the bulk acoustic wave in the thin-film resonator unit 101. However, the wafer level package structure of the thin film resonator provided by the embodiment of the present invention is not limited to the above structure for avoiding the loss of the acoustic wave energy.
Step 120, a second wafer is prepared, wherein the second wafer has a third surface and a fourth surface opposite to the third surface.
Referring to fig. 3, a second wafer 200 is prepared, the second wafer 200 having a third surface 200A and a fourth surface 200B opposite to the third surface 200A. Specifically, the second wafer 200 may be a high-resistivity silicon wafer, which has fewer lattice defects and is helpful for further reducing the energy loss of the bulk acoustic wave in the thin-film resonator unit 101.
Step 130, the first surface of the first wafer is placed on the third surface side of the second wafer.
Referring to fig. 4, the first surface 100A of the first wafer 100 is placed on the third surface 200A side of the second wafer 200.
Alternatively, the first surface 100A of the first wafer 100 may be placed on the third surface 200A side of the second wafer 200 by a bonding process. Specifically, the bonding process of the first wafer 100 and the second wafer 200 may be performed on the first surface 100A of the first wafer 100 and the third surface 200A of the second wafer 200 through a bonding adhesive layer (not shown).
Step 140 is forming a trench in the second wafer, the trench exposing a portion or all of the pad.
Referring to fig. 5, fig. 5a is a schematic structural diagram of a second surface 200B of the second wafer 20, and fig. 5B is a cross-sectional view of a portion of the second wafer 20 in fig. 5 a. It should be noted that the grooves 201 are used as dicing streets for subsequent dicing, and fig. 5a shows a plurality of grooves 201 extending along the X direction and the Y direction of the plane of the second surface 200B of the second wafer 20.
Referring to fig. 5, a trench 201 is formed in the second wafer 200, and the trench 201 exposes a part or all of the pad 102. In this embodiment, the formation of the trench 201 in the second wafer 200 may be completed by selecting a single dry etching process and a single wet etching process, or by combining the dry etching process and the wet etching process, and the preparation of the trench 201 does not need to use a Through Silicon Via (TSV) technique with high process difficulty. The trench 201 exposes part or all of the pad 102 to realize a circuit structure in the trench 201 of the second wafer 200 to lead out an electric signal of the thin film resonator unit 101, thereby realizing an electric connection with an external circuit.
And 150, forming a wiring layer on the bottom surface and the side wall of the groove, wherein the wiring layer is electrically connected with the bonding pad.
Referring to fig. 6, a wiring layer 202 is formed on the bottom surface and the sidewall of the trench 201, wherein the wiring layer 202 is electrically connected to the pad 102. The wiring layer 202 is electrically connected to the pad 102 to realize extraction of an electric signal of the thin-film resonator unit 101, thereby realizing electrical connection to an external circuit. On the basis that the second wafer 200 is a high-resistance silicon wafer, electrical insulation between the wiring layer 202 and the second wafer 200 can be achieved without providing an insulating layer between the wiring layer 202 and the second wafer 200. It should be noted that in this embodiment, an insulating layer may also be optionally disposed between the wiring layer 202 and the second wafer 200, so as to further ensure the electrical insulation between the wiring layer 202 and the second wafer 200. It should be noted that the wiring layer 202 formed by multiple layers of metal can be better electrically connected to the pad 102 than the wiring layer 202 formed by one layer of metal. Illustratively, the preparation of the wiring layer 202 may be completed by a metal sputtering process. The wiring layer 202 may be made of aluminum and/or copper, which are excellent in conductivity and inexpensive. Embodiments of the present invention are not limited to the above-described selection of materials for the wiring layer 202.
Step 160, cutting the second wafer and the first wafer along the groove.
Referring to fig. 6 and 7, the second wafer 200 and the first wafer 100 are diced along the trenches 201 to obtain the wafer-level package structure of the independent thin film resonator shown in fig. 7.
In this embodiment, a plurality of thin film resonator package structures are prepared through the first wafer 100 and the second wafer 200, which is called as a thin film resonator wafer-level package method, so that the package efficiency of the thin film resonator package method is improved, and due to the wafer-level package, compared with the case where an independent support structure and an independent thin film resonator unit are packaged by metal bonding, the pad 102 does not need to be set to a thickness greater than or equal to 1 micron, so that the size of the thin film resonator package structure is reduced, and the production cost is reduced. In the wafer-level packaging structure of the thin film resonator prepared by the method, the pad 102 is equivalent to an electric signal leading-out end of the thin film resonator unit 101, the wiring layer 202 on the bottom surface and the side wall of the groove 201 is electrically connected with the pad 102 to lead out the electric signal of the thin film resonator unit 101, so that the electric signal is electrically connected with an external circuit, a circuit board substrate is not needed to be used for realizing the electric connection with the external circuit, the production cost is saved, and the process flow is simplified. In addition, the formation of the trench 201 in the second wafer 200 may be completed by selecting a single dry etching process and a single wet etching process, or by combining the dry etching process and the wet etching process, and the preparation of the trench 201 does not need to use a Through Silicon Via (TSV) technique with relatively high process difficulty, which reduces the process difficulty.
Optionally, before the second wafer 200 and the first wafer 100 are cut, laser marking may be performed on the second wafer 200 side, so as to distinguish the package structures of different thin film resonators.
In order to further achieve the technical effect of completely and stably electrically connecting the electrical signal of the thin film resonator unit 101 with an external circuit, the embodiment of the present invention further provides the following technical solutions:
fig. 8-19 are structural diagrams corresponding to steps of another wafer-level packaging method for a thin film resonator according to an embodiment of the present invention. Fig. 20 is a flowchart illustrating another wafer level packaging method for a thin film resonator according to an embodiment of the present invention.
On the basis of the above technical solution, referring to fig. 20, the wiring layer extends to the fourth surface of the second wafer; step 160 further includes, along the trench, before dicing the second wafer and the first wafer:
step 1601, at least two conductive connection structures are formed on the fourth surface of the second wafer, and the conductive connection structures are electrically connected with the wiring layer.
Referring to fig. 11, at least two conductive connection structures 203 are formed on the fourth surface 200B of the second wafer 200, and the conductive connection structures 203 are electrically connected to the wiring layer 202. Specifically, the conductive connection structure 203 may be made of copper, which has excellent conductive performance and heat dissipation performance. However, the material selection of the conductive connection structure 203 is not limited thereto in the embodiments of the present invention. The conductive connection structure 203 is used for leading out the electric signal of the thin film resonator unit 101, and further realizes the electric connection with an external circuit, and because the conductive connection structure 203 has a large volume and good heat dissipation performance, the technical effect of completely and stably electrically connecting the electric signal of the thin film resonator unit 101 with the external circuit can be realized. Illustratively, the height of the conductive connection structure 203 is greater than or equal to 40 microns and less than or equal to 90 microns. When the height of the conductive connection structure 203 is too small to be smaller than 40 μm, the volume of the conductive connection structure 203 is too small on the basis of ensuring the conductive connection structure 203 with a predetermined cross-sectional area, and the heat dissipation performance of the package structure of the thin film resonator is not good. When the height of the conductive connection structure 203 is too large, which is larger than 90 μm, the volume of the conductive connection structure 203 is too large on the basis of ensuring the conductive connection structure 203 with a predetermined cross-sectional area, and the size of the package structure of the thin film resonator is too large to be matched with other electrical devices.
Step 1602, a first protection layer is formed on a fourth surface side of the second wafer, wherein the first protection layer exposes a surface of the conductive connection structure away from the second wafer and is flush with a surface of the conductive connection structure away from the second wafer.
Referring to fig. 13, a first passivation layer 204 is formed on the fourth surface 200B of the second wafer 200, wherein the first passivation layer 204 exposes a surface of the conductive connection structure 203 on a side away from the second wafer 200 and is flush with a surface of the conductive connection structure 203 on a side away from the second wafer 200. It should be noted that the first protection layer 204 described in the embodiment of the present invention covers the trench 201, the wiring layer 202, and the portion of the pad 102 that is not covered by the wiring layer 202. Specifically, the conductive connection structure 203 is used to lead out an electrical signal of the thin-film resonator unit 101, so as to be electrically connected to an external circuit. When the external circuit is electrically connected to the thin film resonator unit 101 through the conductive connection structure 203, since the first protection layer 204 only exposes the surface of the conductive connection structure 203 on the side away from the second wafer 200 and is flush with the surface of the conductive connection structure 203 on the side away from the second wafer 200, the arrangement of the first protection layer 204 provides a flat contact surface for connecting the package structure of the thin film resonator with the external circuit, so as to improve the mechanical stability of the thin film resonator unit 101 in electrical connection with the external circuit, and in addition, the first protection layer 204 can protect the conductive connection structure 203, the wiring layer 202 and the pad 102 from mechanical damage caused by an external force. The first protection layer 204 may be filled with an insulating material on the fourth surface 200B side of the second wafer 200, and covers the trench 201, the wiring layer 202, and the portion of the pad 102 not covered by the wiring layer 202, and then the first protection layer 204 with a certain mechanical strength is formed by curing. For example, the first protection layer 204 may be formed by an epoxy molding compound, which has good insulation and a certain mechanical strength after being cured. However, the material of the first protection layer 204 is not limited to the above selection in the embodiment of the present invention.
Step 1603, forming a redistribution layer on the surface of the first protection layer on the side far away from the second wafer, wherein the redistribution layer is electrically connected with the conductive connection structure.
Referring to fig. 14, a redistribution layer 205 is formed on a surface of the first protection layer 204 on a side away from the second wafer 200, wherein the redistribution layer is electrically connected to the conductive connection structure 203. Specifically, the redistribution layer 205 is electrically connected with the conductive connection structure 203, and the conductive connection structure 203 can lead out the electrical signal of the thin film resonator unit 101, so that the redistribution layer 205 can electrically connect the electrical signal lead-out of the thin film resonator unit 101 with an external circuit. It should be noted that the redistribution layer 205 formed by multiple layers of metal can be better electrically connected to the conductive connection structure 203 than the redistribution layer 205 formed by one layer of metal. Illustratively, the fabrication of the redistribution layer 205 may be completed by a metal sputtering process. Illustratively, some circuit structures that are impedance-matched to the electrical signals of the thin-film resonator unit 101 may be fabricated in the redistribution layer 205 to avoid loss of the electrical signals of the thin-film resonator unit 101. The redistribution layer 205 may be made of copper metal having good conductivity and low cost. Embodiments of the present invention are not limited to the above-described selection of materials for the redistribution layer 205.
Optionally, referring to fig. 14, a redistribution layer 205 including an inductance structure is formed on a surface of the first protection layer 204 on a side away from the second wafer 200.
Specifically, the redistribution layer 205 including the inductance structure may form an impedance-matched circuit structure with the electrical signal of the thin-film resonator unit 101 to avoid loss of the electrical signal of the thin-film resonator unit 101.
In order to ensure that a closed space is formed between the first wafer 100 and the second wafer 200, the embodiment of the present invention further provides the following technical solutions:
fig. 21 is a schematic flow chart included in step 120 in fig. 1. Referring to fig. 21, the step 120 of preparing the second wafer includes:
step 1201, a second wafer is provided.
Referring to fig. 3, a second wafer 200 is provided, the second wafer 200 having a third surface 200A and a fourth surface 200B opposite to the third surface 200A.
At step 1202, at least one seal ring structure is formed on the third surface of the second wafer.
Referring to fig. 8, wherein fig. 8a is a top view and fig. 8b is a cross-sectional view of the second wafer 200, at least one seal ring structure 206 is formed on the third surface 200A of the second wafer 200. Correspondingly, the step 130 of placing the first surface of the first wafer on the third surface side of the second wafer comprises:
the first surface of the first wafer is placed on the third surface side of the second wafer including a seal ring structure, wherein the seal ring structure surrounds the thin-film resonator unit, and a portion of the bonding pad covers the seal ring structure.
Referring to fig. 9, where fig. 9a is a top view of the seal-ring structure 206 and the pad 102, and fig. 9b is a cross-sectional view of the first wafer 100 and the second wafer 200 after bonding, the first surface 100A of the first wafer 100 is placed on the third surface 200A side of the second wafer 200 including the seal-ring structure 206, where the seal-ring structure 206 surrounds the thin-film resonator unit 101, and a portion of the pad 102 covers the seal-ring structure 206. The arrangement of the seal ring structure 206 can ensure that a closed space is formed between the first wafer 100 and the second wafer 200, so as to avoid the loss of the external environment to the thin film resonator unit 101, and the seal ring structure 206 is arranged inside the package structure of the thin film resonator, so that the size of the package structure of the thin film resonator is further reduced compared with the package structure of the thin film resonator.
For example, the seal ring structure 206 may be made of a dry film material, which is a polymer compound having a certain viscosity under a certain temperature or pressure condition, so that the bonding process between the first wafer 100 and the second wafer 200 can be performed on the seal ring structure 206. Specifically, a tape-shaped dry film material may be attached to the third surface 200A of the second wafer 200 to form at least one seal ring structure 206.
The seal ring structure 206 may also be made of a non-adhesive material, such as Polyimide (PI) or Dibenzoyl peroxide (BPO). Specifically, a dispensing or brushing process may be used to form at least one seal ring structure 206 on the third surface 200A of the second wafer 200 with polyimide or dibenzoyl peroxide. Since polyimide or dibenzoyl peroxide has no adhesiveness, when bonding the first wafer 100 and the second wafer 200, a bonding adhesive layer needs to be formed between the first wafer 100 and the second wafer 200 to complete the bonding process of the first wafer 100 and the second wafer 200, so as to enable the first surface 100A of the first wafer 100 to be placed on the third surface 200A side of the second wafer 200 including the seal ring structure 206.
Illustratively, the height of the seal ring structure 206 is greater than or equal to 5 microns and less than or equal to 10 microns, and the width of the seal ring structure 206 is greater than or equal to 50 microns and less than or equal to 100 microns. The specific dimensions of the seal ring structure 206 may be adjusted according to the actual specifications.
In the above technical solution, the redistribution layer 205 is electrically connected to the conductive connection structure 203, and the conductive connection structure 203 can lead out an electrical signal of the thin film resonator unit 101, so that the redistribution layer 205 can lead out the electrical signal of the thin film resonator unit 101 to be electrically connected to an external circuit. It should be noted that the redistribution layer 205 includes an external electrical connection portion and a functional line portion, and in order to protect the functional line in the redistribution layer 205, the embodiment of the present invention further provides the following technical solution:
referring to fig. 15, step 1603 further includes, after forming the redistribution layer on the surface of the first protection layer on the side away from the second wafer:
an insulating layer 207 is formed on a surface of the redistribution layer 205 on a side away from the second wafer 200, wherein the insulating layer 207 includes at least one opening structure 207A, and a portion of the redistribution layer 205 is exposed by the opening structure 207A.
Specifically, the opening structure 207A exposes a portion of the redistribution layer 205, the portion of the redistribution layer 205 is an external electrical connection portion of the redistribution layer 205, and the external electrical connection portion of the redistribution layer 205 is used for electrical connection with an external circuit, so as to extract an electrical signal of the thin film resonator unit 101 and electrically connect with the external circuit. The functional line portion of the rewiring layer 205 may be some circuit structure that is impedance-matched to the electric signal of the thin-film resonator unit 101 to avoid loss of the electric signal of the thin-film resonator unit 101.
The formation of the first protective layer flush with the surface of the conductive connection structure on the side remote from the second wafer is described in detail below. FIG. 22 is a flowchart included in step 1602 of FIG. 20. On the basis of the above technical solution, referring to fig. 22, the step 1602 of forming a first protection layer on the fourth surface side of the second wafer includes:
step 16020, forming a protective material layer on the fourth surface side of the second wafer, wherein the protective material layer covers the conductive connection structure.
Referring to fig. 12, a protective material layer 204A is formed on the fourth surface 200B side of the second wafer 200, wherein the protective material layer 204A covers the conductive connection structure 203. It should be noted that the protective material layer 204A described in the embodiment of the present invention also covers the trench 201, the wiring layer 202, and a portion of the pad 102 that is not covered by the wiring layer 202. The protective material layer 204A may be filled on the fourth surface 200B of the second wafer 200 with an insulating material, and has a certain mechanical strength after being cured.
Step 16021, a planarization process is performed on the protection material layer to form a first protection layer.
Referring to fig. 13, the protective material layer 204A is subjected to a planarization process to form the first protective layer 204.
In the above technical solution, the protection material layer 204A is planarized to form the first protection layer 204, so as to provide a flat contact surface for connecting the package structure of the thin film resonator with an external circuit, so as to improve the mechanical stability of the thin film resonator unit 101 in electrical connection with the external circuit, and in addition, the first protection layer 204 can protect the conductive connection structure 203, the wiring layer 202 and the pad 102 from mechanical damage caused by an external force.
On the basis of the above technical solution, the step 140 further includes, before forming the trench in the second wafer:
the fourth surface 200B of the second wafer 200 is thinned.
Referring to fig. 10, the fourth surface 200B of the second wafer 200 is thinned. Specifically, the thinned second wafer 200 may reduce the size of the package structure of the thin film resonator.
In order to protect and realize the protection of the first wafer 100, the embodiment of the present invention further provides the following technical solutions:
fig. 23 is a flowchart illustrating a wafer level packaging method for a thin film resonator according to another embodiment of the present invention. On the basis of the above technical solution, referring to fig. 23, step 160 further includes, before the dicing the second wafer and the first wafer along the trench:
step 1604, a second passivation layer is formed on the second surface of the first wafer.
Referring to fig. 17, a second passivation layer 104 is formed on the second surface 100B of the first wafer 100.
And 1605, forming a supporting layer on the side of the second protective layer far away from the first wafer.
Referring to fig. 18, a side of the second passivation layer 104 away from the first wafer 100 is formed into a support layer 300. Step 160 further includes, along the trench, after dicing the second wafer and the first wafer:
and removing the support layer.
Referring to fig. 19, the support layer 300 is removed. Specifically, the second passivation layer 104 is used to protect the first wafer 100 from mechanical damage caused by external force. The second protective layer 10 may be made of an organic material, which has a good buffering effect on external stress. The support layer 300 is used to support the second wafer 200 and the first wafer 100 when the second wafer 200 and the first wafer 100 are cut along the grooves 201. Illustratively, the support layer 300 may be a material sensitive to ultraviolet light to achieve an effect of easily removing the support layer 300.
Optionally, on the basis of the foregoing technical solution, before the step 1604 forms the second protection layer on the second surface of the first wafer, the method further includes:
and thinning the second surface of the first wafer.
Referring to fig. 16, the second surface 100B of the first wafer 100 is thinned. The thinning of the processed first wafer 100 may further reduce the size of the package structure of the thin film resonator.
The embodiment of the invention also provides a wafer level packaging structure of the thin film resonator. Taking fig. 7 as an example for explanation, referring to fig. 7, the wafer level package structure of the thin film resonator includes: a first wafer 100, the first wafer 100 having a first surface 100A and a second surface 100B opposite to the first surface 100A, the first surface 100A of the first wafer 100 being provided with at least one thin-film resonator unit 101 and at least two pads 102, the pads 102 being electrically connected to electrodes of the thin-film resonator unit 101; a second wafer 200, the second wafer 200 having a third surface 200A and a fourth surface 200B opposite to the third surface 200A, the first surface 100A of the first wafer 100 being located on the third surface 200A side of the second wafer 200; the second wafer 200 is provided with a trench 201 and a wiring layer 202, the trench 201 exposing a part or all of the pad 102; the wiring layer 202 is located on the bottom surface and the sidewall of the trench 201, and the wiring layer 202 is electrically connected to the pad 102.
In this embodiment, a plurality of thin film resonator package structures are prepared through the first wafer 100 and the second wafer 200, which is called as a thin film resonator wafer-level package method, so that the package efficiency of the thin film resonator package method is improved, and due to the wafer-level package, compared with the case where an independent support structure and an independent thin film resonator unit are packaged by metal bonding, the pad 102 does not need to be set to a thickness greater than or equal to 1 micron, so that the size of the thin film resonator package structure is reduced, and the production cost is reduced. In the wafer-level packaging structure of the thin film resonator prepared by the method, the pad 102 is equivalent to an electric signal leading-out end of the thin film resonator unit 101, the wiring layer 202 on the bottom surface and the side wall of the groove 201 is electrically connected with the pad 102 to lead out the electric signal of the thin film resonator unit 101, so that the electric signal is electrically connected with an external circuit, a circuit board substrate is not needed to be used for realizing the electric connection with the external circuit, the production cost is saved, and the process flow is simplified. In addition, the formation of the trench 201 in the second wafer 200 may be completed by selecting a single dry etching process and a single wet etching process, or by combining the dry etching process and the wet etching process, and the preparation of the trench 201 does not need to use a Through Silicon Via (TSV) technique with relatively high process difficulty, which reduces the process difficulty.
In order to further achieve the technical effect of completely and stably electrically connecting the electrical signal of the thin film resonator unit 101 with an external circuit, the embodiment of the present invention further provides the following technical solutions:
taking fig. 19 as an example for illustration, referring to fig. 19, the wafer level package structure of the thin film resonator further includes at least two conductive connection structures 203, a first protection layer 204, and a redistribution layer 205; the conductive connection structure 203 is located on the fourth surface 200B of the second wafer 200, the wiring layer 202 extends to the fourth surface 200B of the second wafer 200, and the conductive connection structure 203 is electrically connected to the wiring layer 202; the first passivation layer 204 is disposed on the fourth surface 200B of the second wafer 200, wherein the first passivation layer 204 exposes a surface of the conductive connection structure 203 on a side away from the second wafer 200, and is flush with a surface of the conductive connection structure 203 on a side away from the second wafer 200; the redistribution layer 205 is located on a surface of the first protection layer 204 on a side away from the second wafer 20.
Specifically, the redistribution layer 205 is electrically connected with the conductive connection structure 203, and the conductive connection structure 203 can lead out the electrical signal of the thin film resonator unit 101, so that the redistribution layer 205 can electrically connect the electrical signal lead-out of the thin film resonator unit 101 with an external circuit.
In order to ensure that a closed space is formed between the first wafer 100 and the second wafer 200, the embodiment of the present invention further provides the following technical solutions:
referring to fig. 19, the wafer-level package structure of the thin film resonator further includes a seal ring structure 206, the seal ring structure 206 is located on the third surface 200A of the second wafer 200 and surrounds the thin film resonator unit 101, and a portion of the pad 102 covers the seal ring structure 206.
Specifically, the arrangement of the seal ring structure 206 ensures that a sealed space is formed between the first wafer 100 and the second wafer 200, so as to avoid the loss of the external environment to the thin film resonator unit 101, and the seal ring structure 206 is arranged inside the package structure of the thin film resonator, so that compared with the arrangement at the periphery of the package structure of the thin film resonator, the size of the package structure of the thin film resonator is further reduced.
Optionally, on the basis of the above technical solution, the redistribution layer 205 including the inductance structure may form an impedance-matched circuit structure with the electrical signal of the thin film resonator unit 101, so as to avoid loss of the electrical signal of the thin film resonator unit 101.
In order to protect the functional lines in the redistribution layer 205, the embodiment of the present invention further provides the following technical solutions:
referring to fig. 19, the wafer level package structure of the thin film resonator further includes an insulating layer 207, the insulating layer 207 is located on a surface of the redistribution layer 205 on a side away from the second wafer 200, and the insulating layer 207 includes at least one opening structure 207A, and the opening structure 207A exposes a portion of the redistribution layer 205.
Specifically, the opening structure 207A exposes a portion of the redistribution layer 205, the portion of the redistribution layer 205 is an external electrical connection portion of the redistribution layer 205, and the external electrical connection portion of the redistribution layer 205 is used for electrical connection with an external circuit. The portion of the redistribution layer 205 not exposed by the opening structure 207A is a functional wiring portion, which may be some circuit structure that is impedance-matched to the electrical signal of the thin film resonator unit 101, so as to avoid loss of the electrical signal of the thin film resonator unit 101.
Optionally, on the basis of the above technical solution, referring to fig. 19, the wafer-level package structure of the thin film resonator further includes a second protection layer 104, where the second protection layer 104 is located on the second surface 100B of the first wafer 100. Specifically, the second passivation layer 104 is used to protect the first wafer 100 from mechanical damage caused by external force.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (16)

1. A wafer level packaging method of a thin film resonator is characterized by comprising the following steps: preparing a first wafer, wherein the first wafer is provided with a first surface and a second surface opposite to the first surface, the first surface of the first wafer is provided with at least one thin film resonator unit and at least two bonding pads, and the bonding pads are electrically connected with electrodes of the thin film resonator unit;
preparing a second wafer having a third surface and a fourth surface opposite to the third surface;
placing the first surface of the first wafer on a third surface side of the second wafer;
forming a groove in the second wafer, wherein the groove exposes part or all of the bonding pad;
forming a wiring layer on the bottom surface and the side wall of the groove, wherein the wiring layer is electrically connected with the bonding pad;
and cutting the second wafer and the first wafer along the groove.
2. The wafer-level packaging method for the thin film resonator according to claim 1, wherein the wiring layer extends to a fourth surface of the second wafer; the method further includes, before dicing the second wafer and the first wafer along the trench:
forming at least two conductive connection structures on the fourth surface of the second wafer, wherein the conductive connection structures are electrically connected with the wiring layer;
forming a first protective layer on the fourth surface side of the second wafer, wherein the first protective layer exposes the surface of the conductive connection structure on the side away from the second wafer and is flush with the surface of the conductive connection structure on the side away from the second wafer;
and forming a heavy wiring layer on the surface of the first protective layer on the side far away from the second wafer.
3. The wafer-level packaging method for the thin film resonator according to claim 1, wherein the preparing the second wafer comprises:
providing a second wafer;
forming at least one seal ring structure at a third surface of the second wafer;
correspondingly, placing the first surface of the first wafer on the third surface side of the second wafer comprises:
placing the first surface of the first wafer on a third surface side of a second wafer including the seal ring structure, wherein the seal ring structure surrounds the thin-film resonator unit, and a portion of the bonding pad covers the seal ring structure.
4. The wafer-level packaging method for the thin film resonator according to claim 2, wherein the forming of the redistribution layer on the surface of the first protective layer on the side away from the second wafer comprises:
and forming a redistribution layer comprising an inductance structure on the surface of one side, away from the second wafer, of the first protection layer.
5. The wafer-level packaging method for the thin film resonator according to claim 2, further comprising, after forming a redistribution layer on a surface of the first protective layer on a side away from the second wafer:
and forming an insulating layer on the surface of the redistribution layer on the side far away from the second wafer, wherein the insulating layer comprises at least one opening structure, and the opening structure exposes part of the redistribution layer.
6. The wafer-level packaging method for the thin film resonator according to claim 2, wherein the forming of the first protection layer on the fourth surface side of the second wafer comprises:
forming a protective material layer on the fourth surface side of the second wafer, wherein the protective material layer covers the conductive connection structure;
and carrying out planarization treatment on the protective material layer to form the first protective layer.
7. The wafer-level packaging method for the thin film resonator according to claim 1, further comprising, before the second wafer is grooved:
and thinning the fourth surface of the second wafer.
8. The wafer-level packaging method for the thin film resonator according to claim 1, wherein the dicing the second wafer and the first wafer along the trench further comprises:
forming a second protective layer on the second surface of the first wafer;
forming a supporting layer on one side, far away from the first wafer, of the second protective layer;
the method further includes, after dicing the second wafer and the first wafer along the trench:
and removing the supporting layer.
9. The wafer-level packaging method for the thin film resonator according to claim 8, wherein before forming the second protective layer on the second surface of the first wafer, the method further comprises:
and thinning the second surface of the first wafer.
10. The wafer-level packaging method for the thin film resonator according to any one of claims 1 to 9, wherein the placing the first surface of the first wafer on the third surface side of the second wafer comprises:
placing the first surface of the first wafer on the third surface side of the second wafer by a bonding process.
11. A wafer level packaging structure of a thin film resonator is characterized by comprising: the wafer comprises a first wafer and a second wafer, wherein the first wafer is provided with a first surface and a second surface opposite to the first surface, the first surface of the first wafer is provided with a thin film resonator unit and at least two bonding pads, and the bonding pads are electrically connected with electrodes of the thin film resonator unit;
a second wafer having a third surface and a fourth surface opposite the third surface, the first surface of the first wafer being located on a third surface side of the second wafer;
the second wafer is provided with a groove and a wiring layer, and the groove exposes part or all of the bonding pad; the wiring layer is located on the bottom surface and the side wall of the groove, and the wiring layer is electrically connected with the bonding pad.
12. The wafer-level package structure of the thin film resonator according to claim 11, further comprising at least two conductive connection structures, a first protection layer, and a redistribution layer;
the conductive connection structure is located on the fourth surface of the second wafer, the wiring layer extends to the fourth surface of the second wafer, and the conductive connection structure is electrically connected with the wiring layer;
the first protection layer is located on a fourth surface of the second wafer, wherein the first protection layer exposes the surface of the conductive connection structure on the side far away from the second wafer and is flush with the surface of the conductive connection structure on the side far away from the second wafer;
the rewiring layer is located on the surface of one side, away from the second wafer, of the first protection layer.
13. The wafer-level package structure of the thin film resonator of claim 11, further comprising a seal ring structure located on the third surface of the second wafer and surrounding the thin film resonator unit, wherein a portion of the bonding pad covers the seal ring structure.
14. The wafer-level package structure of the thin film resonator of claim 12, wherein the redistribution layer comprises an inductor structure.
15. The wafer-level package structure of the thin film resonator according to claim 12, further comprising an insulating layer on a surface of the redistribution layer on a side away from the second wafer, wherein the insulating layer includes at least one opening structure that exposes a portion of the redistribution layer.
16. The wafer-level package structure of the thin film resonator of claim 11, further comprising a second protection layer on the second surface of the first wafer.
CN202110145337.1A 2021-02-02 2021-02-02 Wafer-level packaging method and structure of thin-film resonator Active CN112967940B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110145337.1A CN112967940B (en) 2021-02-02 2021-02-02 Wafer-level packaging method and structure of thin-film resonator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110145337.1A CN112967940B (en) 2021-02-02 2021-02-02 Wafer-level packaging method and structure of thin-film resonator

Publications (2)

Publication Number Publication Date
CN112967940A true CN112967940A (en) 2021-06-15
CN112967940B CN112967940B (en) 2022-06-24

Family

ID=76272405

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110145337.1A Active CN112967940B (en) 2021-02-02 2021-02-02 Wafer-level packaging method and structure of thin-film resonator

Country Status (1)

Country Link
CN (1) CN112967940B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594051A (en) * 2021-07-09 2021-11-02 苏州汉天下电子有限公司 Semiconductor packaging method
CN113808922A (en) * 2021-09-14 2021-12-17 苏州汉天下电子有限公司 Pattern etching method of wafer, thin film resonator assembly and preparation method

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383299A (en) * 2007-09-05 2009-03-11 精材科技股份有限公司 Wafer level package of electronic element and manufacturing method thereof
CN103489846A (en) * 2012-06-11 2014-01-01 精材科技股份有限公司 Chip package and method for forming the same
CN104218022A (en) * 2011-02-10 2014-12-17 精材科技股份有限公司 Chip package and fabrication method thereof
CN106373971A (en) * 2015-07-23 2017-02-01 精材科技股份有限公司 Chip scale sensing chip package and a manufacturing method thereof
JP2018067902A (en) * 2016-10-17 2018-04-26 ウィン セミコンダクターズ コーポレーション Bulk acoustic wave resonator with mass adjustment structure and bulk acoustic wave filter
CN109273406A (en) * 2018-09-05 2019-01-25 苏州科阳光电科技有限公司 Packaging method of wafer-level chip
CN110855264A (en) * 2019-12-06 2020-02-28 北京汉天下微电子有限公司 Resonator packaging structure and manufacturing method thereof
CN111510099A (en) * 2020-04-24 2020-08-07 杭州见闻录科技有限公司 Film bulk acoustic wave filter and wafer level packaging method thereof
CN212292788U (en) * 2020-05-20 2021-01-05 华景科技无锡有限公司 Wafer-level packaging structure of micro-electro-mechanical system microphone

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101383299A (en) * 2007-09-05 2009-03-11 精材科技股份有限公司 Wafer level package of electronic element and manufacturing method thereof
CN104218022A (en) * 2011-02-10 2014-12-17 精材科技股份有限公司 Chip package and fabrication method thereof
CN103489846A (en) * 2012-06-11 2014-01-01 精材科技股份有限公司 Chip package and method for forming the same
CN106373971A (en) * 2015-07-23 2017-02-01 精材科技股份有限公司 Chip scale sensing chip package and a manufacturing method thereof
JP2018067902A (en) * 2016-10-17 2018-04-26 ウィン セミコンダクターズ コーポレーション Bulk acoustic wave resonator with mass adjustment structure and bulk acoustic wave filter
CN109273406A (en) * 2018-09-05 2019-01-25 苏州科阳光电科技有限公司 Packaging method of wafer-level chip
CN110855264A (en) * 2019-12-06 2020-02-28 北京汉天下微电子有限公司 Resonator packaging structure and manufacturing method thereof
CN111510099A (en) * 2020-04-24 2020-08-07 杭州见闻录科技有限公司 Film bulk acoustic wave filter and wafer level packaging method thereof
CN212292788U (en) * 2020-05-20 2021-01-05 华景科技无锡有限公司 Wafer-level packaging structure of micro-electro-mechanical system microphone

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113594051A (en) * 2021-07-09 2021-11-02 苏州汉天下电子有限公司 Semiconductor packaging method
CN113594051B (en) * 2021-07-09 2024-02-20 苏州汉天下电子有限公司 Semiconductor packaging method
CN113808922A (en) * 2021-09-14 2021-12-17 苏州汉天下电子有限公司 Pattern etching method of wafer, thin film resonator assembly and preparation method
CN113808922B (en) * 2021-09-14 2024-03-19 苏州汉天下电子有限公司 Pattern etching method of wafer, thin film resonator component and preparation method

Also Published As

Publication number Publication date
CN112967940B (en) 2022-06-24

Similar Documents

Publication Publication Date Title
US11870410B2 (en) Packaging method and packaging structure of film bulk acoustic resonator
US20050104204A1 (en) Wafer-level package and its manufacturing method
US9362139B2 (en) Method of making a semiconductor device having a functional capping
CN112967940B (en) Wafer-level packaging method and structure of thin-film resonator
TWI582847B (en) Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
JP5861771B2 (en) Elastic wave device and manufacturing method thereof
US20090041270A1 (en) Mems Microphone And Method For Producing Said Microphone
US20210242855A1 (en) Packaging method and packaging structure of film bulk acoustic resonator
CN112039459B (en) Packaging method and packaging structure of bulk acoustic wave resonator
CN112117982B (en) Packaging structure and manufacturing method thereof
US20210184645A1 (en) Packaging module and packaging method of baw resonator
CN112039456A (en) Packaging method and packaging structure of bulk acoustic wave resonator
US8587106B2 (en) Wide band and radio frequency waveguide and hybrid integration in a silicon package
WO2022179479A1 (en) Mems device and manufacturing method therefor
WO2021135013A1 (en) Semiconductor structure having stacked units and manufacturing method therefor, and electronic device
CN114284234B (en) Packaging structure and manufacturing method for packaging structure
US7911043B2 (en) Wafer level device package with sealing line having electroconductive pattern and method of packaging the same
WO2022143968A1 (en) Mems device and method for fabrication thereof
JP4825111B2 (en) Method for manufacturing piezoelectric thin film device
CN113659954B (en) Bulk acoustic wave resonator, packaging method thereof and electronic equipment
CN115549624A (en) Electronic device and manufacturing method thereof
US7791183B1 (en) Universal low cost MEM package
KR20070012659A (en) Component with encapsulation suitable for wlp and production method
CN117639701A (en) Single crystal filter and manufacturing method thereof
CN117220627A (en) Preparation method of filter, filter and electronic equipment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant