CN212292788U - Wafer-level packaging structure of micro-electro-mechanical system microphone - Google Patents
Wafer-level packaging structure of micro-electro-mechanical system microphone Download PDFInfo
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- CN212292788U CN212292788U CN202020849780.8U CN202020849780U CN212292788U CN 212292788 U CN212292788 U CN 212292788U CN 202020849780 U CN202020849780 U CN 202020849780U CN 212292788 U CN212292788 U CN 212292788U
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Abstract
The utility model discloses a micro-electromechanical system microphone wafer level packaging structure, include: the independent chip comprises a first wafer and a second wafer; the first wafer comprises an application specific integrated circuit chip unit, and a plurality of first bonding pads are arranged on the first surface of the first wafer; the second wafer is positioned on the first wafer, the second wafer contains a micro-electro-mechanical system microphone chip unit, a third surface of the second wafer is provided with a plurality of second bonding pads, and a plurality of conductive through holes are formed in the second wafer; the first wafer is provided with a plurality of first through holes, a first insulating layer and a wiring layer; the first through hole exposes part or all of the first pad; a first insulating layer disposed on a sidewall of the first via hole; and a wiring layer disposed on the first insulating layer, the wiring layer being electrically connected to the first pad. The embodiment of the utility model provides a technical scheme has effectively reduced the product size.
Description
Technical Field
The embodiment of the utility model provides a relate to microphone technical field, especially relate to a micro-electromechanical system microphone wafer level packaging structure.
Background
A Micro-Electro-Mechanical System (MEMS) microphone is a microphone manufactured based on MEMS technology, converts a voice signal into an electrical signal, and is widely applied to mobile phones, computers, cameras, video cameras, and smart home products.
The micro electro mechanical system microphone packaging structure comprises a Circuit board, wherein a single micro electro mechanical system microphone chip and a single Application Specific Integrated Circuit (ASIC) chip are electrically connected through a gold wire and are arranged on the Circuit board, the micro electro mechanical system microphone chip transmits an electric signal converted from a sound signal to the ASIC chip, and the ASIC chip processes and amplifies the electric signal.
The current micro-electro-mechanical system microphone packaging structure cannot meet the requirement of product miniaturization.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a mems microphone wafer level package structure, which effectively reduces the size of the product.
The embodiment of the utility model provides a micro-electromechanical system microphone wafer level packaging structure, include:
independent chips comprising a first wafer and a second wafer;
the first wafer is provided with a first surface and a second surface opposite to the first surface, an application specific integrated circuit chip unit is contained in the first wafer, a plurality of first bonding pads are arranged on the first surface of the first wafer, and the first bonding pads are electrically connected with the application specific integrated circuit chip unit;
the second wafer is arranged on the first wafer, the second wafer is provided with a third surface and a fourth surface opposite to the third surface, a micro electro mechanical system microphone chip unit is arranged in the second wafer, a plurality of second bonding pads are arranged on the third surface of the second wafer and electrically connected with the micro electro mechanical system microphone chip unit, a plurality of conductive through holes are arranged in the second wafer, and one conductive through hole exposes part or all of one second bonding pad arranged on the third surface, and covers part or all of one first bonding pad;
the first wafer is provided with a plurality of first through holes, a first insulating layer and a wiring layer; the first through hole exposes part or all of the first bonding pad; the first insulating layer is arranged on the side wall of the first through hole; the wiring layer is arranged on the first insulating layer and is electrically connected with the first bonding pad.
In this embodiment, the independent chips include a first wafer and a second wafer; the first wafer comprises an integrated circuit chip unit, the second wafer comprises a micro electro mechanical system microphone chip unit, the second wafer is located on the first wafer, the micro electro mechanical system microphone chip unit is electrically connected with a second bonding pad, the micro electro mechanical system microphone chip unit transmits an electric signal converted by a sound signal to the second bonding pad, a conductive through hole transmits the electric signal of the second bonding pad to a first bonding pad arranged on the first surface of the first wafer, the first bonding pad transmits the electric signal to an application specific integrated circuit chip unit for signal processing and amplification, the processed electric signal is transmitted to the other first bonding pad by the application specific integrated circuit chip unit, and a wiring layer transmits the electric signal of the first bonding pad arranged on the first surface of the first wafer to the second surface of the first wafer so as to be electrically connected with an external circuit. Compared with the prior art, the packaging structure reduces the packaging size in the horizontal direction, and in the technical scheme in the embodiment, the electric connection between the micro-electromechanical system microphone chip unit and the integrated circuit chip unit is realized through the conductive through holes. In addition, according to the technical scheme of the embodiment, the first wafer and the second wafer are adopted to complete the packaging of the integrated circuit chip units and the micro electro mechanical system microphone chip units, which is called wafer-level packaging, wherein the first wafer can comprise a plurality of integrated circuit chip units and the second wafer can comprise a plurality of micro electro mechanical system microphone chip units, and the first wafer and the second wafer are cut to simultaneously complete the packaging of a plurality of independent chips.
Drawings
FIG. 1 is a schematic diagram of a MEMS microphone package according to the prior art;
fig. 2 is a schematic structural diagram of a mems microphone wafer level package structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another mems microphone wafer level package structure according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of a wafer level packaging method for a mems microphone according to an embodiment of the present invention;
fig. 5-15 are cross-sectional views of a mems microphone wafer level packaging method according to another embodiment of the present invention;
fig. 16 is a schematic flow chart illustrating another wafer level packaging method for a mems microphone according to an embodiment of the present invention;
fig. 17 is a schematic flowchart of another wafer level packaging method for mems microphones according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As mentioned in the background above, the current mems microphone package structure cannot meet the requirement of miniaturization of the product. The reason for this is that, referring to fig. 1, the existing mems microphone package structure includes an independent mems microphone chip 10, an independent asic chip 11, a housing 12 and a circuit board 13, where the independent mems microphone chip 10 and the independent asic chip 11 are electrically connected by gold wires 14 and are tiled on the circuit board 13, which results in a large size of the package structure in the horizontal direction, resulting in a large volume of the package structure and failing to meet the requirement for miniaturization of the product.
To the above technical problem, the embodiment of the utility model provides a following technical scheme:
fig. 2 is a schematic structural diagram of a wafer level package structure of a mems microphone according to an embodiment of the present invention. Referring to fig. 2, the mems microphone wafer level package structure includes: an individual chip 20, the individual chip 20 including a first wafer 21 and a second wafer 22; the first wafer 21 has a first surface 210A and a second surface 210B opposite to the first surface 210A, the first wafer 21 includes the asic chip units 21A therein, the first surface 210A of the first wafer 21 is provided with a plurality of first bonding pads 211, and the first bonding pads 211 are electrically connected to the asic chip units 21A; the second wafer 22 is located on the first wafer 21, wherein the second wafer 22 has a third surface 220A and a fourth surface 220B opposite to the third surface 220A, the second wafer 22 includes a mems microphone chip unit 22A, the third surface 220A of the second wafer 22 is provided with a plurality of second pads 221, the second pads 221 are electrically connected to the mems microphone chip unit 22A, the second wafer is provided with a plurality of conductive vias 222, a portion or all of a conductive via 222 is exposed from a second pad 221 located on the third surface 220A, and a portion or all of a first pad 211 is covered by a conductive via 222; the first wafer 21 is provided with a plurality of first via holes 212, a first insulating layer 213, and a wiring layer 214; the first via hole 212 exposes a part or all of the first pad 211; a first insulating layer 213 disposed on a sidewall of the first via hole 212; and a wiring layer 214 disposed on the first insulating layer 213, the wiring layer 214 being electrically connected to the first pad 211.
In this embodiment, the second bonding pad 221 is equivalent to the lead-out electrode of the mems microphone chip unit 22A, and the second bonding pad 221 is electrically connected to two electrodes of the mems microphone chip unit 22A.
The routing layer 214 may include one or more layers of metal. The manufacturing process of the wiring layer 214 may be, for example, a magnetron sputtering process. The mems microphone chip unit 22A transmits the electrical signal converted from the sound signal to the second pad 221, the conductive via 222 transmits the electrical signal of the second pad 221 to the first pad 211 disposed on the first surface 210A of the first wafer 21, the first pad 211 transmits the electrical signal to the asic chip unit 21A for signal processing and amplification, the processed electrical signal is transmitted from the asic chip unit 21A to another first pad 211, and the wiring layer 214 transmits the electrical signal of the first pad 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21 for electrical connection with an external circuit.
It should be noted that the multi-layer metal-formed wiring layer 214 can be better electrically connected to the first pad 211 than the one-layer metal-formed wiring layer 214. Illustratively, metal titanium is sputtered on the surface of the first insulating layer 213, and then a layer of metal copper is sputtered on the surface of the metal titanium by magnetron sputtering, thereby completing the fabrication of the wiring layer 214.
In the present embodiment, the individual chips 20 include a first wafer 21 and a second wafer 22; the first wafer 21 includes an integrated circuit chip unit 21A, the second wafer 22 includes a mems microphone chip unit 22A, the second wafer 22 is located on the first wafer 21, the mems microphone chip unit 22A is electrically connected to the second bonding pad 221, the mems microphone chip unit 22A transmits an electrical signal converted from a sound signal to the second bonding pad 221, the conductive via 222 transmits the electrical signal of the second bonding pad 221 to the first bonding pad 211 disposed on the first surface 210A of the first wafer 21, the first bonding pad 211 transmits the electrical signal to the asic chip unit 21A for signal processing and amplification, the processed electrical signal is transmitted from the asic chip unit 21A to another first bonding pad 211, the wiring layer 214 transfers the electrical signals of the first pads 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21 so as to be electrically connected to an external circuit. Compared with the packaging structure in the prior art, the independent micro electro mechanical system microphone chip 10 and the independent application specific integrated circuit chip 11 are tiled on the circuit board 14, so that the packaging size in the horizontal direction is reduced, and in the technical scheme in the embodiment, the electric connection between the micro electro mechanical system microphone chip unit 22A and the integrated circuit chip unit 21A is realized through the conductive through hole 222. In addition, in the technical scheme of this embodiment, the first wafer 21 and the second wafer 22 are used to complete the packaging of the integrated circuit chip unit 21A and the mems microphone chip unit 22A, which is referred to as wafer level packaging, wherein the first wafer 21 may include a plurality of integrated circuit chip units 21A and the second wafer may include a plurality of mems microphone chip units 22A, and the first wafer 21 and the second wafer 22 are cut to simultaneously complete the packaging of a plurality of independent chips, which greatly improves the packaging efficiency compared with the prior art in which the independent mems microphone chip 10 and the independent asic chip 11 are tiled on the circuit board 14.
In the above technical solution, the wiring layer 214 transmits the electrical signal of the first pad 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21 so as to be electrically connected to the external circuit. In actual conditions, the electric connection is realized with external circuit contact to partial wiring layer 214, in order to protect the part in the wiring layer 214 that does not contact with external circuit, the embodiment of the utility model provides a following technical scheme: fig. 3 is a schematic structural diagram of another mems microphone wafer level package structure according to an embodiment of the present invention. Referring to fig. 3, the first wafer 21 is further provided with a second insulating layer 215 disposed on the wiring layer 214, the second insulating layer 215 includes at least one first opening structure 215A, and each first opening structure 215A exposes a portion of the wiring layer 214.
Specifically, the second insulating layer 215 includes at least one first opening structure 215A, and each first opening structure 215A exposes a portion of the wiring layer 214 to be electrically connected to an external circuit contact, so as to protect a portion of the wiring layer 214 that is not in contact with the external circuit.
Optionally, referring to fig. 3, the mems microphone wafer level package structure further includes a cover plate 30 disposed on the third surface 220A of the second wafer 22, the cover plate 30 includes a second opening structure 31, and the second opening structure 31 exposes the mems microphone chip unit 22A.
Specifically, sound enters from the second opening structure 31, and the mems microphone chip unit 22A converts the sound signal into an electrical signal, and transmits the electrical signal to the integrated circuit chip unit 21A in the first wafer 21 through the second pad 221 and the conductive via 222. The wiring layer 214 transmits the electrical signals of the first pads 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21, and thus, the electrical connection with the external circuit is achieved.
In the above solution, the conductive vias 222 transmit the electrical signals of the second pads 221 to the integrated circuit chip units 21A in the first wafer 21. Alternatively, referring to fig. 3, the conductive via 222 includes: a second via hole 222A disposed in the second wafer 22, a second via hole 222A exposing a second pad 221 partially or entirely located on the third surface 220A; a third insulating layer 222B provided on a surface of a sidewall of the second via hole 222A; the conductive pillar 222C is disposed on the surface of the third insulating layer 222B away from the side wall of the second via hole 222A, and the second pad 221 covers the conductive pillar.
Specifically, the third insulating layer 222B insulates the conductive post 222C from the second wafer 22. The conductive pillar 222C, the third insulating layer 222B, and the second wafer 22 form an equivalent capacitor, wherein the second wafer 22 is made of a high-resistance silicon material, so that the capacitance of the equivalent capacitor is relatively low, and the interference to the mems microphone chip unit 22A is relatively small. The conductive pillar 222C is electrically connected to the second pad 221, so that the conductive via 222 transmits the electrical signal of the second pad 221 to the ic chip unit 21A in the first wafer 21 through the first pad 211, and further to the wiring layer 214 through the first pad 211. The wiring layer 214 transmits the electrical signal of the first pad 211 to the second surface 210B of the first wafer 21, and thus, the electrical connection with the external circuit is achieved.
Optionally, referring to fig. 3, the second wafer 22 further includes a groove 22B disposed corresponding to the mems microphone chip unit 22A, and the mems microphone chip unit 22A is suspended above the groove 22B, wherein the mems microphone chip unit 22A is close to the third surface 220A, and the groove 22B is located on the fourth surface 220B.
The sound signal can be propagated in the groove 22B, and the groove 22B can reduce the damping of the air discharge in the mems microphone chip unit 22A, thereby improving the signal-to-noise ratio of the mems microphone chip unit 22A. The larger the volume of the groove 22B, the higher the signal-to-noise ratio of the mems microphone chip unit 22A, and the better the product performance.
In the above technical solution, the mems microphone chip unit 22A converts the sound signal into an electrical signal, and transmits the electrical signal to the first pad 211 through the through hole 222, and the wiring layer 214 transmits the electrical signal to the second surface 210B of the first wafer 21, so as to achieve electrical connection with an external circuit. The mems microphone chip unit 22A may be a condenser microphone or a piezoelectric microphone. When the mems microphone chip unit 22A is of a condenser microphone type, the mems microphone chip unit 22A includes a diaphragm and a back plate, the diaphragm is electrically connected to one second bonding pad 221, and the back plate is electrically connected to another second bonding pad 221.
The specific principle is as follows: the capacitance microphone chip is used for changing the distance between the vibrating diaphragm and the back plate according to the received sound signal, the capacitance values of the vibrating diaphragm and the back plate are changed, and a corresponding electric signal is output between the vibrating diaphragm and the back plate.
When the mems microphone chip unit 22A is a piezoelectric microphone, the mems microphone chip unit includes a piezoelectric module, the piezoelectric module includes a first electrode, a piezoelectric film, and a second electrode stacked in sequence from bottom to top, the first electrode is electrically connected to one second pad 221, and the second electrode is electrically connected to another second pad 221.
The specific principle is as follows: the piezoelectric film is used for generating deformation according to the received sound signal, and charges with different signs appear on the first surface and the second surface, so that a potential difference is formed between the first electrode and the second electrode and serves as a corresponding electric signal. The stronger the sound signal, the larger the voltage value corresponding to the electric signal.
The mems microphone chip unit 22A converts the sound signal into an electrical signal, and transmits the electrical signal to the integrated circuit chip unit 21A in the first wafer 21 through the second pad 221 and the conductive via 222. The wiring layer 214 transmits the electrical signals of the first pads 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21, and thus, the electrical connection with the external circuit is achieved.
Based on the same conception, the embodiment of the utility model also provides a micro-electromechanical system microphone wafer level packaging method. FIG. 4 provides a flow chart of a wafer level packaging method for a MEMS microphone. Fig. 5-15 are cross-sectional views corresponding to steps of a wafer level packaging method for a mems microphone according to another embodiment of the present invention. Referring to fig. 4, the method includes the steps of:
Referring to fig. 5, a first wafer 21 is prepared, the first wafer 21 has a first surface 210A and a second surface 210B opposite to the first surface 210A, the first wafer 21 includes a plurality of asic chip units 21A, the first surface 210A of the first wafer 21 is provided with a plurality of first bonding pads 211, and the first bonding pads 211 are electrically connected to the asic chip units 21A. The asic chip unit 21A is a circuit structure formed by forming a plurality of layers of electronic components having specific functions on the first wafer 21 by, for example, multiple photolithography, ion implantation, etching, and evaporation processes. The first pad 211 corresponds to the extraction electrode of the asic chip unit 21A.
And 120, preparing a second wafer, wherein the second wafer is provided with a third surface and a fourth surface opposite to the third surface, the second wafer is internally provided with a plurality of micro electro mechanical system microphone chip units, the third surface of the second wafer is provided with a plurality of second bonding pads, the second bonding pads are electrically connected with the micro electro mechanical system microphone chip units, a plurality of conductive through holes are arranged in the second wafer, and part or all of the second bonding pads on the third surface are exposed by one conductive through hole.
Referring to fig. 6, a second wafer 22 is prepared, where the second wafer 22 has a third surface 220A and a fourth surface 220B opposite to the third surface 220A, the second wafer 22 includes a plurality of mems microphone chip units 22A, the third surface 220A of the second wafer 22 is provided with a plurality of second pads 221, the second pads 221 are electrically connected to the mems microphone chip units 22A, the second wafer 22 is provided with a plurality of conductive vias 222, and a portion or all of the second pads 221 on the third surface 220A are exposed by one of the conductive vias 222. The second bonding pad 221 corresponds to an extraction electrode of the mems microphone chip unit 22A, and the second bonding pad 221 is electrically connected to two electrodes of the mems microphone chip unit 22A.
Referring to fig. 7, the second wafer 22 is disposed on the first wafer 21, wherein the fourth surface 220B of the second wafer 22 is disposed on the first surface 210A of the first wafer 21, and a conductive via 222 covers a part or all of a first pad 211.
Optionally, the step 140 of forming at least one first via in the first wafer, before the first via exposes part or all of the first pad, further includes: and forming a protective film layer on the third surface of the second wafer.
Referring to fig. 8, a protective film 23 is formed over the third surface 220A of the second wafer 22. Alternatively, the protective film 23 is formed over the third surface 220A of the second wafer 22 through a bonding process. The layer between the protective film 23 and the third surface 220A of the second wafer 22 is a bonding layer. The protective film 23 is used to improve the mechanical performance of the device and prevent subsequent operations performed on the first wafer 21 from damaging the first wafer 21 and the second wafer 22.
At least one first via is formed in the first wafer, and the first via exposes a portion or all of the first pad, step 140.
Referring to fig. 9, at least one first via hole 212 is formed in the first wafer 21, and the first via hole 212 exposes a part or all of the first pad 211. The formation of the first via 212 may be accomplished by an etching process.
Optionally, before forming at least one first via 212 on the first wafer 21, and exposing part or all of the first pad 211 through the first via 212, the first wafer 21 may be thinned. The thinning operation may reduce the difficulty of forming the first via 212.
Referring to fig. 10, a first insulating layer 213 is formed on sidewalls of the first via hole 212. As an example of the first insulating layer 213, silicon oxide, silicon nitride, or the like can be used.
A wiring layer is formed on the first insulating layer, the wiring layer being electrically connected to the first pad, step 160.
Referring to fig. 11, a wiring layer 214 is formed on the first insulating layer 213, the wiring layer 214 being electrically connected to the first pad 211. Specifically, the mems microphone chip unit 22A transmits the electrical signal converted from the sound signal to the second pad 221, the conductive via 222 transmits the electrical signal of the second pad 221 to the first pad 211 disposed on the first surface 210A of the first wafer 21, the first pad 211 transmits the electrical signal to the asic chip unit 21A for signal processing and amplification, the processed electrical signal is transmitted from the asic chip unit 21A to another first pad 211, and the wiring layer 214 transmits the electrical signal of the first pad 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21 for electrical connection with an external circuit. It should be noted that the multi-layer metal-formed wiring layer 214 can be better electrically connected to the first pad 211 than the one-layer metal-formed wiring layer 214. Illustratively, metal titanium is sputtered on the surface of the first insulating layer 213, and then a layer of metal copper is sputtered on the surface of the metal titanium by magnetron sputtering, thereby completing the fabrication of the wiring layer 214.
Optionally, after forming the wiring layer 214 on the first insulating layer 213, the wiring layer 214 is electrically connected to the first pad 211, and further includes: referring to fig. 12, a second insulating layer 215 is formed on the wiring layer 214, the second insulating layer 215 including at least one first opening structure 215A, each first opening structure 215A exposing a portion of the wiring layer 214. The second insulating layer 215 includes at least one first opening structure 215A, and each first opening structure 215A exposes a portion of the wiring layer 214 to be electrically connected to an external circuit contact, so as to protect a portion of the wiring layer 214 not contacted to the external circuit. The second insulating layer 215 may be silicon oxide or silicon nitride.
Optionally, forming a second insulating layer 215 on the wiring layer 214, where the second insulating layer 215 includes at least one first opening structure 215A, and after exposing a portion of the wiring layer 214, each first opening structure 215A further includes:
referring to fig. 13, the protective film layer 23 is removed.
Referring to fig. 14, a cover plate 30 is formed over the third surface 220A of the second wafer 22, the cover plate 30 includes a plurality of second opening structures 31, and each second opening structure 31 exposes a mems microphone chip unit 22A. Specifically, sound enters from the second opening structure 31, and the mems microphone chip unit 22A converts the sound signal into an electrical signal, and transmits the electrical signal to the integrated circuit chip unit 21A in the first wafer 21 through the second pad 221 and the conductive via 222. The wiring layer 214 transmits the electrical signals of the first pads 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21, and thus, the electrical connection with the external circuit is achieved. The cap plate 30 may be formed over the third surface 220A of the second wafer 22 through a bonding process.
Referring to fig. 15, a plurality of mems microphone chip units and a plurality of asic chip units are cut along the first via 212 to form a plurality of individual chips 20, each individual chip 20 including a mems microphone chip unit 22A and an asic chip unit 21A.
In the present embodiment, the individual chips 20 include a first wafer 21 and a second wafer 22; the first wafer 21 includes an integrated circuit chip unit 21A, the second wafer 22 includes a mems microphone chip unit 22A, the second wafer 22 is located on the first wafer 21, the mems microphone chip unit 22A is electrically connected to the second bonding pad 221, the mems microphone chip unit 22A transmits an electrical signal converted from a sound signal to the second bonding pad 221, the conductive via 222 transmits the electrical signal of the second bonding pad 221 to the first bonding pad 211 disposed on the first surface 210A of the first wafer 21, the first bonding pad 211 transmits the electrical signal to the asic chip unit 21A for signal processing and amplification, the processed electrical signal is transmitted from the asic chip unit 21A to another first bonding pad 211, the wiring layer 214 transfers the electrical signals of the first pads 211 disposed on the first surface 210A of the first wafer 21 to the second surface 210B of the first wafer 21 so as to be electrically connected to an external circuit. Compared with the packaging structure in the prior art, the independent micro electro mechanical system microphone chip 10 and the independent application specific integrated circuit chip 11 are tiled on the circuit board 14, so that the packaging size in the horizontal direction is reduced, and in the technical scheme in the embodiment, the electric connection between the micro electro mechanical system microphone chip unit 22A and the integrated circuit chip unit 21A is realized through the conductive through hole 222. In addition, in the technical scheme of this embodiment, the first wafer 21 and the second wafer 22 are used to complete the packaging of the integrated circuit chip unit 21A and the mems microphone chip unit 22A, which is referred to as wafer level packaging, wherein the first wafer 21 may include a plurality of integrated circuit chip units 21A and the second wafer may include a plurality of mems microphone chip units 22A, and the first wafer 21 and the second wafer 22 are cut to simultaneously complete the packaging of a plurality of independent chips, which greatly improves the packaging efficiency compared with the prior art in which the independent mems microphone chip 10 and the independent asic chip 11 are tiled on the circuit board 14.
Fig. 16 is a schematic flow chart illustrating another wafer level packaging method for a mems microphone according to an embodiment of the present invention. Alternatively, referring to fig. 16, the step 120 of preparing the second wafer includes:
Taking fig. 3 as an example for illustration, a second wafer 22 is provided, and the second wafer 22 has a third surface 220A and a fourth surface 220B opposite to the third surface.
Taking fig. 3 as an example, a plurality of grooves 22B and a plurality of mems microphone chip units 22A are formed in the second wafer 22 by using a mems process, and one mems microphone chip unit 22A is suspended above one of the grooves 22B, wherein the mems microphone chip unit 22A is close to the third surface 220A, and the groove 22B is located on the fourth surface 220B. Specifically, the sound signal can be propagated in the groove 22B, and the groove 22B can reduce the damping of the air exhaust in the mems microphone chip unit 22A, thereby improving the signal-to-noise ratio of the mems microphone chip unit 22A. The larger the volume of the groove 22B, the higher the signal-to-noise ratio of the mems microphone chip unit 22A, and the better the product performance.
Taking fig. 3 as an example for illustration, a plurality of second bonding pads 221 are formed on the third surface 220A of the second wafer 22, and the second bonding pads 221 are electrically connected to the mems microphone chip unit 22A.
Taking fig. 3 as an example, a plurality of conductive vias 222 are formed on the second wafer 22, and a conductive via 222 exposes a second pad 221 located on the third surface 220A partially or completely.
Fig. 17 is a schematic flowchart of another wafer level packaging method for a mems microphone according to an embodiment of the present invention. Optionally, referring to fig. 17, step 1204 forms a plurality of conductive vias in the second wafer, a conductive via exposing a second pad located partially or entirely on the third surface comprising:
Taking fig. 3 as an example, a plurality of second through holes 222A are formed in the second wafer, and a second through hole 222A exposes a second pad 221 partially or completely located on the third surface 220A.
Taking fig. 3 as an example, a third insulating layer 222B is formed on the sidewall of the second via hole 222A.
Taking fig. 3 as an example, the conductive pillar 222C is formed on the surface of the third insulating layer 222B on the side away from the sidewall of the second via hole 222A, and the second pad 221 covers the conductive pillar 222C.
Specifically, the third insulating layer 222B insulates the conductive post 222C from the second wafer 22. The conductive pillar 222C, the third insulating layer 222B, and the second wafer 22 form an equivalent capacitor, wherein the second wafer 22 is made of a high-resistance silicon material, so that the capacitance of the equivalent capacitor is relatively low, and the interference to the mems microphone chip unit 22A is relatively small. The conductive pillar 222C is electrically connected to the second pad 221, so that the conductive via 222 transmits the electrical signal of the second pad 221 to the ic chip unit 21A in the first wafer 21 through the first pad 211, and further to the wiring layer 214 through the first pad 211. The wiring layer 214 transmits the electrical signal of the first pad 211 to the second surface 210B of the first wafer 21, and thus, the electrical connection with the external circuit is achieved.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (6)
1. A wafer level package structure of a micro electro mechanical system microphone, comprising:
independent chips comprising a first wafer and a second wafer;
the first wafer is provided with a first surface and a second surface opposite to the first surface, an application specific integrated circuit chip unit is contained in the first wafer, a plurality of first bonding pads are arranged on the first surface of the first wafer, and the first bonding pads are electrically connected with the application specific integrated circuit chip unit;
the second wafer is arranged on the first wafer, the second wafer is provided with a third surface and a fourth surface opposite to the third surface, a micro electro mechanical system microphone chip unit is arranged in the second wafer, a plurality of second bonding pads are arranged on the third surface of the second wafer and electrically connected with the micro electro mechanical system microphone chip unit, a plurality of conductive through holes are arranged in the second wafer, and one conductive through hole exposes part or all of one second bonding pad arranged on the third surface, and covers part or all of one first bonding pad;
the first wafer is provided with a plurality of first through holes, a first insulating layer and a wiring layer; the first through hole exposes part or all of the first bonding pad; the first insulating layer is arranged on the side wall of the first through hole; the wiring layer is arranged on the first insulating layer and is electrically connected with the first bonding pad.
2. The wafer level package structure of claim 1, wherein the first wafer further comprises a second insulating layer disposed on the wiring layer, the second insulating layer comprising at least one first opening structure, each of the first opening structures exposing a portion of the wiring layer.
3. The mems microphone wafer level package structure of claim 1, further comprising a cover plate disposed over the third surface of the second wafer, the cover plate comprising a second opening structure that exposes the mems microphone chip unit.
4. The mems microphone wafer level package structure of claim 1, wherein the conductive via comprises:
the second through hole is arranged in the second wafer, and part or all of the second through hole exposes a second bonding pad positioned on the third surface;
a third insulating layer disposed on a surface of a sidewall of the second via hole;
and the conductive column is arranged on the surface of one side of the side wall, far away from the second through hole, of the third insulating layer, and the second bonding pad covers the conductive column.
5. The mems microphone wafer level package structure of claim 1, wherein the second wafer further comprises a recess corresponding to the mems microphone die units, and one of the mems microphone die units is suspended above one of the recesses, wherein the mems microphone die units are close to the third surface and the recess is located on the fourth surface.
6. The mems microphone wafer level package structure of claim 1, wherein the mems microphone chip unit comprises a diaphragm electrically connected to one of the second bonding pads and a back plate electrically connected to the other of the second bonding pads;
alternatively, the first and second electrodes may be,
the micro electro mechanical system microphone chip unit comprises a piezoelectric module, wherein the piezoelectric module comprises a first electrode, a piezoelectric film and a second electrode which are stacked from bottom to top in sequence, the first electrode is electrically connected with the second bonding pad, and the second electrode is electrically connected with the second bonding pad.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112967940A (en) * | 2021-02-02 | 2021-06-15 | 苏州汉天下电子有限公司 | Wafer-level packaging method and structure of thin-film resonator |
| CN113891200A (en) * | 2021-09-24 | 2022-01-04 | 青岛歌尔智能传感器有限公司 | Packaging structure of microphone |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112967940A (en) * | 2021-02-02 | 2021-06-15 | 苏州汉天下电子有限公司 | Wafer-level packaging method and structure of thin-film resonator |
| CN113891200A (en) * | 2021-09-24 | 2022-01-04 | 青岛歌尔智能传感器有限公司 | Packaging structure of microphone |
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