CN101383299A - Wafer level package of electronic element and manufacturing method thereof - Google Patents
Wafer level package of electronic element and manufacturing method thereof Download PDFInfo
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- CN101383299A CN101383299A CN 200710149797 CN200710149797A CN101383299A CN 101383299 A CN101383299 A CN 101383299A CN 200710149797 CN200710149797 CN 200710149797 CN 200710149797 A CN200710149797 A CN 200710149797A CN 101383299 A CN101383299 A CN 101383299A
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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Abstract
The invention provides a wafer grade encapsulating device of an electronic component and a manufacturing method thereof. The manufacturing method of the wafer grade encapsulating device of the electronic component comprises the following steps: a semiconductor wafer is supplied and comprises a plurality of electronic component chips, the semiconductor wafer and a bearing substrate are bonded, the back surface of the semiconductor wafer is thinned and is etched to form a first groove, an insulating layer is deposited on the back surface of the semiconductor wafer in an adaptability mode, an insulating layer which is arranged at the bottom of the first groove is etched to form a second groove, the insulating layer which is arranged at the bottom of the groove and an interlaminar dielectric layer are orderly removed, the partial surfaces of a pair of contact cushions are exposed, and a conducting layer is deposited on the back surface of the semiconductor wafer in an adaptability mode; after the semiconductor wafer is patterned, the semiconductor wafer and the contact cushions form an S-shaped connecting line, and an external conducting wire and a welding bump are formed. Because the conducting layer and the contact cushions of the invention have a large contact area, the electric conductivity and the adhesive property of a T-shaped connecting line are improved, and the technical qualification rate is increased.
Description
Technical field
The present invention relates to the wafer-level packaging of electronic component, particularly a kind of wafer-level packaging of cmos image sensor and manufacture method thereof.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor image sensor (CMOS image sensor) has been widely used in many applications, and for example static digital camera (digital still camera, DSC).Above-mentioned application is mainly utilized active pixel array or image sensing unit (image sensor cell) array, comprises the optical diode element, converts numerical data to the image luminous energy with incident.
The wafer-level package of conditional electronic element (chip scale package is called for short CSP) is designed for chip upside-down mounting type and engages (flip chip bonding) on the carrying substrate, for example package substrate, module substrate or printed circuit board (PCB) (PCB).When carrying out flip-chip bond (flip chip bonding) processing step, need soldering projection, weld stud or other terminals on the encapsulation object are engaged on the coupling contact mat that carries on the substrate.Terminal contact behind the joint can provide the encapsulation object and carry the physical connection between the substrate and be electrically connected.
In order to solve the contact mat engagement problems of known technology, industry develops a kind of technology of shell-type semiconductor element wafer-level packaging.For example, No. 6,792,480, United States Patent (USP) US and disclose the technology that discloses a kind of wafer-level packaging of semiconductor element for US2001/0018236 number in early days.Provide T shape line between the contacting of substrate contact mat and crystal grain.Figure 1A shows the generalized section of the cmos image sensor of traditional wafer scale assembling.Figure 1B shows the partial enlarged drawing of the cmos image sensor of Figure 1A.See also Figure 1A, the cmos image sensing element packaging body comprises the bearing structure of transparent substrates 24 as wafer-level package, bonding cmos image sensor crystal grain 12 on it, and it comprises the sensing region with microlens array 10, as the image sensing face.Distance piece 26 is arranged between transparent substrates 24 and the cmos image sensor crystal grain 12, to define hole 30. Adhesive layer 14,28 is formed on the substrate, with 12 sealings of cmos image sensor crystal grain.Optical texture 16 is arranged on the adhesive layer 14, to strengthen this crystal grain class encapsulation structure.T shape line comprises conductor structure 18, and an end of conductor structure 18 connects contact mat 22, and a plurality of terminals that extend on this wafer-level package from the crystal grain circuit contact.Ball grid array (ball grid array) 20 is formed in the terminal contact of crystal grain level encapsulation.
See also Figure 1B,, easily cause and the reliability issues generation such as peel off because conductor structure 18 and the contact-making surface 18a between the contact mat 22 of T shape line is little.
In view of this, industry needs a kind of integrated circuit component package design, improves conductor structure and the caking property between the contact mat and the conductivity of T shape line.
Summary of the invention
The invention provides a kind of wafer-level packaging and manufacture method thereof of electronic component.Contact mat part and conductive layer contact area partly in T shape line form step structure, improve the caking property and the conductivity of improving T shape line of contact mat and conductive layer.
The invention provides a kind of manufacture method of wafer-level packaging of electronic component, comprising: semiconductor crystal wafer is provided, comprises a plurality of electronic component chips on it; This semiconductor crystal wafer and carrying substrate and the back side of this semiconductor crystal wafer of thinning bond; The back side of this semiconductor crystal wafer of etching is to form first groove; Compliance ground depositing insulating layer is in the back side of this semiconductor crystal wafer; The insulating barrier of this channel bottom of etching is to form second groove; Remove this insulating barrier and the interlayer dielectric layer (ILD) of this first channel bottom of layer in regular turn, and expose the part surface of a pair of contact mat; Compliance ground deposits a conductive layer in the back side of this semiconductor crystal wafer, and with behind its patterning, forms S shape line with this contact mat; And formation outer lead and soldering projection.
According to the manufacture method of the wafer-level packaging of electronic component of the present invention, wherein this electronic component chip comprises the complement metal oxide semiconductor image sensor.
According to the manufacture method of the wafer-level packaging of electronic component of the present invention, wherein this carrying substrate is a transparent substrates, comprises eyeglass level glass or quartz.
Manufacture method according to the wafer-level packaging of electronic component of the present invention wherein forms this insulating barrier step and comprises spraying process, sputtering method, print process, rubbing method or spin-coating method.
According to the manufacture method of the wafer-level packaging of electronic component of the present invention, wherein the material of this insulating barrier comprises epoxy resin, pi, resin, silica, metal oxide or silicon nitride.
Manufacture method according to the wafer-level packaging of electronic component of the present invention, after forming this insulating barrier step, also comprise and form patterned mask layer on this insulating barrier, and expose this insulating barrier of this channel bottom, utilize this mask layer to stop again, this insulating barrier of this channel bottom of etching and this ILD layer in regular turn are until spacer structure, to form this second groove.
According to the manufacture method of the wafer-level packaging of electronic component of the present invention, wherein the part surface of this contact mat that exposes comprises vertical component and horizontal component.
The present invention provides a kind of wafer-level packaging of electronic component in addition, comprise: semiconductor crystal wafer, have a plurality of electronic component chips, with carrying substrate subtend bonding, wherein each electronic component chip comprises that a pair of contact mat and interlayer dielectric layer cover this electronic component chip, expose the vertical component and the horizontal component of this contact mat; And conductive layer, being arranged at outside the wafer-level packaging of this electronic component, this vertical component and this horizontal component that contact this contact mat in compliance ground exposes constitute S shape and are electrically connected; Wherein this S shape is electrically connected a plurality of contact terminals at the wafer-level packaging back side that extends to this electronic component.
According to the wafer-level packaging of electronic component of the present invention, wherein this electronic component chip comprises the complement metal oxide semiconductor image sensing apparatus.
According to the wafer-level packaging of electronic component of the present invention, wherein this carrying substrate is a transparent substrates, comprises eyeglass level glass or quartz.
Utilization of the present invention removes the insulating barrier of channel bottom in regular turn and removes the step of interlayer dielectric layer (ILD), the vertical plane and the horizontal plane that expose contact mat, the conductive layer that causes follow-up formation is lined with bigger contact area with contacting, and improves the conductivity and the caking property of T shape line, promotes the technology qualification rate.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Figure 1A shows the generalized section of the cmos image sensor of traditional wafer scale assembling;
Figure 1B shows the partial enlarged drawing of the cmos image sensor of Figure 1A;
Fig. 2 shows the flow chart according to the manufacture method of the wafer-level packaging of the electronic component of the embodiment of the invention; And
The generalized section of each step in the manufacture method of the wafer-level packaging of the cmos image sensor of Fig. 3 A-Fig. 3 I demonstration embodiment of the invention.
Wherein, description of reference numerals is as follows:
Known portions (Figure 1A～Figure
1B)
10～microlens array; 12～cmos image sensor crystal grain;
14,28～adhesive layer; 16～optical texture;
18～conductor structure; 18a～contact-making surface;
20～ball grid array; 22～contact mat;
24～transparent substrates; 26～distance piece;
30～hole.
The present invention's part (Fig. 2～Fig. 3 I)
S200-S290～processing step;
300a, 300b～cmos image sensor packaging body;
305～the first grooves;
306～the second grooves;
310～semiconductor crystal wafer;
Semiconductor crystal wafer after 310 '～thinning;
320～transparent substrates;
325～distance piece;
330～hole;
335a, 335b～contact mat;
340～interlayer dielectric layer;
350a, 350b～microlens array;
360～insulating barrier;
370～conductive layer;
380～ball grid array;
V～vertical contact portion;
H～horizontal contact section branch.
Embodiment
Below describe and be accompanied by the example of description of drawings in detail with each embodiment, as reference frame of the present invention.In accompanying drawing or specification description, similar or identical part is all used identical figure number.And in the accompanying drawings, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover, the part of each element will be to describe explanation respectively in the accompanying drawing, it should be noted that, element not shown in the figures or describe, for having the form of knowing usually known to the knowledgeable in the affiliated technical field, in addition, only for disclosing the ad hoc fashion that the present invention uses, it is not in order to limit the present invention to certain embodiments.
Fig. 2 shows the flow chart according to the manufacture method of the wafer-level packaging of the electronic component of the embodiment of the invention.The semiconductor crystal wafer (step S200) of tool integrated circuit component at first, is provided.A plurality of electronic components, for example cmos image sensor and corresponding lens arrangement are formed on the semiconductor crystal wafer.Then, in step S210, the semiconductor crystal wafer subtend is bonded on the package substrate.In step S220, with the back side thinning of semiconductor crystal wafer, in order to more frivolous packaging body.Then, the back etched of semiconductor crystal wafer is formed first groove (S230), expose interlayer dielectric (ILD) layer of cmos image sensor element.Then, compliance ground depositing insulating layer is in the back side of semiconductor crystal wafer (S240).Then, see also step S250, remove the partial insulative layer and the ILD layer of channel bottom, forming second groove, and go deep into spacer structure.In step S260, remove the insulating barrier and the ILD layer of first channel bottom in regular turn, and expose the vertical plane and the horizontal plane of contact mat.Then, compliance ground depositing conducting layer, and with its patterning, to form S shape line (S270).Then, form outer lead and soldering projection and finish the wafer-level packaging (S280, S290) of electronic component.
The principal character of the embodiment of the invention and scheme are the steps of utilizing the insulating barrier that removes channel bottom in regular turn and removing interlayer dielectric layer (ILD), the vertical plane and the horizontal plane that expose contact mat, the conductive layer that causes follow-up formation is lined with bigger contact area with contacting, improve the conductivity and the caking property of T shape line, promote the technology qualification rate.
The generalized section of each step in the manufacture method of the wafer-level packaging of the cmos image sensor of Fig. 3 A-Fig. 3 I demonstration embodiment of the invention.See also Fig. 3 A, the bearing structure of transparent substrates 320 as wafer-level packaging is provided.The material of transparent substrates 320 comprises eyeglass level glass or quartz.Semiconductor crystal wafer 310 has formed the internal circuit of a plurality of cmos image sensors and microlens array 350a, the 350b of correspondence, as the image sensing face on it.The internal circuit of each cmos image sensor is electrically connected to contact mat 335a, 335b, and interlayer dielectric layer 340 is arranged on the internal circuit and microlens array 350a, 350b of cmos image sensor, as protective layer.
Then, with semiconductor crystal wafer 310 and transparent substrates 320 subtends bonding, distance piece 325 is set therebetween, what make the cmos image sensor exists hole 330 with transparent substrates 320.
See also Fig. 3 B, in order to meet advanced packaging technology and to form more frivolous packaging body, the back side thinning of semiconductor crystal wafer 310 is become preset thickness 310 '.The thinning step comprises technologies such as grinding, cmp and etch-back.
See also Fig. 3 C,, be etched into and have first groove 305, manifest ILD layer 340 in wherein with the 310 ' patterning of the semiconductor crystal wafer after the thinning.For example, with photoetching and etch process, with the back etched of semiconductor crystal wafer 310 ', till exposing ILD layer 340.Then, compliance ground depositing insulating layer 360 is in the back side of semiconductor crystal wafer 310 '.Insulating barrier 360 can be by chemical vapour deposition technique (CVD), physical vaporous deposition (PVD), sputtering method, print process, and ink-jet method, immersion plating, spraying process (spray coating) or method of spin coating form.The material of insulating barrier 360 comprises epoxy resin, pi, resin, silica, metal oxide or silicon nitride.
Then, see also Fig. 3 D, remove the partial insulative layer 360 and the ILD layer 340 of first groove, 305 bottoms, in the distance piece 325 that gos deep into part, to form second groove 306.For example form the mask layer (not shown) and expose insulating barrier 360 zones of desiring to remove, impose etching step again the insulating barrier 360 of groove 305 bottoms is removed with ILD layer 340.After forming the second ditch layer 306, mask layer is removed.
See also Fig. 3 E, then remove the insulating barrier 360 and ILD layer 340 of first groove, 305 base sections in regular turn, and expose contact mat 335a, 335b.It should be noted that the above-mentioned step that removes utilizes etching step to extend along the sidewall of first groove 306, till exposing contact mat 335a, 335b.For example, in second groove 306, contact mat 335a exposes vertical component v and horizontal component h, shown in Fig. 3 G.
See also Fig. 3 F, compliance ground depositing conducting layer 370, and with its patterning, to form the S shape line that constitutes by contact mat 335a, 335b and conductive layer 370.According to the embodiment of the invention, because in second groove 306, contact mat forms ledge structure and comprises that vertical contact portion v and horizontal contact section divide h, makes subsequent deposition conductive layer 370, between the preferable adherence of generation.Moreover, because the contact area of conductive layer 370 and contact mat 335a, 335b increases, make the conductivity of contact point be improved, shown in Fig. 3 G again.
See also Fig. 3 H, then form in the terminal contact that ball grid array 380 is formed at semiconductor packages.For example soldered ball mask layer (not shown) is formed in the encapsulation of crystal grain level, exposes the terminal contact area of reservation.Then, form welded ball array 380 on the terminal contact area that exposes.Then, the wafer level packaging structure along line of cut C cuts above-mentioned cmos image sensor makes it be separated into independently cmos image sensor packaging body 300a, 300b, shown in Fig. 3 I.In addition, the manufacture method of the wafer scale assembling structure of the embodiment of the invention still comprises other members and processing step, should be those skilled in the art and understands, and for asking simple and clear event, omits disclosing of correlative detail at this.
Though the foregoing description is the example explanation with the wafer-level package of cmos image sensor, right non-in order to limit the present invention, the wafer-level package of other electronic components comprises that integrated circuit component, photoelectric cell (optoelectronic device), microcomputer electric component (micro-electromechanical device) or surface acoustic wave element (surface acoustic wave device) all can be applicable in the embodiments of the invention.
Though the present invention with preferred embodiment openly as above; so it is not in order to limit scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can making a little variation and modification, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (10)
1. the manufacture method of the wafer-level packaging of an electronic component comprises:
Semiconductor crystal wafer is provided, comprises a plurality of electronic component chips on it;
Described semiconductor crystal wafer and carrying substrate and the back side of the described semiconductor crystal wafer of thinning bond;
The back side of the described semiconductor crystal wafer of etching is to form first groove;
Compliance ground depositing insulating layer is in the back side of described semiconductor crystal wafer;
The insulating barrier of the described channel bottom of etching is to form second groove;
Remove the described insulating barrier and the interlayer dielectric layer of the described channel bottom of layer in regular turn, and expose the part surface of a pair of contact mat;
Compliance ground depositing conducting layer is in the back side of described semiconductor crystal wafer, and with behind its patterning, forms S shape line with described contact mat; And
Form outer lead and soldering projection.
2. the manufacture method of the wafer-level packaging of electronic component as claimed in claim 1, wherein said electronic component chip comprises the complement metal oxide semiconductor image sensor.
3. the manufacture method of the wafer-level packaging of electronic component as claimed in claim 1, wherein said carrying substrate is a transparent substrates, comprises eyeglass level glass or quartz.
4. the manufacture method of the wafer-level packaging of electronic component as claimed in claim 1 wherein forms described insulating barrier step and comprises spraying process, sputtering method, print process, rubbing method or spin-coating method.
5. the manufacture method of the wafer-level packaging of electronic component as claimed in claim 1, the material of wherein said insulating barrier comprises epoxy resin, pi, resin, silica, metal oxide or silicon nitride.
6. the manufacture method of the wafer-level packaging of electronic component as claimed in claim 1, after forming described insulating barrier step, also comprise and form patterned mask layer on described insulating barrier, and expose the described insulating barrier of described channel bottom, utilize described mask layer to stop again, the described insulating barrier of the described channel bottom of etching and described interlayer dielectric layer in regular turn are until spacer structure, to form described second groove.
7. the manufacture method of the wafer-level packaging of electronic component as claimed in claim 1, the part surface of the wherein said contact mat that exposes comprises vertical component and horizontal component.
8. the wafer-level packaging of an electronic component comprises:
Semiconductor crystal wafer has a plurality of electronic component chips, and with carrying substrate subtend bonding, wherein each electronic component chip comprises that a pair of contact mat and interlayer dielectric layer cover described electronic component chip, expose the vertical component and the horizontal component of described contact mat; And
Conductive layer is arranged at outside the wafer-level packaging of described electronic component, and described vertical component and described horizontal component that contact described contact mat in compliance ground exposes constitute S shape and be electrically connected;
Wherein said S shape is electrically connected a plurality of contact terminals at the wafer-level packaging back side that extends to described electronic component.
9. the wafer-level packaging of electronic component as claimed in claim 8, wherein said electronic component chip comprises the complement metal oxide semiconductor image sensing apparatus.
10. the wafer-level packaging of electronic component as claimed in claim 8, wherein said carrying substrate is a transparent substrates, comprises eyeglass level glass or quartz.
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| CN200710149797.1A CN101383299B (en) | 2007-09-05 | 2007-09-05 | Wafer level package of electronic element and manufacturing method thereof |
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| CN200710149797.1A CN101383299B (en) | 2007-09-05 | 2007-09-05 | Wafer level package of electronic element and manufacturing method thereof |
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| CN 201010229517 Division CN101950729B (en) | 2007-09-05 | 2007-09-05 | Wafer level packaging of electronic component and manufacturing method thereof |
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| CN101383299A true CN101383299A (en) | 2009-03-11 |
| CN101383299B CN101383299B (en) | 2011-01-19 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544035A (en) * | 2010-11-24 | 2012-07-04 | 美商豪威科技股份有限公司 | Wafer dicing using scribe line etch |
| CN104037144B (en) * | 2013-03-07 | 2017-01-11 | 精材科技股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112967940A (en) * | 2021-02-02 | 2021-06-15 | 苏州汉天下电子有限公司 | Wafer-level packaging method and structure of thin-film resonator |
-
2007
- 2007-09-05 CN CN200710149797.1A patent/CN101383299B/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102544035A (en) * | 2010-11-24 | 2012-07-04 | 美商豪威科技股份有限公司 | Wafer dicing using scribe line etch |
| CN102544035B (en) * | 2010-11-24 | 2015-03-04 | 美商豪威科技股份有限公司 | Wafer dicing using scribe line etch |
| CN104037144B (en) * | 2013-03-07 | 2017-01-11 | 精材科技股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN112967940A (en) * | 2021-02-02 | 2021-06-15 | 苏州汉天下电子有限公司 | Wafer-level packaging method and structure of thin-film resonator |
| CN112967940B (en) * | 2021-02-02 | 2022-06-24 | 苏州汉天下电子有限公司 | Wafer-level packaging method and structure of thin-film resonator |
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| CN101383299B (en) | 2011-01-19 |
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