CN219180516U - Trench gate field effect transistor - Google Patents
Trench gate field effect transistor Download PDFInfo
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- CN219180516U CN219180516U CN202223597748.3U CN202223597748U CN219180516U CN 219180516 U CN219180516 U CN 219180516U CN 202223597748 U CN202223597748 U CN 202223597748U CN 219180516 U CN219180516 U CN 219180516U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The utility model relates to a trench gate field effect transistor, comprising a substrate; a first N-type doped region deposited on the substrate; a second N-type doped region deposited on the first N-type doped region, the second N-type doped region having a doping concentration greater than the doping concentration of the first N-type doped region; a first groove is formed at the side of the second N-type doped region, and a P-type doped region is filled in the first groove; a second groove is formed in the middle of the second N-type doped region, and polysilicon is filled in the second groove to form a gate region; according to the trench gate field effect transistor, the on resistance of silicon carbide is further reduced by the P-type doped region, the working capacity of the silicon carbide in a high-temperature environment is improved, and the short circuit prevention capacity is improved.
Description
Technical Field
The utility model relates to the technical field of silicon carbide, in particular to a trench gate field effect transistor.
Background
Silicon carbide is a novel wide-bandgap semiconductor material and has excellent physical, chemical and electrical properties, the breakdown electric field strength of the silicon carbide is 10 times that of the traditional silicon, and the thermal conductivity is three times that of the traditional silicon, so that a silicon carbide-based power device semiconductor has attractive force and application prospect in high-power and high-temperature application environments, however, pure silicon carbide is not conductive, special particles are required to be added to realize the conductivity of the silicon carbide, wherein the silicon carbide metal oxide field effect transistor has the characteristics of low on-resistance, high switching speed, high temperature resistance and the like, and in the prior art, the conduction internal resistance of the trench gate field effect transistor relative to a planar gate is reduced, but the conduction internal resistance of the trench gate field effect transistor is still insufficient in some application occasions, particularly in high-temperature operation, and the short circuit capability of the technology needs to be enhanced.
Disclosure of Invention
Therefore, the technical problem to be solved by the utility model is to overcome the problem of overlarge on-resistance of silicon carbide in the prior art, and further provide the trench gate field effect transistor which can further reduce the on-resistance of the silicon carbide and improve the capability of preventing short circuit of the silicon carbide.
In order to solve the technical problems, the utility model provides a trench gate field effect transistor, which comprises a substrate; a first N-type doped region deposited on the substrate; a second N-type doped region deposited on the first N-type doped region, the second N-type doped region having a doping concentration greater than the doping concentration of the first N-type doped region; a first groove is formed at the side of the second N-type doped region, and a P-type doped region is filled in the first groove; and a second groove is formed in the middle of the second N-type doped region, and polysilicon is filled in the second groove to form a gate region.
In one embodiment of the present utility model, the thickness of the P-type doped region along the deposition direction is consistent with the thickness of the second N-type doped region.
In one embodiment of the present utility model, the P-type doped region is a silicon carbide P-type doped region.
In one embodiment of the present utility model, the semiconductor device further includes a multi-ion region disposed on the second N-type doped region, wherein a third trench in straight line with the second trench is formed in the middle of the multi-ion region, and metal is filled in the third trench and connected with the polysilicon.
In one embodiment of the present utility model, the multi-ion region is located at both sides of the third trench to form a source region.
In one embodiment of the present utility model, the semiconductor device further comprises an oxide layer disposed on the multi-ion region, wherein a source electrode connected to the source electrode region and a gate electrode connected to the gate electrode region are disposed on the oxide layer.
In one embodiment of the utility model, the back side of the substrate is deposited with metal to form the drain.
In one embodiment of the utility model, the substrate is a silicon carbide substrate.
In one embodiment of the present utility model, the second N-type doped region is etched to obtain the first trench and the second trench.
Compared with the prior art, the technical scheme of the utility model has the following advantages:
the utility model relates to a trench gate field effect transistor, which comprises a substrate; a first N-type doped region deposited on the substrate; a second N-type doped region deposited on the first N-type doped region, the second N-type doped region having a doping concentration greater than the doping concentration of the first N-type doped region; a first groove is formed at the side of the second N-type doped region, and a P-type doped region is filled in the first groove; a second groove is formed in the middle of the second N-type doped region, and polysilicon is filled in the second groove to form a gate region; compared with the prior art, the P-type doped region is formed in the second N-type doped region, a part of the second N-type doped region is replaced, the on-resistance of the second N-type doped region is effectively reduced, the conductivity of the transistor is improved, meanwhile, the on-resistance of the second groove can be reduced due to the arrangement mode of the gate region, and when electrons pass through the second N-type doped region, heat generation is effectively reduced, and the power consumption of the transistor is reduced.
Drawings
In order that the utility model may be more readily understood, a more particular description of the utility model will be rendered by reference to specific embodiments thereof that are illustrated in the appended drawings, in which
Fig. 1 is a schematic diagram of a trench gate silicon carbide field effect transistor in accordance with a preferred embodiment of the present utility model.
Fig. 2 is a schematic diagram of a trench gate field effect transistor according to a preferred embodiment of the present utility model.
Fig. 3 is a schematic structural diagram of a trench gate field effect transistor according to a preferred embodiment of the present utility model.
Description of the specification reference numerals: 1. a drain electrode; 2. a substrate; 3. a first N-type doped region; 4. a second N-type doped region; 5. an oxide layer; 6. a P-type doped region; 7. a P-type doped region; 8. a second trench; 9. a P-type doped region; 10. a third trench; 11. a channel; 12. a multi-ion region; 13. a source region; 14. a gate; 15. a source electrode; 18. a first trench; 19. a first trench; 20. a first trench; 21. a P-region; 22. an n+ region.
Detailed Description
The present utility model will be further described with reference to the accompanying drawings and specific examples, which are not intended to be limiting, so that those skilled in the art will better understand the utility model and practice it.
Examples
Referring to fig. 1 to 3, a trench gate field effect transistor of the present utility model includes a substrate 2; the substrate 2 is composed of silicon carbide and nitrogen ions, and the substrate 2 has good conductivity.
The first N-type doped region 3 is deposited on the substrate 2, the first N-type doped region 3 is composed of silicon carbide and nitrogen ions, the concentration of the silicon carbide and the nitrogen ions is higher than that of the substrate 2, and the first N-type doped region 3 has good conductivity.
A second N-type doped region 4, which is formed of silicon carbide and nitrogen ions and has good conductivity, is deposited on the first N-type doped region 3, and has a doping concentration of the second N-type doped region 4 greater than that of the first N-type doped region 3; the first trenches 20 are formed at two sides of the second N-type doped region 4, and the P-type doped region 9,P-type doped region 9 filled in the first trenches 20 is composed of silicon carbide and aluminum ions, so that the on-resistance of the second N-type doped region 4 can be further reduced; the second trench 8 is formed in the middle of the second N-type doped region 4, and the second trench 8 is filled with polysilicon to form a gate 14 region, wherein the polysilicon has inactive chemical properties and lower on-resistance compared with metal.
The thickness of the P-type doped region 9 along the deposition direction is consistent with the thickness of the second N-type doped region 4, the P-type doped region 9 can reduce the space occupied by the second N-type doped region 4, change the distribution of the electric field of the second N-type doped region 4, further reduce the on-resistance of the second N-type doped region 4, the second N-type doped region 4 is provided with a channel 11, the channel 11 is arranged between the two P-type doped regions 9, and current flows through the channel 11.
The P-type doped region 9 is a silicon carbide P-type doped region 9, the silicon carbide P-type doped region 9 mainly comprises silicon carbide and aluminum ions, and the silicon carbide P-type doped region 9 can reduce the on-resistance of the second N-type doped region 4 and improve the conductivity of the P-type doped region 9.
The semiconductor device further comprises a multi-ion region 12 arranged on the second N-type doped region 4, a third groove 10 which is communicated with the second groove 8 in a straight line is formed in the middle of the multi-ion region 12, metal is filled in the third groove 10 and connected with the polysilicon, and the voltage is connected with the metal.
The multi-ion region 12 is located at two sides of the third trench 10 to form a source 15 region 13, and current flows into the source 15.
The semiconductor device further comprises an oxide layer 5 arranged on the multi-ion region 12, the main component of the oxide layer 5 is silicon dioxide, the silicon dioxide has stable chemical properties and low on-resistance, the oxide layer 5 is used for isolating substances on two sides, a source electrode 15 connected with the source electrode 15 region 13 is arranged on the oxide layer 5, a grid electrode 14 connected with the grid electrode 14 region is arranged on the oxide layer 5, and the grid electrode 14 is connected with voltage.
The back side of the substrate 2 is deposited with metal to form a drain electrode 1 which is connected to a voltage, and an electric field is formed between the drain electrode 1 and a gate electrode 14.
The gate 14 is connected to a voltage, the gate 14 is composed of a first trench 20 and polysilicon placed in the first trench 20, the polysilicon has a better on-resistance than metal, the first trench 20 is obtained by etching in the second N-type doped region 4, and multiple ion regions 12 are disposed at two sides of the gate 14.
The channel 11 is a channel defined by the multi-ion region 12 and the P-type doped region 9 in the second N-type doped region 4, the second N-type doped region 4 is respectively connected with the drain electrode 1 and the source electrode 15, the gate 14 contacts the channel 11, compared with the planar gate which does not contact the channel 11, the channel 11 has the characteristic of small area, and further the on-resistance of the gate 14 itself can be reduced, when the gate 14 and the drain electrode 1 are electrified with voltage, an electric field is formed, so that electrons move from the P-region 21 and the n+ region 22 of the multi-ion region 12 to the drain electrode 1, and current sequentially passes through the multi-ion region 12 and the channel 11 from the drain electrode 1 to the source electrode 15.
The multi-ion region 12 includes a P-region 21 of a first conductivity type and an n+ region 22 of a second conductivity type, the P-region 21 and the n+ region 22 being obtained by injecting energetic particles into the multi-ion region 12, the first conductivity type and the second conductivity type being opposite in electrical property, the P-region 21 being larger than the n+ region 22, the P-region 21 and the n+ region 22 being operative to form a conductive channel 11 on an oxidized surface after the gate 14 is electrically connected to the drain 1, the conductive channel 11 being operative to pass electrons when the voltage is removed, the conductive channel 11 being vanished.
The substrate 2 is a silicon carbide substrate 2, which is formed by doping silicon carbide with nitrogen ions, the silicon carbide substrate 2 is arranged between the drain electrode 1 and the first N-type doped region 3, the silicon carbide substrate 2 and metal deposited on the back of the silicon carbide substrate form the drain electrode 1, electrons enter the silicon carbide substrate 2 after leaving the first N-type doped region 3 and then enter the drain electrode 1, and the silicon carbide substrate 2 has good wear resistance, heat dissipation and corrosion resistance, can keep stability under the condition of complex external environment and continuously and normally works.
The second N-type doped region 4 is etched to obtain the first trench 20 and the second trench 8, and the second trench 8 spans the second N-type doped region 4 and the multi-ion region 12.
The doping concentration of the second N-type doped region 4 is higher than that of the first N-type doped region 3, the doping concentration of the first N-type doped region 3 ensures that the breakdown voltage is not small, and the alternating use of the second N-type doped region 4 and the P-type doped region 9 can reduce the on-resistance of the transistor.
The working principle of the trench gate field effect transistor of the utility model is as follows:
when the multi-ion-source-drain electrode structure works, negative voltage is connected to the grid electrode 14, an electric field is formed between the grid electrode 14 and the drain electrode 1 after positive voltage is connected to the drain electrode 1, the electric field is formed between the grid electrode 14 and the drain electrode 1, a depletion region is formed on the surface of the oxide layer 5 of the multi-ion region 12 due to the voltage, a conductive channel 11 is formed in the depletion region, electrons are emitted from the P-region 21 and the N+ region 22, pass through the conductive channel 11, and sequentially pass through the multi-ion region 12, the second N-type doped region 4, the channel 11, the first N-type doped region 3, the substrate 2 and reach the drain electrode 1; the P-type doped region 9 is arranged at two sides of the channel 11 and is formed by mixing aluminum ions and silicon carbide, and the P-type doped region 9 replaces a part of the second N-type doped region 4, so that the on-resistance of the silicon carbide is further reduced, the conductivity and short circuit prevention capability of the transistor are improved, and the power consumption of the transistor is further reduced.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations and modifications of the present utility model will be apparent to those of ordinary skill in the art in light of the foregoing description. It is not necessary here nor is it exhaustive of all embodiments. And obvious variations or modifications thereof are contemplated as falling within the scope of the present utility model.
Claims (9)
1. A trench gate field effect transistor, comprising,
a substrate;
a first N-type doped region deposited on the substrate;
a second N-type doped region deposited on the first N-type doped region, the second N-type doped region having a doping concentration greater than the doping concentration of the first N-type doped region; a first groove is formed at the side of the second N-type doped region, and a P-type doped region is filled in the first groove; and a second groove is formed in the middle of the second N-type doped region, and polysilicon is filled in the second groove to form a gate region.
2. The trench-gate field effect transistor of claim 1, wherein the thickness of the P-type doped region in the deposition direction is consistent with the thickness of the second N-type doped region.
3. A trench-gate field effect transistor according to claim 1 or 2 wherein the P-type doped region is a silicon carbide P-type doped region.
4. The trench-gate field effect transistor of claim 1, further comprising a multi-ion region disposed on the second N-type doped region, wherein a third trench in linear communication with the second trench is formed in a middle portion of the multi-ion region, and wherein the third trench is filled with metal and is connected to the polysilicon.
5. The trench-gate field effect transistor of claim 4, wherein the multi-ion region forms source regions on opposite sides of the third trench.
6. The trench-gate field effect transistor of claim 5, further comprising an oxide layer disposed over the multi-ion region, wherein a source electrode is disposed over the oxide layer and coupled to the source region, and wherein a gate electrode is disposed over the oxide layer and coupled to the gate region.
7. The trench-gate field effect transistor of claim 1 wherein the back side of the substrate is deposited with metal to form the drain.
8. The trench-gate field effect transistor of claim 1, wherein the substrate is a silicon carbide substrate.
9. The trench-gate field effect transistor of claim 1, wherein the second N-type doped region is etched to obtain the first trench and the second trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223597748.3U CN219180516U (en) | 2022-12-30 | 2022-12-30 | Trench gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223597748.3U CN219180516U (en) | 2022-12-30 | 2022-12-30 | Trench gate field effect transistor |
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| Publication Number | Publication Date |
|---|---|
| CN219180516U true CN219180516U (en) | 2023-06-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223597748.3U Active CN219180516U (en) | 2022-12-30 | 2022-12-30 | Trench gate field effect transistor |
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| CN (1) | CN219180516U (en) |
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- 2022-12-30 CN CN202223597748.3U patent/CN219180516U/en active Active
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