CN218957727U - 半导体器件 - Google Patents

半导体器件 Download PDF

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Publication number
CN218957727U
CN218957727U CN202221986369.0U CN202221986369U CN218957727U CN 218957727 U CN218957727 U CN 218957727U CN 202221986369 U CN202221986369 U CN 202221986369U CN 218957727 U CN218957727 U CN 218957727U
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semiconductor die
conductive
die
semiconductor
pair
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CN202221986369.0U
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M·德桑塔
M·阿莱西
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STMicroelectronics SRL
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STMicroelectronics SRL
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Abstract

本实用新型的各个实施例涉及半导体器件。引线框包括管芯焊盘，管芯焊盘上布置有第一半导体管芯，其中导电带在第一半导体管芯上延伸。第一半导体管芯位于引线框和导电带中间。第二半导体管芯被安装在导电带上，用于在同一管芯焊盘上提供第二半导体管芯和第一半导体管芯的堆叠布置，其中至少一个导电带在第一半导体管芯和第二半导体管芯中间。封装尺寸减小因此可以在不明显影响器件组装流程的情况下实现。

Description

半导体器件
技术领域
本说明书涉及半导体器件。
一个或多个实施例可以有利地应用于功率半导体器件。
背景技术
在各种功率半导体器件(包括例如，方形扁平无引脚(QFN)封装中的功率半导体器件)中，一个或多个功率集成电路芯片或管芯与驱动器集成电路芯片或者例如使用BCD(Bipolar-CMOS-DMOS)技术制造的芯片并排布置。
这些芯片(或管芯：术语“芯片”和“管芯”在本文中用作同义词)可以被安装在引线框中的相应相邻管芯焊盘或焊垫(paddle)上。
引线键合(wire bonding)被用于提供管芯到管芯或管芯到引线框的连接(例如，信号、接地)，并且被楔形键合到引线框引线的所谓“带”被用于提供适合承载高电流的导线或路径。
在这样的布置中，用于安装各种电源和驱动器芯片或管芯的不同管芯焊盘或焊垫占据了大量的衬底(引线框)空间。
本领域需要为适当地处理这样的问题做出贡献。
实用新型内容
鉴于上述问题，本实用新型旨在提供一种半导体器件，该半导体器件具有更小的尺寸，从而减少在衬底上的占用空间。
根据本公开的一个或多个方面，提供了一种器件，包括：衬底，包括管芯焊盘，管芯焊盘上布置有至少一个第一半导体管芯，其中至少一个导电带在至少一个第一半导体管芯上延伸，其中至少一个第一半导体管芯位于衬底和至少一个导电带中间，以及至少一个第二半导体管芯，在至少一个导电带上，以在管芯焊盘上提供至少一个第二半导体管芯和至少一个第一半导体管芯的堆叠布置，其中至少一个导电带在至少一个第一半导体管芯和至少一个第二半导体管芯中间。
在一个或多个实施例中，至少一个第一半导体管芯包括在衬底上布置的相邻第一半导体管芯对；至少一个导电带包括导电带对，每个导电带在第一半导体管芯中的一个第一半导体管芯上延伸；第一半导体管芯中的每个第一半导体管芯位于衬底和导电带对中的相应导电带中间；以及至少一个第二半导体管芯桥状地跨过导电带对中的导电带进行附接，以提供至少一个第二半导体管芯的堆叠布置，其中导电带对中的每个导电带在第一半导体管芯中的相应的一个第一半导体管芯和第二半导体管芯的一个端部中间。
在一个或多个实施例中，用于将至少一个第二半导体管芯桥状地跨过导电带对中的导电带进行附接的导电附接材料。
在一个或多个实施例中，导电带对中的导电带通过至少一个第二半导体管芯相互电耦接。
在一个或多个实施例中，至少一个导电带具有波浪形图案，其中导电带中具有至少一个平坦部分，其中至少一个第二半导体管芯被附接到导电带中的至少一个平坦部分。
在一个或多个实施例中，半导体器件还包括：另一管芯焊盘，被提供在衬底中与管芯焊盘相邻；以及至少一个第三半导体管芯，被附接在另一管芯焊盘上。
在一个或多个实施例中，半导体器件还包括：第一导线键合图案，在至少一个第二半导体管芯和至少一个第一半导体管芯的堆叠布置中将至少一个第一半导体管芯和至少一个第二半导体管芯相互耦接。
在一个或多个实施例中，半导体器件还包括：第二导线键合图案，将至少一个第一半导体管芯与衬底中围绕管芯焊盘提供的导电结构阵列中的导电结构耦接。
在一个或多个实施例中，半导体器件还包括：第三导线键合图案，将至少一个第二半导体管芯与衬底中围绕管芯焊盘提供的导电结构阵列中的导电结构耦接。
在一个或多个实施例中，至少一个导电带包括在至少一个第一半导体管芯上延伸的导电带对；至少一个第一半导体管芯位于衬底和导电带对中间；以及至少一个第二半导体管芯桥状地跨过导电带对中的导电带进行附接，以提供至少一个第二半导体管芯的堆叠布置，其中导电带对中的每个导电带在至少一个第一半导体管芯和至少一个第二半导体管芯中间。
在一个或多个实施例中，半导体器件还包括用于将所述至少一个第二半导体管芯桥状地跨过所述导电带对中的所述导电带进行附接的导电附接材料。
一个或多个实施例涉及对应的半导体器件。诸如包括多个相互耦接的半导体集成电路芯片或管芯的功率器件的半导体器件可以是这样的器件的示例。
一个或多个实施例涉及通过使用用于附接的一个或多个带状区段，将至少一个管芯(例如，驱动器或控制器管芯)堆叠到另一管芯 (例如，功率管芯)上。
通过这种方式，整体封装高度(略微)增加，而增加量在很大程度上被封装占用空间的显著减少所补偿。这可能使得更小的引线框、更小的封装以及最终安装到诸如印刷电路板(PCB)的衬底上的占用空间减少。
因此一个或多个实施例依赖于出人意料的认识，诸如通常用于在半导体功率器件中提供电流通道或路径的带足够牢固来充分支撑附接在其上的一个或多个半导体芯片。
一个或多个实施例提供以下优点中的一个或多个：与现有导线键合机的兼容性；提供了即插即用工艺，其中组装步骤的数量保持基本不变；广泛适用于多种引线框封装；封装尺寸减小；由于封装尺寸减小而节省成本；以及由于能够根据期望规格定制导线和带，因此具有选择性。
正如在包括堆叠芯片的布置中的情况一样，通过使用布置在其之间的带作为支撑结构，某个芯片(例如，较小的芯片)可以被放置在至少另一个芯片的“顶部”。
一个或多个实施例因此有助于减小半导体芯片封装的总体X尺寸和Y尺寸，并具有在制造半导体器件中利用管芯键合、导线键合和带键合(加上芯片或管芯堆叠)的可能协同组合的能力。
附图说明
现在将参考附图，仅通过示例的方式来描述一个或多个实施例，其中：
图1和图2是包括多个半导体芯片的半导体器件的平面图，多个半导体芯片被布置在具有提供功率连接通道或路径的带的衬底上；
图3是根据本说明书的实施例的半导体器件的平面图；
图4是根据本说明书的实施例的另一半导体器件的平面图；
图5是根据本说明书的实施例的又一半导体器件的平面图；
图6是根据本说明书的实施例的又一半导体器件的平面图；以及
图7是图6所示示例的可能变型的示例性平面图。
具体实施方式
除非另有指示，否则不同附图中对应的附图标记通常指代对应的部分。
附图被绘制来清楚地图示实施例的相关方面并且不一定按比例绘制。
图中绘制的特征边缘不一定指示特征范围的终止。
在随后的描述中，图示了各种具体细节来提供对根据本说明书的实施例的各种示例的深入理解。实施例可以在没有一个或多个具体细节的情况下获得，或者利用其他方法、部件、材料等来获得。在其他情况下，未详细图示或描述已知的结构、材料或操作，使得实施例的各个方面不会被模糊。
在本说明书的框架中对“实施例”或“一个实施例”的引用意在指示与实施例有关的描述的特定配置、结构或特性被包括在至少一个实施例中。因此，可能出现在本说明书的各个点中的诸如“在实施例中”、“在一个实施例中”等的短语不一定完全指代同一实施例。此外，特定的配置、结构或特性可以在一个或多个实施例中以任何适当的方式组合。
本文中使用的标题/附图标记仅是为了方便而提供，并且因此不限定保护范围或实施例的范围。
如图1和图2中例示的半导体器件10可以包括多个半导体集成电路芯片(或管芯)C1、C2，无论它们的数量和功能如何，它们均被布置在诸如引线框的衬底12中的相应相邻管芯焊盘或焊垫12A处。
名称“引线框”(或“引线框架”)目前(例如参见美国专利商标局的USPC综合词汇表)用于指示为集成电路芯片或管芯提供支撑的金属框架以及将管芯或芯片中的集成电路与其他电气部件或接触部互连的电引线。
本质上，引线框包括导电结构(引线)12B的阵列，其从轮廓位置沿半导体芯片或管芯的方向向内延伸，从而从一个或多个管芯焊盘或焊垫12A形成导电结构阵列，导电结构阵列被配置为其上附接有至少一个半导体芯片或管芯。
至少一个半导体芯片或管芯到管芯焊垫的附接可以经由诸如管芯附接粘合剂(例如，管芯附接膜或DAF)的已知材料来进行。
引线框通常使用诸如光刻技术的技术来创建。使用该技术，箔或带形式的金属(例如，铜)材料在顶部侧和底部侧被蚀刻以创建各种焊盘和引线。
诸如引线框的衬底有利地以预模制形式提供，其中绝缘树脂(例如，环氧树脂)填充管芯焊盘12A和引线12B之间的空白空间。
因此经预模制的引线框12是基本上平坦的层状衬底，其中经预模制的材料(树脂)填充引线框的导电结构(例如，由诸如铜的金属材料制成)中的空间，导电结构已被例如通过蚀刻，在成型期间被赋予了包括空白空间的经雕刻的外观。
经预模制的引线框的总厚度与经雕刻的导电结构的厚度相同。
在图1和图2中，附图标记14指示所谓的“带”(即，导电材料的窄条带，铜可以是这种材料的示例)，“带”提供在功率管芯 C2之上延伸并且被配置为将电流从功率管芯C2传输到一个或多个电气负载(图中不可见)的导电线。
如图1和图2所示，带14可以呈现有助于借助超声键合进行焊接的波浪形(波状)图案。
图1和图2中例示的功率封装包括至少两个芯片或管芯。
这些可以包括例如一个或多个“功率”管芯C2，其提供器件10 的功率区段；以及至少一个较小的管芯C1，其用作控制器并且被连接到一个或多个功率管芯C2和衬底(引线框)12中的外部引线12B 两者。
如前所述，诸如14的带主要用于“重型”线，而一个或多个控制器管芯C1通常使用细导线进行导线键合。
在如图1和图2所示的常规布置中，每个管芯C1、C2被布置在相应的管芯焊垫12A上。
因此，最终封装尺寸由提供以用于承载管芯C1、C2的管芯焊垫的数量和尺寸来支配。
从封装的角度来看，随着管芯数量的增加，这会转化为更大的封装尺寸，就像目前包括多管芯封装的功率应用一样。
换言之，在图1和图2所示的布置中，其中管芯C1、C2彼此相邻布置，管芯C1、C2数量的增加导致需要更多的空间和更大的器件封装的X尺寸和Y尺寸，其中最终封装尺寸不可避免地增加。
以一种互补的方式，引线框中可用的管芯安装位置的数量与单个管芯的尺寸直接相关，并且只有在存在较小尺寸的管芯时，引线框中才有更多的位置可用。
如果管芯尺寸更小，则引线框中的可用位置可以增加，但仍受到与每个器件的管芯数量相关的器件封装尺寸的限制。
最终封装成本与封装尺寸相关。
堆叠芯片或管芯的可能性(例如，通过将较小的管芯堆叠在较大管芯的“顶部”)在本领域中是众所周知的。
另一方面，查看图1和图2并考虑例如将管芯C1堆叠在管芯C2 或管芯C2中的一个上，将必然得出结论，在管芯C2之上延伸的带 14不利于这种解决方案。
如果考虑在带14赋予用于促进其键合(例如，借助超声键合) 的一般波浪图案，情况尤其如此。
与这样的预期相反，发明人发现用于制造如图1和图2中所示的功率半导体器件的带14可以变得足够牢固(刚性和耐久)，以用作半导体管芯(诸如驱动管芯C1)的安装表面。
如果(如从图3开始的图中所示)用于在其上安装管芯C1的带 14或带14中的每一个被成形(以带键合领域技术人员已知的其他方式)为如图3至图7中的14A处所例示的平坦表面，则情况尤其如此。
再次注意，贯穿这些附图，与已结合图1和图2讨论的部分或元件类似或相似的部分或元件使用相同的附图标记来指示：为简洁起见，将不重复对应的详细描述。
图3图示了在这样的平坦的带表面14A上安装(附接)较小的集成电路管芯(诸如控制器管芯C1)的可能性。
这可以经由本领域技术人员已知的常规附接材料(“胶合剂”) 发生。
图3图示了能够完全容纳在单个带14中提供的平坦表面14A之上的较小尺寸的管芯C1。
通过将图3与图1进行比较，可能会注意到，随着带14中的一个带上安装的管芯C1依次在一个或多个管芯C2之上延伸，如图3 所示，在图1中容纳管芯C1(包括图右侧的管芯焊盘12A)的衬底 (引线框)12的一部分不再用于安装管芯C1。
衬底(引线框)12的该部分可以被消除或用于结合图7所讨论的另一目的。
图4例示了在带14上布置(附接)的管芯C1的尺寸不是严格结合(binding)的，因为如虚线轮廓所示的C1(例如，相对较大的) 管芯可以“横跨(astride)”安装或“桥状”跨过两个相邻的带14(例如，在两个相应的平坦部分14A之间)。
诸如C1的管芯可以使用诸如胶合剂或胶带的附接材料而被键合在带14的顶部，根据期望的应用，附接材料可以是导电的或不导电的。
如图4中例示的桥状安装可以被采用(例如，使用导电材料来将管芯C1附接到带14上)来创建将两个相邻带14耦接的导电路径。这样的布置在于2022年6月24日提交的美国专利申请号17/848,958 中公开(其要求于2021年6月30日提交的意大利专利申请102021000017207的优先权)，该公开内容通过引用而被并入。相邻带还可以与两个不同的管芯C2a和C2b相关联(通常如箭头所示)。换言之，相邻的半导体管芯对C2a和C2b被布置有导电带对14，这样的一个导电带在半导体管芯中对应的一个半导体管芯上延伸。然后半导体管芯C1桥状地跨过所述导电带对中的所述导电带进行附接。然后半导体管芯C2a、C2b中的每一个管芯位于衬底和导电带对中的相应导电带中间。
图5是在两个(不一定是相邻的)带14的相应附接表面14A上安装多个管芯C1的可能示例。
无论采用何种布置来附接，图3至图5所示的解决方案图示了(通过与图1和图2的直接比较)显著减小最终封装的整体X尺寸和Y 尺寸的可能性。
该尺寸减小有利于增加特定引线框12上的可用封装位置的数量，并有可能降低最终封装成本。
图6和图7的比较例示了该可能性。
图6图示了通过“消除”图1中衬底(引线框)12的右侧部分，在两个带14之间跨接或桥状附接管芯C1(沿例如图4的线)并利用经由堆叠芯片C1和C2实现的空间优势来提供器件封装的总体减少的可能性。
图7是采用经由堆叠芯片C1和C2而实现的空间优势来保持图1 中衬底(引线框)12的右侧部分并在虚线轮廓中采用衬底12的该部分来安装一个或多个附加芯片或管芯(如附图标记C3所示)的可能性的示例。
基本上类似的方法可以被应用于图2的布置，其中图左侧上的被安装在一个或多个带14上的管芯C1“闲置”的位置可能被用于安装另一管芯。
此外，图6是经由常规导线键合16而将控制器管芯C1电耦接到功率管芯C2的可能性的示例。
图7图示了除该可能性之外的可能性：经由进一步的导线键合18 将功率管芯C2电耦接到引线框中的外部引线12B；并且经由另外的导线键合20将控制器管芯C1电耦接到引线框中的外部引线12B。
应当理解，将管芯C1和C2称为控制器和功率管芯纯粹是示例性的：一个或多个实施例实际上可以与所涉及的芯片或管芯的性质和类型无关地进行应用。
尽管本文中已例示了诸如14的“功能性”带(即，旨在为器件 10提供高电流流动通道或路径的带)，但某些示例可以考虑提供“虚设”带(即，通过任何电连接本身不是必需的带)来便于在其上布置芯片或管芯，芯片或管芯可以以具有“功能性”带的桥状布置。这样的“虚设”带例如可以被用于封装中的另一功能，诸如散热。
发现目前用于在半导体功率器件中提供带的常规金属材料(例如，铝、铜或金)对于实施例来说是足够的，也就是说，足以生产足够牢固以支撑诸如其上安装的C1的半导体管芯的带，该带具有在其中形成诸如14A的平坦部分的能力。
本文中的示例对器件10的组装流程没有明显影响。
事实上，在一个或多个带(如先前形成，以根据需要提供功率线) 上进行管芯键合之后，导线键合过程(如图7的导线键合线16、18 和20所例示)可以被执行并继续进行其他组装步骤(模制和封装、单片化等)。
在不损害基本原理的情况下，细节和实施例可以在不脱离实施例的范围的情况下，相对于仅以示例方式描述的内容变化，甚至是显著变化。
权利要求是本文提供的关于实施例的技术教导的组成部分。
保护范围由所附权利要求确定。

Claims (11)

1.一种半导体器件，其特征在于，包括：
衬底，包括管芯焊盘，所述管芯焊盘上布置有至少一个第一半导体管芯，其中至少一个导电带在所述至少一个第一半导体管芯上延伸，其中所述至少一个第一半导体管芯位于所述衬底和所述至少一个导电带中间，以及
至少一个第二半导体管芯，在所述至少一个导电带上，以在所述管芯焊盘上提供所述至少一个第二半导体管芯和所述至少一个第一半导体管芯的堆叠布置，其中所述至少一个导电带在所述至少一个第一半导体管芯和所述至少一个第二半导体管芯中间。
2.根据权利要求1所述的器件，其特征在于：
其中所述至少一个第一半导体管芯包括在所述衬底上布置的相邻第一半导体管芯对；
其中所述至少一个导电带包括导电带对，每个导电带在所述第一半导体管芯中的一个第一半导体管芯上延伸；
其中所述第一半导体管芯中的每个第一半导体管芯位于所述衬底和所述导电带对中的相应导电带中间；以及
其中所述至少一个第二半导体管芯桥状地跨过所述导电带对中的所述导电带进行附接，以提供所述至少一个第二半导体管芯的堆叠布置，其中所述导电带对中的每个导电带在所述第一半导体管芯中的相应的一个第一半导体管芯和所述第二半导体管芯的一个端部中间。
3.根据权利要求1所述的器件，其特征在于，用于将所述至少一个第二半导体管芯桥状地跨过所述导电带对中的所述导电带进行附接的导电附接材料。
4.根据权利要求1所述的器件，其特征在于，所述导电带对中的所述导电带通过所述至少一个第二半导体管芯相互电耦接。
5.根据权利要求1所述的器件，其特征在于，所述至少一个导电带具有波浪形图案，其中所述导电带中具有至少一个平坦部分，其中所述至少一个第二半导体管芯被附接到所述导电带中的所述至少一个平坦部分。
6.根据权利要求1所述的器件，其特征在于，还包括：
另一管芯焊盘，被提供在所述衬底中与所述管芯焊盘相邻；以及
至少一个第三半导体管芯，被附接在所述另一管芯焊盘上。
7.根据权利要求1所述的器件，其特征在于，还包括：
第一导线键合图案，在所述至少一个第二半导体管芯和所述至少一个第一半导体管芯的所述堆叠布置中将所述至少一个第一半导体管芯和所述至少一个第二半导体管芯相互耦接。
8.根据权利要求1所述的器件，其特征在于，还包括：
第二导线键合图案，将所述至少一个第一半导体管芯与所述衬底中围绕所述管芯焊盘提供的导电结构阵列中的导电结构耦接。
9.根据权利要求1所述的器件，其特征在于，还包括：
第三导线键合图案，将所述至少一个第二半导体管芯与所述衬底中围绕所述管芯焊盘提供的导电结构阵列中的导电结构耦接。
10.根据权利要求1所述的器件，其特征在于：
其中所述至少一个导电带包括在所述至少一个第一半导体管芯上延伸的导电带对；
其中所述至少一个第一半导体管芯位于所述衬底和所述导电带对中间；以及
其中所述至少一个第二半导体管芯桥状地跨过所述导电带对中的所述导电带进行附接，以提供所述至少一个第二半导体管芯的堆叠布置，其中所述导电带对中的每个导电带在所述至少一个第一半导体管芯和所述至少一个第二半导体管芯中间。
11.根据权利要求10所述的器件，其特征在于，还包括用于将所述至少一个第二半导体管芯桥状地跨过所述导电带对中的所述导电带进行附接的导电附接材料。
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