CN218783035U - Three-dimensional packaging structure of power semiconductor module - Google Patents

Abstract

The utility model relates to a power semiconductor module technical field, concretely relates to power semiconductor module's three-dimensional packaging structure, including last DBC board and lower DBC board, the lower surface of going up the DBC board is connected with the first metal bridge of a plurality of and second chip of electricity in advance, down the DBC board with go up DBC board parallel arrangement, just the upper surface of DBC board is connected with the first chip of a plurality of and second metal bridge of electricity in advance down, first chip with first metal bridge one-to-one electricity is connected, the second metal bridge with second chip one-to-one electricity is connected. The utility model provides a three-dimensional packaging structure of power semiconductor module, reduced the mutual thermal interference of chip during operation, improved the radiating efficiency of module; meanwhile, the chip is in surface-to-surface contact connection with the DBC board through the metal bridge, so that stray inductance is reduced, internal resistance is reduced, and the use efficiency of electric energy is improved; in addition, the device also has the advantages of high space utilization rate, high power density and the like.

Description

Three-dimensional packaging structure of power semiconductor module

Technical Field

The utility model relates to a power semiconductor module technical field, concretely relates to power semiconductor module's three-dimensional packaging structure.

Background

The power semiconductor module or power module refers to a special power device which is manufactured by connecting a plurality of power semiconductor devices according to a certain circuit topological structure and integrating the power semiconductor devices in the same plastic package shell. Power semiconductor modules have been widely used in various power conversion fields because of their advantages such as small size, high reliability, and simplified design.

In the prior art, the packages of the power semiconductor modules are often completed on the same DBC (Direct Bonding coater) surface, and a heat dissipation device is arranged on the other DBC surface for heat dissipation, and the planar package structure has the following problems: 1. the number of chips on the same DBC surface in the power module is large, the positions are concentrated, and the heat dissipation effect is poor; 2. the chips are electrically connected in a bonding aluminum wire mode, the bonding aluminum wires are many and long, and the wire arrangement is complex, so that stray inductance in the module is high; 3. the reliability is often inconsistent when in use due to various differences such as connection conditions, and the bonding points with high heat generation often fall off first, so that the service life of the whole power module is shortened.

SUMMERY OF THE UTILITY MODEL

The utility model discloses a solve among the prior art power module packaging structure and have that chip quantity is many and the position concentrates the technical problem that leads to the radiating effect poor, provide a power semiconductor module's three-dimensional packaging structure, set up a plurality of chip dispersion on two upper and lower DBC boards, reduced each chip thermal interference each other, the radiating effect is good.

The technical scheme of the utility model:

a three-dimensional packaging structure of a power semiconductor module comprises:

the lower surface of the upper DBC board is electrically connected with a plurality of first metal bridges and a second chip in advance;

the lower DBC plate is arranged in parallel with the upper DBC plate, a plurality of first chips and second metal bridges are electrically connected to the upper surface of the lower DBC plate in advance, the first chips are electrically connected with the first metal bridges in a one-to-one correspondence mode, and the second metal bridges are electrically connected with the second chips in a one-to-one correspondence mode.

Further, the air conditioner is provided with a fan,

the lower surface of the upper DBC plate is in surface-to-surface contact and electrical connection with the first metal bridge, the first metal bridge is in surface-to-surface contact and electrical connection with the first chip, and the first chip is in surface-to-surface contact and electrical connection with the upper surface of the lower DBC plate;

the lower surface of the upper DBC plate is in surface-to-surface contact and electrical connection with the second chip, the second chip is in surface-to-surface contact and electrical connection with the second metal bridge, and the second metal bridge is in surface-to-surface contact and electrical connection with the upper surface of the lower DBC plate; the first chip and the second chip are uniformly distributed.

Further, the three-dimensional package structure further includes at least one NTC resistor, and the NTC resistor is disposed on the lower surface of the upper DBC board or the upper surface of the lower DBC board.

Furthermore, the three-dimensional package structure further includes a plurality of power terminals and signal terminals, and the plurality of power terminals and the plurality of signal terminals are cross-distributed and electrically connected to the lower surface of the upper DBC board and the upper surface of the lower DBC board.

Further, the upper DBC board includes a first upper surface metal layer, a first intermediate insulating layer, and a first lower surface metal layer; the lower DBC plate comprises a second upper surface metal layer, a second middle insulating layer and a second lower surface metal layer; and a Pinfin substrate is connected to the first upper surface metal layer or the second lower surface metal layer.

Furthermore, the three-dimensional packaging structure is filled with epoxy resin.

Furthermore, the first chip and the second chip are both integrated chips comprising an IGBT and an FWD.

Further, the circuit topology of the volumetric packaging structure comprises at least one half-bridge topology, wherein,

the upper chip in each half-bridge topology is the second chip and is configured on the lower surface of the upper DBC board, and the lower chip in each half-bridge topology is the first chip and is configured on the upper surface of the lower DBC board;

the lower surface of the upper DBC plate is provided with a first etching groove which separates the second chip from the first metal bridge; and a second etching groove is formed in the upper surface of the lower DBC plate, and separates the first chip and the second metal bridge in each half-bridge topological structure from the first chip and the second metal bridge in the adjacent half-bridge topological structure.

Furthermore, the lower surface of the upper DBC plate and the upper surface of the lower DBC plate are both provided with a plurality of grid signal terminals and grid etching grooves, the grid signal terminals are electrically connected with the grids of the corresponding second chip/first chip through aluminum wires, the grid etching grooves are arranged around the grid signal terminals in a one-to-one correspondence manner, the first metal bridge and the second metal bridge are both provided with notches, and the notches correspond to the grid arrangement of the second chip/first chip.

Furthermore, the circuit topology structure of the three-dimensional packaging structure is a three-phase bridge topology structure and comprises three half-bridge topology structures connected in parallel.

After the technical scheme is adopted, the utility model provides a pair of power semiconductor module's three-dimensional packaging structure compares with prior art, has following beneficial effect:

1. the utility model discloses become the spatial structure with traditional power semiconductor module's encapsulation from planar structure, all be equipped with the chip on two upper and lower DBC boards, the chip passes through the DBC board that metal bridge face-to-face contact electricity corresponds, and chip evenly distributed is between two upper and lower DBC boards, and furthest has reduced the mutual thermal interference condition of chip during operation, has greatly improved the radiating efficiency of module.

2. Aiming at the defects of the traditional aluminum wire bonding, the collector electrode of each chip in the utility model is electrically connected with the pattern on the corresponding DBC plate through the metal bridge, and the chips, the metal bridge and the DBC plate are all sintered or welded in a surface-to-surface contact manner, thus abandoning the traditional aluminum wire bonding mode, greatly increasing the flow area, and improving the reliability and the service life of the module; simultaneously, because traditional bonding aluminium silk is in large quantity and length is long, the utility model discloses use the metal bridge can greatly shorten the electric current route for the inside stray inductance of module diminishes, and makes the internal resistance reduce, has promoted the availability factor of electric energy.

3. The utility model discloses set up partial power terminal and/or signal terminal on last DBC board, set up another partial power terminal and/or signal terminal on the DBC board down, make full use of vertical space, improved module internal space utilization, overall structure is compacter, makes the module of power density than traditional packaging form promote greatly, accords with the expectation of the miniaturized development in market.

Drawings

Fig. 1 is a schematic view of an outline structure of a three-dimensional package structure according to a first embodiment;

fig. 2 is an exploded view of the three-dimensional package structure according to the first embodiment;

fig. 3 is a schematic cross-sectional view of a three-dimensional package structure according to a first embodiment;

fig. 4 is a schematic structural view of a lower surface of an upper DBC plate according to the first embodiment;

FIG. 5 is a schematic structural view of an upper surface of a lower DBC plate according to the first embodiment;

fig. 6 is a schematic circuit topology diagram of a three-dimensional package structure according to a first embodiment;

fig. 7 is a schematic circuit topology diagram of a second embodiment of the three-dimensional package structure;

fig. 8 is a schematic structural view of a lower surface of an upper DBC plate according to a second embodiment;

fig. 9 is a schematic structural view of an upper surface of a lower DBC plate according to a second embodiment;

fig. 10 is a schematic circuit topology diagram of a three-dimensional package structure according to a third embodiment;

fig. 11 is a schematic structural view of a lower surface of an upper DBC plate of the third embodiment;

fig. 12 is a schematic structural view of an upper surface of a lower DBC plate according to a third embodiment.

Wherein the content of the first and second substances,

an upper DBC plate 1, a first upper surface metal layer 101, a first intermediate insulating layer 102, a first lower surface metal layer 103; a first metal bridge 111, a second chip 112; a DC + power terminal 121, a DC-power terminal 122; an E4 signal terminal 131, an E5 signal terminal 132, an E6 signal terminal 133; r1 signal terminal 141, R2 signal terminal 142; g1 signal terminals 151, G2 signal terminals 152, G3 signal terminals 153; a first etching bath 161; gate etch trenches 171, aluminum wire 172;

a lower DBC plate 2, a second upper surface metal layer 201, a second intermediate insulating layer 202, a second lower surface metal layer 203; a first chip 211, a second metal bridge 212; u-phase power terminal 221, v-phase power terminal 222, w-phase power terminal 223; an E1 signal terminal 231, an E2 signal terminal 232, an E3 signal terminal 233; a G4 signal terminal 251, a G5 signal terminal 252, a G6 signal terminal 253; a second etching bath 261;

a Pinfin substrate 3;

and (4) plastic packaging the shell.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

In the description of the present invention, it should be understood that the directions or positional relationships indicated by the directional terms such as "front, back, upper, lower, left, right", "horizontal, vertical, horizontal" and "top, bottom", etc. are usually based on the directions or positional relationships shown in the drawings, and are only for convenience of description and simplification of the description, and in the case of not making a contrary explanation, these directional terms do not indicate and imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore, should not be construed as limiting the scope of the present invention; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and if not stated otherwise, the terms have no special meaning, and therefore, the scope of the present invention should not be construed as being limited.

The utility model aims at providing a three-dimensional packaging structure of power semiconductor module replaces the packaging structure of traditional planar, through two DBC boards about setting up to set up a plurality of chip and metal bridge on two DBC boards respectively, thereby make the increase of distance between the chip, and the radiating effect promotes. Meanwhile, the power supply has the advantages of compact structure, small occupied space, high power density, small internal resistance, small stray inductance, long service life, high use efficiency and the like. The following is a detailed description of the embodiments.

The first embodiment is as follows:

as shown in fig. 1 to 6, the present embodiment provides a three-dimensional package structure of a power semiconductor module, including an upper DBC board 1 and a lower DBC board 2, where the upper DBC board 1 and the lower DBC board 2 are both copper-clad ceramic substrates, the lower surface of the upper DBC board 1 is electrically connected to a plurality of first metal bridges 111 and a plurality of second chips 112 in advance by sintering or welding, and further, the lower DBC board 2 is disposed parallel to the upper DBC board 1, and the upper surface of the lower DBC board 2 is also electrically connected to a plurality of first chips 211 and a plurality of second metal bridges 212 in advance by sintering or welding, where the first chips 211 and the first metal bridges 111 are in one-to-one correspondence and are electrically connected to each other by welding, and the second metal bridges 212 and the second chips 112 are in one-to-one correspondence and are also electrically connected to each other by welding. The first metal bridge 111 and the second metal bridge 212 have a certain thickness, and simultaneously play a role of supporting and conducting electricity, and specific shapes thereof can be selected, but are not limited to blocks, columns and the like.

Thus, in the embodiment, two DBC boards, namely an upper DBC board 1 and a lower DBC board 2, are adopted, and the middle of the two DBC boards is supported and conducted through a metal bridge to form a three-dimensional packaging structure, so that compared with the existing planar packaging structure, the heat dissipation area is greatly increased, and the heat dissipation effect is better; in addition, in the present embodiment, a part of chips are disposed on the upper DBC board 1, and another part of chips are disposed on the lower DBC board 2, compared with the prior art, the chips are not concentrated on the same DBC board any more, the heat generation condition of the module is changed from single-point concentrated heat generation to multi-point distributed heat generation, and preferably, the first chip 211 and the second chip 112 can be uniformly and symmetrically disposed between the upper DBC board 1 and the lower DBC board 2, so that the mutual thermal interference condition of the chips during operation is reduced to the maximum extent, and the heat dissipation efficiency of the module is greatly increased.

As a preferred embodiment of this embodiment, the lower surface pattern of the upper DBC plate 1 is electrically connected to the first metal bridge 111 in a surface-to-surface contact manner (e.g. sintering or soldering, the same applies below), the first metal bridge 111 is electrically connected to the first chip 211 in a surface-to-surface contact manner, and the first chip 211 is electrically connected to the upper surface pattern of the lower DBC plate 2 in a surface-to-surface contact manner; similarly, the lower surface pattern of the upper DBC plate 1 is electrically connected to the second chip 112 in a surface-to-surface contact manner, the second chip 112 is electrically connected to the second metal bridge 212 in a surface-to-surface contact manner, and the second metal bridge 212 is electrically connected to the upper surface pattern of the lower DBC plate 2 in a surface-to-surface contact manner. Thus, aiming at the defects of the traditional aluminum wire bonding, the chip and the DBC plate are connected by the metal bridge, and the chip, the metal bridge and the DBC plate are sintered or welded in a surface-to-surface contact manner, so that the traditional connection mode of the aluminum wire bonding is abandoned, the flow area is greatly increased, and the reliability and the service life of the module are improved; meanwhile, as the traditional bonding aluminum wires are large in number and long in length, the current path can be greatly shortened by using the metal bridge, so that the stray inductance inside the module is reduced, the internal resistance is reduced, and the use efficiency of electric energy is improved.

As shown in fig. 3, the upper DBC board 1 includes a first upper surface metal layer 101, a first intermediate insulating layer 102 and a first lower surface metal layer 103, the first lower surface metal layer 103 electrically connects the first metal bridge 111 and the second chip 112, and the first upper surface metal layer 101 can directly dissipate heat or connect with a Pinfin substrate 3 (pin fin structure) for heat dissipation; the lower DBC plate 2 includes a second upper surface metal layer 201, a second intermediate insulating layer 202, and a second lower surface metal layer 203, the second upper surface metal layer 201 electrically connects the first chip 211 and the second metal bridge 212, and the second lower surface metal layer 203 can directly dissipate heat or connect the Pinfin substrate 3 for heat dissipation. Based on the three-dimensional package structure of the embodiment and the good heat dissipation effect brought by the surface-to-surface contact and electrical connection among the chip, the metal bridge and the DBC board, in the embodiment, the Pinfin substrate 3 can be welded and arranged only on the second lower surface metal layer 203, so that the overall volume of the module can be reduced. Further, a filler of a thermal molding material such as epoxy resin is filled in an upper region of the Pinfin substrate 3 to form the mold package 4.

The three-dimensional package structure of this embodiment further includes at least one NTC resistor, and the NTC resistor may be sintered on the lower surface of the upper DBC board 1 or the upper surface of the lower DBC board 2 for temperature detection or over-temperature protection.

Further, the three-dimensional packaging structure further comprises a plurality of power terminals and signal terminals, wherein the power terminals comprise input and output terminals of electric energy, the signal terminals comprise control terminals for controlling the on and off of each chip, detection terminals connected with NTC resistors and the like, and the power terminals and the signal terminals are welded on the lower surface of the upper DBC plate 1 and the upper surface of the lower DBC plate 2 in a cross distribution mode. In the conventional planar package structure, in order to secure an electrical distance, each terminal can be extended only along a horizontal length direction of the module; the three-dimensional packaging structure of the embodiment can be provided with a part of power terminals and/or signal terminals on the upper DBC board 1, and another part of power terminals and/or signal terminals on the lower DBC board 2, so that the vertical space is fully utilized, the overall structure of the module is more compact, the power density of the module is greatly improved, and the three-dimensional packaging structure accords with the expectation of market miniaturization development.

As a preferred embodiment of the present embodiment, the first chip 211 and the second chip 112 of the present embodiment are both integrated chips including IGBTs and FWDs, and are RC-IGBTs (reverse conducting chips), in each RC-IGBT chip, an emitter unit, a gate unit, and an anode unit of the corresponding FWD of each IGBT are located on the same side of the RC-IGBT chip, and a collector unit of each IGBT and a cathode unit of the corresponding FWD are located on the other side of the RC-IGBT chip.

As shown in fig. 6, the circuit of the three-phase package structure of the present embodiment is a three-phase bridge topology structure, which includes three half-bridge topologies connected in parallel, an upper chip in each half-bridge topology structure is the second chip 112 and is disposed on the lower surface of the upper DBC board 1, and a lower chip in each half-bridge topology structure is the first chip 211 and is disposed on the upper surface of the lower DBC board 2.

Specifically, corresponding to the three-phase bridge topology, as shown in fig. 4-5, three first metal bridges 111 and three second chips 112 are disposed on the lower surface of the upper DBC plate 1, one side of the three first metal bridges 111 is sintered or welded on the upper DBC plate 1, the other side of the three first metal bridges 111 is used for welding with the emitter of the first chip 211 on the lower DBC plate 2, and the collector of the first chip 211 is sintered or welded on the lower DBC plate 2; the collectors of the three second chips 112 are sintered or soldered on the upper DBC plate 1, the emitters of the three second chips 112 are used to be soldered with one side of the second metal bridges 212 on the lower DBC plate 2, and the other side of the second metal bridges 212 is sintered or soldered on the lower DBC plate 2. As shown in fig. 4, on the upper DBC board 1, there are further provided a DC + power terminal 121 electrically connected to the collector of the second chip 112 and a DC-power terminal 122 electrically connected to the first metal bridges 111, and E4, E5, and E6 signal terminals 131, 132, and 133 electrically connected to the three first metal bridges 111 in a one-to-one correspondence, and R1 and R2 signal terminals 141 and 142 electrically connected to both ends of the NTC resistor, and G1, G2, and G3 signal terminals 151, 152, and 153 electrically connected to the gates of the three second chips 112 in a one-to-one correspondence. Each terminal is bent in an L shape and extends out of the upper part of the module.

Further, as shown in fig. 4 to 5, three first chips 211 and three second metal bridges 212 are provided on the upper surface of the lower DBC plate 2, the collectors of the three first chips 211 are sintered or soldered on the lower DBC plate 2, and the emitters of the three first chips 211 are used for soldering with the first metal bridges 111 on the upper DBC plate 1; one side of the three second metal bridges 212 is sintered or soldered on the lower DBC plate 2 and the other side of the three second metal bridges 212 is used for soldering with the emitter of the second chip 112 on the upper DBC plate 1. As shown in fig. 5, on the lower DBC board 2, there are further provided an E1 signal terminal 231, an E2 signal terminal 232, an E3 signal terminal 233, a U-phase power terminal 221, a V-phase power terminal 222, and a W-phase power terminal 223 electrically connected to the collectors of the three first chips 211 in a one-to-one correspondence, and a G4 signal terminal 251, a G5 signal terminal 252, and a G6 signal terminal 253 electrically connected to the gates of the three first chips 211 in a one-to-one correspondence. Each terminal is bent in an L shape and extends out to the upper part of the module.

As shown in fig. 4, the present embodiment further provides a first etching groove 161 on the lower surface of the upper DBC plate 1 to separate three second chips 112 from three first metal bridges 111; the second etching bath 261 is disposed on the upper surface of the lower DBC plate 2 to separate the first chip 211 and the second metal bridge 212 in each half-bridge topology from the first chip 211 and the second metal bridge 212 in the adjacent half-bridge topology, so that the arrangement is more compact without affecting the electrical insulation between the chips by disposing the first etching bath 161 and the second etching bath 261.

Further, in the present embodiment, six gate etching grooves 171 are further disposed on the lower surface of the upper DBC plate 1 and the upper surface of the lower DBC plate 2, the six gate etching grooves 171 are correspondingly disposed around six gate signal terminals (i.e., the G1 signal terminal 151, the G2 signal terminal 152, the G3 signal terminal 153, the G4 signal terminal 251, the G5 signal terminal 252, and the G6 signal terminal 253) one by one, and each gate signal terminal is electrically connected to the gate of the corresponding second chip 112/first chip 211 through an aluminum wire 172. By providing the gate signal terminals, the arrangement can be made more compact without affecting the electrical insulation between each gate signal terminal and the peripheral circuit. In addition, a notch is further formed in the first metal bridge 111, and the notch corresponds to the gate of the first chip 211; the second metal bridge 212 is also provided with a gap corresponding to the gate of the second chip 112.

As can be seen from the above, the three-dimensional package structure of the power semiconductor module provided in this embodiment reduces the thermal interference between the chips during operation, and improves the heat dissipation efficiency of the module; meanwhile, the chip is connected with the DBC board through the metal bridge, so that stray inductance is reduced, internal resistance is reduced, and the use efficiency of electric energy is improved; in addition, the device also has the advantages of high space utilization rate, high power density and the like.

Example two:

the present embodiment provides a three-dimensional package structure of a power semiconductor module, and the main difference from the first embodiment is that the circuit topology of the module is different. As shown in fig. 7, the circuit topology of the present embodiment is a full-bridge topology, which includes two half-bridge topologies connected in parallel, an upper chip in each half-bridge topology is a second chip 112 and is disposed on the lower surface of the upper DBC board 1, and a lower chip in each half-bridge topology is a first chip 211 and is disposed on the upper surface of the lower DBC board 2.

Specifically, corresponding to the full-bridge topology, as shown in fig. 8-9, two first metal bridges 111 and two second chips 112 are disposed on the lower surface of the upper DBC plate 1, one side of the two first metal bridges 111 is sintered or welded on the upper DBC plate 1, the other side of the two first metal bridges 111 is used for welding with the emitter of the first chip 211 on the lower DBC plate 2, and the collector of the first chip 211 is sintered or welded on the lower DBC plate 2; the collectors of the two second chips 112 are sintered or soldered on the upper DBC plate 1, the emitters of the two second chips 112 are adapted to be soldered to one side of a second metal bridge 212 on the lower DBC plate 2, and the other side of the second metal bridge 212 is sintered or soldered on the lower DBC plate 2. As shown in fig. 8, on the upper DBC plate 1, there are further provided a DC + power terminal 121 electrically connected to the collector of the second chip 112 and a DC-power terminal 122 electrically connected to the first metal bridges 111, and E4 and E5 signal terminals 131 and 132 electrically connected to the two first metal bridges 111 in a one-to-one correspondence, and R1 and R2 signal terminals 141 and 142 electrically connected to both ends of the NTC resistor, and G1 and G2 signal terminals 151 and 152 electrically connected to the gates of the two second chips 112 in a one-to-one correspondence. Each terminal is bent in an L shape and extends out of the upper part of the module.

Further, as shown in fig. 9, on the lower DBC plate 2, there are provided an E1 signal terminal 231, an E2 signal terminal 232, a C1 power terminal 224, and a C2 power terminal 225 electrically connected to the collectors of the two first chips 211 in a one-to-one correspondence, and a G4 signal terminal 251 and a G5 signal terminal 252 electrically connected to the gates of the two first chips 211 in a one-to-one correspondence. Each terminal is bent in an L shape and extends out of the upper part of the module. The rest of the device is arranged according to the first embodiment and is not described in detail here.

Example three:

the present embodiment provides a three-dimensional package structure of a power semiconductor module, and the main difference between the three-dimensional package structure of the power semiconductor module and the first and second embodiments is that the circuit topology structure of the module is different. As shown in fig. 10, the circuit topology of the present embodiment is a half-bridge topology, in which the upper chip is the second chip 112 and is disposed on the lower surface of the upper DBC board 1, and the lower chip is the first chip 211 and is disposed on the upper surface of the lower DBC board 2.

Specifically, corresponding to the half-bridge topology, as shown in fig. 11-12, a first metal bridge 111 and a second chip 112 are disposed on the lower surface of the upper DBC board 1, one side of the first metal bridge 111 is sintered or soldered on the upper DBC board 1, the other side of the first metal bridge 111 is used for soldering with the emitter of the first chip 211 on the lower DBC board 2, and the collector of the first chip 211 is sintered or soldered on the lower DBC board; the collector of the second chip 112 is sintered or soldered on the upper DBC plate 1, the emitter of the second chip 112 is used to be soldered to one side of the second metal bridge 212 on the lower DBC plate 2, and the other side of the second metal bridge 212 is sintered or soldered on the lower DBC plate. As shown in fig. 11, on the upper DBC plate 1, there are further provided a DC + power terminal 121 electrically connected to the collector of the second chip 112 and a DC-power terminal 122 electrically connected to the first metal bridge 111, and an E4 signal terminal 131 electrically connected to the first metal bridge 111 correspondingly, and R1 and R2 signal terminals 141 and 142 electrically connected to both ends of the NTC resistor, and a G1 signal terminal 151 electrically connected to the gate of the second chip 112 correspondingly. Each terminal is bent in an L shape and extends out to the upper part of the module.

Further, as shown in fig. 12, an E1 signal terminal 231 and a C1 power terminal 224 electrically connected to the collector of the first chip 211, and a G4 signal terminal 251 electrically connected to the gate of the first chip 211 are provided on the lower DBC plate 2. Each terminal is bent in an L shape and extends out to the upper part of the module. The rest of the devices are arranged according to the first embodiment or the second embodiment, and the details are not described here.

Example four:

the present embodiment provides a three-dimensional package structure of a power semiconductor module, which is different from the first, second and third embodiments in the circuit topology structure of the module, and the circuit topology structure of the present embodiment includes more half-bridge topology structures, and the specific implementation manner thereof can be implemented by referring to the above embodiments in combination with the specific circuit topology structure, and details thereof are not described herein.

Example five:

in the present embodiment, compared with the first to fourth embodiments, the first to fourth embodiments adopt an IGBT power module formed by an IGBT + FWD, the power semiconductor module in the present embodiment is a MOSFET power module, that is, each IGBT + FWD chip in the foregoing embodiments is replaced by a MOSFET + FWD chip, and other specific embodiments refer to the foregoing embodiments, and detailed description thereof is omitted here.

Example six:

compared with the above embodiments, the power semiconductor module in this embodiment may be a diode power module, a thyristor power module, or other power modules.

In this embodiment, the DBC board comprises an upper DBC board and a lower DBC board, wherein a plurality of first metal bridges and a plurality of second chips are electrically connected to the lower surface of the upper DBC board in advance, a plurality of first chips and a plurality of second metal bridges are electrically connected to the upper surface of the lower DBC board in advance, the first chips are electrically connected to the first metal bridges in a one-to-one correspondence, the second metal bridges are electrically connected to the second chips in a one-to-one correspondence, and the upper DBC board and the lower DBC board are arranged in parallel. Similar with above-mentioned embodiment, adopt this kind to set up chip evenly distributed at last DBC board under with DBC board to and carry out the mode that the face-to-face contact is electrically connected through the metal bridge, can play good radiating effect equally, promote the radiating efficiency. Those skilled in the art will appreciate that the arrangement of specific devices, such as terminals, may be laid out in a corresponding circuit topology or may be implemented with reference to the above-described embodiments and will not be described in detail herein.

The above, only be the embodiment of the preferred of the present invention, but the protection scope of the present invention is not limited thereto, and any person skilled in the art is in the technical scope of the present invention, according to the technical solution of the present invention and the utility model, which are designed to be replaced or changed equally, all should be covered within the protection scope of the present invention.

Claims (10)

1. A three-dimensional packaging structure of a power semiconductor module is characterized by comprising:

the lower surface of the upper DBC plate (1) is electrically connected with a plurality of first metal bridges (111) and a second chip (112) in advance;

lower DBC board (2), lower DBC board (2) with go up DBC board (1) parallel arrangement, just the upper surface of lower DBC board (2) is connected with first chip (211) of a plurality of and second metal bridge (212) electrically in advance, first chip (211) with first metal bridge (111) one-to-one is connected, second metal bridge (212) with second chip (112) one-to-one is connected electrically.

2. The solid packaging structure of a power semiconductor module according to claim 1,

the lower surface of the upper DBC plate (1) is in surface-to-surface contact and electrical connection with the first metal bridge (111), the first metal bridge (111) is in surface-to-surface contact and electrical connection with the first chip (211), and the first chip (211) is in surface-to-surface contact and electrical connection with the upper surface of the lower DBC plate (2);

the lower surface of the upper DBC plate (1) is in surface-to-surface contact and electrical connection with the second chip (112), the second chip (112) is in surface-to-surface contact and electrical connection with the second metal bridge (212), and the second metal bridge (212) is in surface-to-surface contact and electrical connection with the upper surface of the lower DBC plate (2); the first chip (211) and the second chip (112) are uniformly distributed.

3. The three-dimensional packaging structure of power semiconductor module according to claim 1, further comprising at least one NTC resistor disposed on the lower surface of the upper DBC board (1) or the upper surface of the lower DBC board (2).

4. The three-dimensional packaging structure of power semiconductor module according to claim 1 or 3, further comprising a plurality of power terminals and signal terminals, wherein the power terminals and the signal terminals are cross-distributed and electrically connected to the lower surface of the upper DBC board (1) and the upper surface of the lower DBC board (2).

5. The three-dimensional packaging structure of a power semiconductor module according to claim 1, wherein the upper DBC board (1) comprises a first upper surface metal layer (101), a first intermediate insulating layer (102) and a first lower surface metal layer (103); the lower DBC plate (2) comprises a second upper surface metal layer (201), a second middle insulating layer (202) and a second lower surface metal layer (203); the first upper surface metal layer (101) or the second lower surface metal layer (203) is connected with a Pinfin substrate (3).

6. The three-dimensional packaging structure of a power semiconductor module according to claim 1, wherein the three-dimensional packaging structure is filled with epoxy resin.

7. The three-dimensional packaging structure of a power semiconductor module according to claim 1, wherein the first chip (211) and the second chip (112) are both integrated chips comprising an IGBT and an FWD.

8. The three-dimensional package structure of a power semiconductor module according to claim 7, wherein the circuit topology of the three-dimensional package structure comprises at least one half-bridge topology, wherein,

the upper chip in each half-bridge topology is the second chip (112) and is configured on the lower surface of the upper DBC board (1), the lower chip in each half-bridge topology is the first chip (211) and is configured on the upper surface of the lower DBC board (2);

the lower surface of the upper DBC plate (1) is provided with a first etching groove (161) which separates the second chip (112) from the first metal bridge (111); and a second etching groove (261) is formed in the upper surface of the lower DBC plate (2) and separates the first chip (211) and the second metal bridge (212) in each half-bridge topological structure from the first chip (211) and the second metal bridge (212) in the adjacent half-bridge topological structure.

9. The three-dimensional packaging structure of a power semiconductor module according to claim 8, wherein the lower surface of the upper DBC plate (1) and the upper surface of the lower DBC plate (2) are provided with a plurality of gate signal terminals and gate etching grooves (171), the gate signal terminals are electrically connected with the gates of the corresponding second chip (112)/first chip (211) through aluminum wires (172), and the gate etching grooves (171) are arranged around the gate signal terminals in a one-to-one correspondence; gaps are arranged on the first metal bridge (111) and the second metal bridge (212) and correspond to the grid electrodes of the second chip (112)/the first chip (211).

10. The solid packaging structure of the power semiconductor module according to claim 8 or 9, wherein the circuit topology of the solid packaging structure is a three-phase bridge topology, which includes three parallel half-bridge topologies.

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